SCAS103 − JANUARY 1990 − REVISED APRIL 1993
•
•
•
•
•
•
•
•
•
DW OR N PACKAGE
Inputs Are TTL-Voltage Compatible
Contains Four Flip-Flops with Double-Rail
Outputs
Clock Enable Latched to Avoid False
Clocking
Applications Include: Buffer/Storage
Registers, Shift Registers, Pattern
Generators
Flow-Through Architecture to Optimize
PCB Layout
Center-Pin VCC and GND Configurations to
Minimize High-Speed Switching Noise
EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity
at 125°C
Package Options Include Plastic Small
Outline Packages, and Standard Plastic
300-mil DIPs
(TOP VIEW)
1Q
2Q
2Q
GND
GND
GND
GND
3Q
3Q
4Q
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
1Q
CLKEN
1D
2D
VCC
VCC
3D
4D
CLK
4Q
description
These circuits are positive-edge-triggered D-type flip-flops with a clock-enable input.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse if CLKEN is low. Clock triggering occurs at a particular voltage level and
is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high
or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking
by transitions at the CLKEN input.
The 74ACT11379 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
CLKEN
CLK
D
Q
Q
H
L
X
X
Q0
Q0
↑
H
H
L
L
↑
L
L
H
X
L
X
Q0
Q0
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
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• DALLAS, TEXAS 75265
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POST OFFICE BOX 655303
POST OFFICE BOX 1443
1
SCAS103 − JANUARY 1990 − REVISED APRIL 1993
logic symbol†
CLKEN
CLK
1D
2D
3D
4D
19
12
18
logic diagram (positive logic)
G1
CLKN
19
IC2
20
2D
17
14
13
1
2
3
8
9
10
11
1Q
1Q
2Q
CLK
12
2Q
3Q
3Q
1D
4Q
4Q
2D
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
3D
18
17
14
20
C1
1
1D
2
C1
3
1D
8
C1
9
1D
4D
13
10
C1
11
1D
1Q
1Q
2Q
2Q
3Q
3Q
4Q
4Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
} Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
2
MIN
MAX
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
IOL
Dt/Dv
Low-level output current
TA
Operating free-air temperature
High-level input voltage
2
High-level output current
Input transition rise or fall rate
•
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•
UNIT
V
V
0.8
V
VCC
VCC
V
−24
mA
V
24
mA
0
10
ns/V
− 40
85
°C
SCAS103 − JANUARY 1990 − REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
4.5 V
4.4
4.4
5.5 V
5.4
5.4
4.5 V
3.94
3.8
IOH = − 24 mA
5.5 V
4.94
4.8
IOH = − 75 mA{
5.5 V
IOH = − 50 mA
A
VOH
IOL = 50 mA
A
VOL
II
ICC
DICC‡
TA = 25°C
TYP
MAX
VCC
IOL = 24 mA
MIN
MAX
UNIT
V
3.85
4.5 V
0.1
5.5 V
0.1
0.1
0.1
4.5 V
0.36
0.44
5.5 V
0.36
0.44
V
IOL = 75 mA{
VI = VCC or GND
5.5 V
5.5 V
± 0.1
±1
mA
VI = VCC or GND, IO = 0
5.5 V
8
80
mA
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
0.9
1
mA
1.65
Ci
VI = VCC or GND
5V
4
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
Clock frequency
tw
Pulse duration
tsu
0
Setup time, before CLK↑
Hold time, after CLK ↑
th
MIN
MAX
UNIT
0
100
MHz
100
CLK high
5
5
CLK low
5
5
Data
5
5
CLKEN high
3.5
3.5
CLKEN low
3.5
3.5
0
0
CLKEN inactive or active, data
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
Any Q or Q
CLK
TA = 25°C
MIN
TYP
MAX
MIN
100
125
100
2.2
5
6.6
2.2
7.4
3.1
7.2
9.8
3.1
11.2
MAX
UNIT
MHz
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
•
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
f = 1 MHz
TYP
UNIT
38
pF
3
SCAS103 − JANUARY 1990 − REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
3V
High-Level
Input
From Output
Under Test
1.5 V
1.5 V
0
tw
C L = 50 pF
(see Note A)
500 Ω
3V
Low-Level
Input
1.5 V
1.5 V
0
VOLTAGE WAVEFORMS
PULSE DURATIONS
LOAD CIRCUIT
3V
1.5 V
Input
3V
Timing
Input
(see Note B)
0
1.5 V
tPHL
tPLH
0
tsu
Data
Input
1.5 V
In-Phase
Output
th
VOH
50%
VOL
3V
1.5 V
tPLH
tPHL
1.5 V
0
Out-of-Phase
Output
(see Note C)
SETUP AND HOLD TIMES
50%
VOH
50%
50%
VOL
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74ACT11379DW
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
74ACT11379N
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
74ACT11379N
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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