SCAS236 − MARCH 1990 − REVISED APRIL 1993
•
•
•
•
•
•
•
DW OR NT PACKAGE
(TOP VIEW)
3-State Buffer-Type Outputs Drive Bus
Lines Directly
Asynchronous Clear
Flow-Through Architecture Optimizes PCB
Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
1CLK
1Q1
1Q2
1Q3
1Q4
GND
GND
GND
GND
2Q1
2Q2
2Q3
2Q4
2CLK
description
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
1OE
1CLR
1D1
1D2
1D3
1D4
VCC
VCC
2D1
2D2
2D3
2D4
2CLR
2OE
This dual 4-bit D-type edge-triggered flip-flop features 3-state outputs designed specifically for bus driving. This
makes these devices particularly suitable for implementing buffer registers, I/O ports, and working registers.
The flip-flops enter data on the low-to-high transition of the clock. The 74AC11874 has clear (1CLR and 2CLR)
inputs and noninverting outputs. Taking CLR low causes the four Q outputs to go low independently of the clock.
The 74AC11874 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLE
(each 4-bit flip-flop)
INPUTS
OE
CLR
CLK
D
OUTPUT
Q
L
L
X
X
L
L
H
↑
H
H
L
H
↑
L
L
L
H
L
X
Q0
H
X
X
X
Z
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
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#'$#1 "** (""!'#'$,
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1
SCAS236 − MARCH 1990 − REVISED APRIL 1993
logic symbol†
28
1OE
1CLK
1
27
1CLR
1D1
1D2
1D3
1D4
26
logic diagram, each quad flip-flop (positive logic)
OE
EN
C1
R
CLK
1D
1
2
25
3
24
4
5
23
1Q1
CLR
1Q2
R
C1
1Q3
D1
Q1
1D
1Q4
R
15
2OE
2CLK
14
16
2CLR
2D1
2D2
2D3
2D4
20
C1
EN
D2
C1
Q2
1D
R
1D
1
10
19
11
18
12
17
13
R
2Q1
C1
D3
2Q2
Q3
1D
2Q3
2Q4
R
C1
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
D4
Q4
1D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −ā 65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2
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•
SCAS236 − MARCH 1990 − REVISED APRIL 1993
recommended operating conditions
VCC
VIH
Supply voltage
VCC = 3 V
VCC = 4.5 V
High-level input voltage
VI
VO
3
5
5.5
0.9
1.35
VCC
VCC
0
VCC = 3 V
VCC = 4.5 V
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
V
1.65
0
High-level output current
V
V
VCC = 4.5 V
VCC = 5.5 V
Low-level input voltage
UNIT
3.85
Output voltage
IOL
MAX
3.15
Input voltage
IOH
NOM
2.1
VCC = 5.5 V
VCC = 3 V
VIL
MIN
V
V
−4
−24
VCC = 5.5 V
VCC = 3 V
−24
VCC = 4.5 V
VCC = 5.5 V
24
mA
12
mA
24
0
10
ns/V
−40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = − 50 µA
VOH
IOH = − 4 mA
TA = 25°C
MIN
TYP
MAX
MIN
3V
2.9
2.9
4.5 V
4.4
4.4
5.5 V
5.4
5.4
3V
2.58
2.48
3.8
MAX
V
4.5 V
3.94
IOH = − 24 mA
5.5 V
4.94
IOH = − 75 mA†
5.5 V
3V
0.1
0.1
IOL = 50 µA
4.5 V
0.1
0.1
5.5 V
0.1
0.1
4.8
3.85
3V
0.36
0.44
4.5 V
0.36
0.44
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA†
5.5 V
II
IOZ
VI = VCC or GND
VO = VCC or GND
5.5 V
± 0.1
±1
µA
5.5 V
± 0.5
±5
µA
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
5.5 V
8
80
µA
VOL
IOL = 12 mA
UNIT
IO = 0
5V
1.65
4.5
Co
VO = VCC or GND
5V
13.5
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
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•
V
pF
pF
3
SCAS236 − MARCH 1990 − REVISED APRIL 1993
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
Clock frequency
0
CLR low
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time after CLK↑
CLK high or low
Data
CLR inactive
Data
60
MIN
MAX
UNIT
0
60
MHz
4
4
8.3
8.3
3
3
1.5
1.5
1
1
ns
ns
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time after CLK↑
0
125
MIN
MAX
UNIT
0
125
MHz
CLR low
4
4
CLK high or low
4
4
Data
2
2
1.5
1.5
1
1
CLR inactive
Data
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPHL
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
60
CLK
Q
CLR
Q
tPZH
tPZL
OE
Q
tPHZ
tPLZ
OE
Q
MIN
MAX
60
UNIT
MHz
2.9
7.3
11
2.9
12.5
3.7
8.8
13.1
3.7
14.6
3.9
9.3
14
3.9
15.7
2.1
5.6
8.7
2.1
9.8
3.1
8.4
13.1
3.1
14.9
4
6.2
8.2
4
8.7
3.9
6.3
8.5
3.9
9
ns
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPHL
4
FROM
(INPUT)
TO
(OUTPUT)
CLK
Q
CLR
Q
tPZH
tPZL
OE
Q
tPHZ
tPLZ
OE
Q
•
TA = 25°C
MIN
TYP
MAX
MIN
125
125
UNIT
MHz
2.3
5.2
7.4
2.3
8.3
2.9
6.1
8.6
2.9
9.6
2.9
6.3
8.9
2.9
10
1.5
4
5.9
1.5
6.6
2.3
5.4
7.8
2.3
8.8
3.8
5.7
7.3
3.8
7.7
3.7
5.5
7.1
3.7
7.5
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•
MAX
ns
ns
ns
ns
SCAS236 − MARCH 1990 − REVISED APRIL 1993
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Outputs enabled
Power dissipation capacitance per flip-flop
Outputs disabled
CL = 50 pF,
TYP
31
f = 1 MHz
13
UNIT
pF
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
GND
CL = 50 pF
(see Note A)
S1
Open
2 × VCC
GND
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
500 Ω
tw
LOAD CIRCUIT FOR OUTPUTS
VCC
Input
50%
50%
0V
VCC
Timing Input
50%
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tsu
th
VCC
Data Input
50%
50%
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
(see Note B)
0V
Output
(see Note D)
tPHL
Output
Waveform 2
S1 at GND
(see Note C)
VOH
50% VCC
VOL
50% VCC
50%
0V
tPLZ
≈ VCC
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
50%
tPLH
50%
tPZL
VCC
50%
VCC
Output
Control
(low-level
enabling)
0V
50% VCC
tPZH
20% VCC
VOL
tPHZ
VOH
50% VCC
80% VCC
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
For testing pulse duration: tr = tf = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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5
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74AC11874DW
OBSOLETE
SOIC
DW
28
TBD
Call TI
Call TI
74AC11874NT
OBSOLETE
PDIP
NT
28
TBD
Call TI
Call TI
74AC11874NT
OBSOLETE
PDIP
NT
28
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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