PCA EPF8087G

High Speed LAN Interface Module
ELECTRONICS INC.
EPF8087G
• Optimized for ML 6673 •
• Recommended for 10/100, 100 BX, 155 Mb/s applications •
(requiring 1:1 magnetics)
• Guaranteed to operate with 8 mA DC Bias •
• Complies with or exceeds IEEE 802.3, 10 BT/100 BX Standards •
Electrical Parameters @ 25° C
Insertion Loss
(dB Max.)
OCL
1-100
MHz
100 KHz, 0.1 Vrms
8 mA DC Bias
Return Loss
(dB Min.)
100-150
MHz
1-30
MHz
30-60
MHz
Common Mode Rejection
(dB Min.)
60-100
MHz
30-100
MHz
200-300 400-500
MHz
MHz
Cable Side
Xmit
Rcv
Xmit
Rcv
Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv
350µH
-1
-1
-3
-3
-18 -18 -12 -12 -10 -10 -40 -40 -30 -20 -20 -15
•
Isolation : 1500 Vrms •
Crosstalk
(dB Min.)*
1-100
MHz
-35
Impedance : 100 Ω • Rise Time : 3.0 nS Max. • *Between Channels •
Schematic
Transmit Channel
Receive Channel
8
6
9
3
12
1
13
16
1:1
1:1
10
5
15
4
Dimensions
Package
A
J
Pin 1
I.D.
B
Pad
Layout
Q
D
A
B
C
D
E
F
G
H
I
J
K
L
M
N
P
Q
.880
.365
.355
.700
.010
.100
.490
.016
.008
.085
0°
.025
P
M
E
C
K
L
PCA ELECTRONICS, INC.
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
Min.
N
PCA
EPF8087G
Date Code
H
Dim.
F
(Inches)
Max. Nom.
.900
.385
.375
Typ.
.015
Typ.
.510
.022
.012
Typ.
8°
.045
(Millimeters)
Min.
Max. Nom.
22.35
9.27
9.02
17.78
.254
2.54
12.45
.406
.203
2.16
0°
.635
.030
.100
.090
.540
22.86
9.78
9.53
Typ.
.381
Typ.
12.95
.559
.305
Typ.
8°
1.14
.762
2.54
2.29
13.72
I
G
CSF8087Ga Rev.1
12/2/97
Product performance is limited to specified parameters. Data is subject to change without prior notice.
TEL: (818) 892-0761
FAX: (818) 894-5791
http://www.pcainc.com
High Speed LAN Interface Module
ELECTRONICS INC.
EPF8087G
The circuit below is a guideline for interconnecting PCA’s EPF8087G with a typical 100 BX PHY chip for 100 Mb/s
applications over UTP cable. Further details of system design, such as chip pin-out, etc. should be obtained from the
specific chip manufacturer.
Typical insertion loss of the isolation transformer is 0.5dB. This parameter covers the entire spectrum of the encoded
signals in 100/155 protocols. Under terminated conditions, to transmit a 2V pk-pk signal across the cable, you must adjust
the specific chip preset template control resistors to get at least 2.12V pk-pk across the transmit side input pins.
It is recommended that system designers do not ground the receiver side center tap, via a capacitor. This may worsen
EMI, specifically if the secondary “common mode termination” is pulled to chassis ground as shown.
The pulldown resistors on unused pins of the RJ45 connector have been known to suppress unwanted radiation that
unused wires pick up from the immediate environment. Their placement and use are to be considered carefully before a
design is finalized.
The “common mode termination” load of 75 Ω shown from the center taps of the secondary may be taken to chassis ground
via a suitable cap. This depends upon the user’s design, EMI margin, etc.
It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit
the plane off at least 0.05 inches away from the chip side pins of EPF8087G. There need not be any ground plane beyond
this point.
For best results, the PCB designer should design the outgoing traces preferably to be 50 Ω, balanced and well coupled to
achieve minimum radiation from these traces.
Typical Application Circuit for 100 BX over UTP
RX+
RX-
3
13
1
Rcv ±
16
2
9
3
1
Xmit ±
6
12
100BX
PHY
TX+
8
TX-
6
10
RJ45*
75
75
15
EPF8087G
.01 µƒ
2 kV
.01 µƒ
2 kV
Vcc
Notes : * Pin-outs shown are for DCE configurations : e.g. Hubs, Repeaters
PCA ELECTRONICS, INC.
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
CSF8087Gb Rev. 1 12/2/97
TEL: (818) 892-0761
FAX: (818) 894-5791
http://www.pcainc.com