10/100 LAN Interface Module for PC Card Applications ELECTRONICS INC. EPF8077G • Optimized for QSI6611/6612 PHY/MAC • • Guaranteed to operate with 8 mA DC bias at 70°C on cable side • • Complies with or exceeds IEEE 802.3, 10 BT/100 BX Standards • Electrical Parameters @ 25° C OCL @ 70°C Insertion Loss (dB Max.) 100 KHz, 0.1 Vrms 8 mA DC Bias Cable Side 1-80 MHz Return Loss (dB Min.) 100 MHz 150 MHz 1-30 MHz 60 MHz Common Mode Rejection (dB Min.) 100 MHz 30-100 MHz 200 MHz Crosstalk (dB Min.) [Between Channels] 500 MHz 5-10 MHz 10-100 MHz -40 -40 Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv 350µH -1 -2 -1 • -2 -3.5 -18 -3 -12 -18 -12 -10 -10 -38 -38 -30 -25 -20 -15 Isolation : 1500 Vrms • Cable Impedance : 100 Ω • Rise Time : 3.0 nS Max. • Schematic Receive Channel Transmit Channel RD+ 3 12 RX+ TD+ 6 13 RX- TD- 5 9 TX- CT 1 RD- 2 1:1 14 CT 10 TX+ 2:1 CT 7 8 CT Dimensions Package* A N J Pin 1 I.D. PCA EPF8077G Date Code B Q Pad Layout D M E C K PCA ELECTRONICS, INC. 16799 SCHOENBORN ST. NORTH HILLS, CA 91343 F Min. A B C D E F G H I J K L M N P Q .790 .510 .078 .600 .003 .100 .660 .016 .008 .090 0° .025 (Inches) Max. Nom. .810 .530 .098 Typ. .020 Typ. .680 .022 .012 Typ. 8° .045 (Millimeters) Min. Max. Nom. 20.06 12.95 1.98 15.24 0.076 2.54 16.76 .406 .203 2.28 0° .635 .040 .100 .085 .700 20.57 13.46 2.49 Typ. .508 Typ. 17.27 .559 .305 Typ. 8° 1.14 1.02 2.54 2.16 17.78 I L H P Dim. G * Pins 4 and 11 are absent. CSF8077Ga Rev. - 9/5/97 Product performance is limited to specified parameters. Data is subject to change without prior notice. TEL: (818) 892-0761 FAX: (818) 894-5791 http://www.pca.com 10/100 LAN Interface Module for PC Card Applications ELECTRONICS INC. EPF8077G The circuit below is a guideline for interconnecting PCA’s EPF8077G with QSI6611 and QSI6612 chip set for 10/100 Mb/s applications. Further details can be obtained from the chip manufacturer application notes. Typical insertion loss of the isolation transformer is 0.5dB. This parameter covers the entire spectrum of the encoded signals in 10/100 protocols. Under terminated conditions, to transmit a 2V pk-pk signal across the cable, you must adjust the chip’s supporting resistor to get at least 2.12V pk-pk across the transmit pins. It is recommended that system designers do not use the receiver side center tap to ground, via a capacitor. This may worsen EMI, specifically if the secondary “common mode termination” is pulled to chassis ground as shown. The phantom resistors shown around the connector have been known to suppress unwanted radiation that unused wires pick up from the immediate environment. Their placement and use are to be considered carefully before a design is finalized. The “common mode termination” load of 75 Ω shown from the center taps of the secondary may be taken to chassis ground via a cap of suitable value. This depends upon user’s design, EMI margin etc. It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit the plane off at least 0.05 inches away from the chip side pins of EPF8077G. There need not be any ground plane beyond this point. For best results, PCB designer should design the outgoing traces preferably to be 50 Ω, balanced and well coupled to achieve minimum radiation from these traces. Typical Application Circuit for UTP 39Ω TX+ 6 TX- 5 7 9 1 10 2 12 3 13 6 50Ω 75Ω RJ45* 4 14 5 RX+ 25Ω RX25Ω 25Ω 25Ω QSI66 11 or QSI66 12 100Ω 100Ω +5V 3 75Ω 50Ω 7 8 2 High Voltage Capacitor EPF8077G 8 Node Pinout Chassis Ground CM Capacitor Notes : * NIC Side is shown. Hub side connection will have crossover swapping pins 3-6 & 1-2. PCA ELECTRONICS, INC. 16799 SCHOENBORN ST. NORTH HILLS, CA 91343 CSF8077Gb Rev. - 9/5/97 TEL: (818) 892-0761 FAX: (818) 894-5791 http://www.pca.com