10/100 Interface Module with Enhanced
Common Mode Attenuation
ELECTRONICS, INC.
EPF8017GH
• Optimized for DP83840A/DP83223 Chip Set •
• Recommended for use with ICS 1890 Series and SSI78Q2120 •
when connected per appropriate schematic
• Guaranteed to operate with 8mA DC bias at 70°C •
• Complies with or exceeds IEEE 802.3, 10 BT/100 BX Standards •
Electrical Parameters @ 25°C
OCL
@ 70°C
Insertion
Loss
(dB Max.)
100KHz, 0.1Vrms
8mA DC Bias
Cable Side
350µH
1-80
MHz
100-150
MHz
80-100
MHz
Common Mode
Rejection
(dB Min.)
Return
Loss
(dB Min.)
1-30
MHz
1-30
MHz
60-100
MHz
30-60
MHz
30-100
MHz
Crosstalk
(dB Min.)
[Between Channels]
100-500
MHz
Xmit
Rcv
Xmit
Rcv
Xmit
Rcv
Xmit
Rcv Xmit
Rcv
Xmit
Rcv Xmit
Rcv
Xmit
Rcv
Xmit
Rcv
-1
-1
-2
-2
-3.5
-3
-18
-18
-12
-10
-10
-40
-35
-30
-10
-10
-12
-40
5-10
MHz
10-100
MHz
-35
-35
• Isolation : 1500Vrms • Rise Time : 3.0nS Max. • Impedance : 100Ω •
Schematic
Receive Channel
1
2
Transmit Channel
7
15
5
14
6
16
11
CMC
10
1:1
1:1
12
3
Package
A
Dimensions
N
J
Pin 1
I.D.
PCA
EPF8017GH
D.C.
B
Q
D
P
M
E
C
H
Solder Pad
Layout
Dim.
A
B
C
D
E
F
G
H
I
J
K
L
M
N
P
Q
F
K
L
Min.
.970
.380
.234
--.010
--.490
.017
.008
--0°
.025
---------
(Inches)
Max.
.990
.400
.252
--.015
--.510
.022
.013
--8°
.045
---------
(Millimeters)
Nom. Min.
Max.
Nom.
.980
24.64 25.15 24.89
.390
9.91
9.65 10.16
.247
6.20
5.94
6.41
.700
17.78
----.013
.330
.254
.381
.100
2.54
----.500
12.45 12.95 12.70
.020
.508
.432
.559
.011
.279
.203
.330
.140
3.56
----4°
4°
0°
8°
.035
.889
.635
1.14
.030
.762
----.100
2.54
----.092
2.34
----.560
14.22
-----
I
G
PCA ELECTRONICS, INC.
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
CSF8017GHa
Rev. A1 4/9/99
Product performance is limited to specified parameters. Data is subject to change without prior notice.
TEL: (818) 892-0761
FAX: (818) 894-5791
http://www.pca.com
10/100 LAN Interface Module with
Enchanced Common Mode Attenuation
EPF8017GH
ELECTRONICS, INC.
The circuit below is a guideline for interconnecting PCA’s EPF8017GH with National DP83840A and DP83223 twister chip
set for 10/100 Mb/s applications. Further details can be obtained from the chip manufacturer application notes. Please
consult PCA for applications help regarding the SSI78Q2120 or ICS1890 series parts or consult with the respective
application notes.
Typical insertion loss of the isolation transformer is 0.5dB. This parameter covers the entire spectrum of the encoded
signals in 10/100 protocols. Under terminated conditions, to transmit a 2V pk-pk signal across the cable, you must adjust
the TXREF resistor of the twister chip to get at least 2.12V pk-pk across pins 16-15.
Note that significant low frequency response improvement can be obtained in the system (improving equalization effects) if
the DC blocking capacitors were not used; this can only be done by choosing a different pinout for the 10 Base-T receiver
side. This is accomplished without impacting any other behavior. If any user has a need to improve this feature, please
consult with the PCA Technical support group. This solution is similar to approaches used in EPF8013GM, EPF8022G
and EPF8038S (a repeater interface module).
It is recommended that system designers do not use the receiver side center tap to ground, via a capacitor. This may
worsen EMI, specifically if the secondary “common mode termination” is pulled to chassis ground as shown.
The phantom resistors shown around the connector have been known to suppress unwanted radiation that unused wires
pick up from the immediate environment. Their placement and use are to be considered carefully before a design is
finalized.
The “common mode termination” load of 75Ω shown from the center taps of the secondary may be taken to chassis ground
via a cap of suitable value. This depends upon user’s design, EMI margin etc.
It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit
the plane off at least 0.05 inches away from the chip side pins of EPF8017GH. There need not be any ground plane
beyond this point.
For best results, PCB designer should design the outgoing traces preferably to be 50Ω, balanced and well coupled to
achieve minimum radiation from these traces.
Typical Application Circuit for UTP (Excerpts from NSC DP83840A application notes)
0.10µF {Note 1}
1
+
Receive
7
RXD
0.1µF
{Note 1}
1000pF
2
6
10
12.1Ω
12.1Ω
14
12.1Ω
1000pF
TXO
+
PMRD
-
DP83840
CMT
16
-
TD
5
15
Transmit
EPF8017GH
7
6
5
50Ω
4
75Ω
RJ45*
3
12
2
11
12.1Ω
+
TXU
8
50Ω
75Ω
2000V
1
Node
Pinout
Isolation Cap
RXI
DP83223
SD
Chassis
Ground
PMID
+
SD
+
Other pull down/up resistors not shown, for clarification please refer to National’s application notes.
RD
-
PCA ELECTRONICS, INC.
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
Notes: 1. See text above for clarification.
2. *NIC side is shown. Hub side connections wiil have crossover swapping pins 3-6 & 1-2.
CSF8017GHb
Rev. A1
4/9/99
TEL: (818) 892-0761
FAX: (818) 894-5791
http://www.pcainc.com