PLL130-09 High Speed Translator Buffer to LVDS FEATURES GND 3 LVDS 4 7 GND 6 LVDS_BAR 5 VDD GND 2 VDD VDD REF_IN 8 VDD 1 12 11 10 9 GND 14 GND 15 OE^ 16 PLL130-09 1 2 3 4 GND 13 REF_IN GND GND The PLL130-09 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 1.0GHz. It provides a pair of differential LVDS output. Any input signal with at least 100mV swing can be used as reference signal. This chip is ideal for conversion from sine wave, TTL, CMOS, or PECL to LVDS. GND GND DESCRIPTION (TOP VIEW) VDD Differential LVDS output Single AC coupled input (min. 100mV swing). Input range from DC to 1.0 GHz. 2.5V to 3.3V operation. Available in 8-Pin SOIC or 3x3mm QFN. PLL130-09 • • • • • PIN CONFIGURATION 8 LVDS_BAR 7 VDD 6 LVDS 5 GND Note: ^ denotes internal pull up BLOCK DIAGRAM REF_IN Input Amplifier LVDS_BAR LVDS 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1 PLL130-09 High Speed Translator Buffer to LVDS PIN DESCRIPTIONS Name 8pin SOIC Pin number 3x3mm QFN Pin number GND 1,3,7 VDD 5,8 1,2,4,5, 9,13,14,15 7,10,11,12 REF_IN 2 3 I LVDS LVDS_BAR OE 4 7 N/A 6 8 16 O O I Type Description P Ground. P Power supply. Reference input signal. The frequency of this signal will be reproduced at the output (after translation to LVDS level). LVDS True output. LVDS Complementary output. Output enable (‘1’ for enable). Internal pull-up (default is ‘1’). ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model V DD VI VO TS TA TJ MIN. -0.5 -0.5 -65 -40 MAX. UNITS 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. AC Specifications PARAMETERS Input Frequency Input signal swing Output Frequency CONDITIONS REF_IN input MIN. 0 100 0 TYP. MAX. UNITS 1000 MHz mV MHz 1000 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 2 PLL130-09 High Speed Translator Buffer to LVDS 3 . LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage V DD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change ∆V OD V OH V OL V OS Power-off Leakage I OXD Output Short Circuit Current I OSD CONDITIONS V OD MIN. TYP. MAX. UNITS 247 -50 355 454 50 1.6 R L = 100 Ω (see figure) 0.9 1.125 0 ∆V OS V out = V DD or GND V DD = 0V 1.4 1.1 1.2 3 1.375 25 mV mV V V V mV ±1 ±10 uA -5.7 -8 mA 4. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100 Ω C L = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50Ω VOD VDIFF VOS RL = 100Ω 50Ω CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 80% 0V 20% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 3 PLL130-09 High Speed Translator Buffer to LVDS PACKAGE INFORMATION 8 PIN ( dimensions in mm ) Narrow SOIC Symbol Min. A 1.47 Max. 1.73 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 4.95 E 3.80 4.00 H 5.80 6.20 L 0.38 e 1.27 1.27 BSC E H D A A 1 C L e B 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 4 PLL130-09 High Speed Translator Buffer to LVDS ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL130-09 S C PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE S=SOIC; Q=QFN Order Number Marking Package Option PLL130-09QC-R PLL130-09QC PLL130-09SC-R PLL130-09SC P130-09QC P130-09QC P130-09SC P130-09SC QFN - Tape and Reel QFN - Tube SOIC -Tape and Reel SOIC - Tube PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 5