PLL620-30 PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output) DIE CONFIGURATION FEATURES DIE SPECIFICATIONS XIN 26 XOUT 27 N/C 28 S2^ 29 OE CTRL 30 N/C 31 N/C Reserved Reserved 21 20 19 18 17 Die ID: A2020-20A C502A 5 GND 6 X 7 8 GNDBUF 4 GNDBUF 3 Reserved 2 GND (0,0) 1 GND Y GNDBUF 16 N/C 15 LVDSB 14 PECLB 13 12 VDDBUF VDDBUF 11 PECL 10 LVDS 9 OUTSEL (Pad #9) Value Size 62 x 65 mil Reverse side Pad dimensions Thickness GND 80 micron x 80 micron 10 mil OUTSEL^ LVDS 1 PECL (default) OESEL (Pad #25) OE_CTRL (Pad #30) 0 1 Tri-state Output enabled (default) 0 1 Output enabled (default) Tri-state 1 (default) OE Q Q Oscillator Amplifier Selected Output 0 0 BLOCK DIAGRAM XOUT 22 OUTPUT SELECTION AND ENABLE Name XIN VDD VDD 23 VDD VDD 24 GND The PLL620-30 is a XO IC specifically designed to drive fundamental or 3 rd OT crystals from 65MHz to 130MHz, with selectable PECL or LVDS outputs and OE logic (enable high or enable low). Its design was optimized to tolerate higher limits of interelectrode capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. 25 (1550,1475) GND DESCRIPTION OESEL^ 65MHz to 130MHz Crystal input. Output range: 32.5MHz – 130MHz (no PLL). Low Injection Power for crystal, 50uW. Complementary outputs: PECL or LVDS. Selectable OE Logic Supports 2.5V or 3.3V-Power Supply. Available in die form. Thickness 10 mil. 62 mil • • • • • • • • 65 mil State Pad #9, #25: Bond to GND to set to “0”. Internal pull up. Pad #30: Logical states defined by PECL levels if OESEL is “1” Logical states defined by CMOS levels if OESEL is “0” OUTPUT FREQUENCY SELECTOR PLL620-30 S2 Output 0 1(Default)* Input/2 Input *Internally set to ‘Default’ through 60K pull-up resistor 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 1 PLL620-30 PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage Input Voltage, dc V DD VI Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model VO TS TA TJ MIN. MAX. UNITS -0.5 4.6 V DD +0.5 V V V DD +0.5 150 85 125 260 2 °C °C °C °C kV -0.5 -65 -40 V Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS SYMBOL CX+ Built-in Capacitance CXC0 OF Inter-electrode capacitance Oscillation Frequency CONDITIONS MIN. TYP. UNITS 2 65MHz to 130MHz (VDD=3.3V) Fund. MAX. 2 pF 130 MHz 2.6 65 3. General Electrical Specifications PARAMETERS SYMBOL Supply Current (Loaded Outputs) Operating Voltage I DD CONDITIONS MIN. PECL/LVDS V DD 2.97 45 45 @ 1.25V (LVDS) @ V DD – 1.3V (PECL) Output Clock Duty Cycle TYP. Short Circuit Current 50 50 ±50 MAX. UNITS 100/80 mA 3.63 55 55 V % mA 4. Jitter Specifications PARAMETERS Period jitter RMS Period jitter peak-to-peak Integrated jitter RMS CONDITIONS MIN. 77.76MHz 77.76MHz Integrated 12 kHz to 20 MHz at 77.76MHz TYP. MAX. 2.5 18.5 0.5 UNITS ps ps ps 5. Phase Noise Specifications PARAMETERS Phase Noise relative to carrier FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS 77.76MHz -75 -95 -125 -145 -155 dBc/Hz 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 2 PLL620-30 PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output) 6. LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage V DD Magnitude Change CONDITIONS V OD ∆V OD V OH V OL V OS Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change R L = 100 Ω (see figure) I OXD Output Short Circuit Current I OSD TYP. MAX. UNITS 247 -50 355 454 50 mV mV 1.4 1.1 1.2 3 1.6 1.375 25 V V V mV ±1 ±10 uA -5.7 -8 mA 0.9 1.125 0 ∆V OS Power-off Leakage MIN. V out = V DD or GND V DD = 0V 7. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100 Ω C L = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50Ω VOD VOS VDIFF 50Ω RL = 100Ω CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 80% 0V 20% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 3 PLL620-30 PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output) 8. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. MAX. UNITS V OH V OL R L = 50 Ω to (V DD – 2V) (see figure) V DD – 1.025 V DD – 1.900 V DD – 0.750 V DD – 1.620 V V Output High Voltage Output Low Voltage 9. PECL Switching Characteristics PARAMETERS SYMBOL Clock Rise Time Clock Fall Time tr tf CONDITIONS @20/80% - PECL @80/20% - PECL PECL Levels Test Circuit OUT TYP. MAX. UNITS 0.3 0.3 0.6 0.5 1.5 1.5 ns ns PECL Output Skew VDD 50Ω MIN. OUT 2.0V 50% 50Ω OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 4 PLL620-30 PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output) PAD ASSIGNMENT Pad # Name X (µ µ m) Y (µ µ m) Description 1 2 Optional GND Optional GND 248 361 109 109 Optional Ground. Optional Ground. 3 4 5 6 7 8 Optional GND Optional GND GND Reserved Optional GNDBUF GNDBUF 473 587 702 874 1042 1171 109 109 109 109 109 109 9 OUTSEL 1400 125 10 11 12 13 14 15 LVDS PECL VDDBUF Optional VDDBUF PECLB LVDSB 1400 1400 1400 1400 1400 1400 259 476 616 716 871 1089 Optional Ground. Optional Ground. Ground. Reserved for future use. Optional Ground, buffer circuitry. Ground, buffer circuitry. Output type selector. Internal pull up. See Output Selection and Enable table on page 1. Internal pull up. LVDS output. PECL output. Power supply, buffer circuitry. Optional Power supply, buffer circuitry. Complementary PECL output. Complementary LVDS output. 16 17 18 19 20 21 Not connected GNDBUF Reserved Reserved Not connected Optional VDD 1400 1389 1232 1042 854 659 1227 1365 1365 1365 1365 1365 Not Connected. Ground, buffer circuitry. Reserved for future use. Reserved for future use. Not Connected. Optional Power supply. 22 23 24 Optional VDD VDD Optional VDD 559 459 358 1365 1365 1365 25 OESEL 194 1365 26 27 28 XIN XOUT Not connected 109 109 109 1223 1017 858 Optional Power supply. Power supply. Optional Power supply. Used to choose between PECL and CMOS OE logic levels. See Output Selection and Enable table on page 1. Internal pull up Crystal input. See Crystal Specifications on page 2. Crystal output. See Crystal Specifications on page 2. Not Connected. 29 S2 109 646 30 OE_CTRL 109 397 31 Not connected 109 181 Used to select output divider. Internal pull up. Used to enable/disable the output(s). See Output Selection and Enable table on page 1. Not connected. Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 5 PLL620-30 PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output) ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL620-30 D C PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRIAL PACKAGE TYPE D=DIE Order Number Marking Package Option PLL620-30DC P620-30DC Die – Waffle Pack PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 6