PLL620-00 Low Phase Noise XO with multipliers (for HF Fund. and 3 rd O.T.) FEATURES DIE CONFIGURATION VDD VDD VDD VDD SEL0^ SEL1^ OUTSEL1^ 23 22 21 20 19 18 17 26 Die ID: A1010-10A XOUT 27 SEL3^ 28 SEL2^ 29 OE CTRL 30 NC 31 C502 5 6 7 8 GNDBUF 4 GND 3 NC (0,0) 2 GND Y GNDBUF 16 CMOS 15 LVDSB 14 PECLB 13 VDDBUF 12 VDDBUF 11 PECL 10 LVDS 9 1 GND The PLL620-00 is an XO IC specifically designed to work with high frequency fundamental and third overtone crystals. Its design was optimized to tolerate higher limits of interelectrode capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. It is ideal for XO applications requiring LVDS or PECL output levels at high frequencies. 24 GND DESCRIPTION 25 GND • • • XIN (1550,1475) GND • 62 mil • OUTSEL0^ 65 mil 100MHz to 200MHz Fundamental or 3 rd Overtone Crystal input. Output range: 100 – 200MHz (no multiplication), 200 – 400MHz (2x multiplier) or 400 – 700MHz (4x multiplier). Available outputs: PECL, LVDS, or CMOS (High Drive (30mA) or Standard Drive (10mA) output). Supports 3.3V-Power Supply. Available in die form. Thickness 10 mil. • X OE_SEL^ OUTPUT SELECTION AND ENABLE DIE SPECIFICATIONS Name Value OUTSEL1 (Pad #18) 0 Size 62 x 65 mil 0 1 Standard CMOS Reverse side Pad dimensions Thickness GND 80 micron x 80 micron 10 mil 1 0 LVDS 1 1 PECL (default) OE_SELECT (Pad #9) 0 BLOCK DIAGRAM SEL 1 (Default) OE Vin X+ Oscillator Amplifier PLL (Phase Locked Loop) Q Q OUTSEL0 (Pad #25) 0 High Drive CMOS Selected Output OE_CTRL (Pad #30) 0 Tri-state 1 (Default) 0 (Default) 1 Output enabled Output enabled Tri-state State Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1” Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is “1” Logical states defined by CMOS levels if OE_SELECT is “0” XPLL by-pass PLL620-00 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 5/10/07 Page 1 PLL620-00 Low Phase Noise XO with multipliers (for HF Fund. and 3 rd O.T.) FREQUENCY SELECTION TABLE SEL3 (Pad #28) 1 SEL2 (Pad #29) 0 SEL1 (Pad #19) 1 SEL0 (Pad #20) 1 Fin x 4 1 1 1 0 Fin x 2 1 1 1 1 No multiplication (no PLL) Selected Multiplier All pads have internal pull-ups (default value is 1). Bond to GND to set to 0. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage Input Voltage, dc Output Voltage, dc V DD VI VO Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model TS TA TJ MIN. MAX. UNITS -0.5 -0.5 4.6 V DD +0.5 V DD +0.5 V V V 150 85 125 260 2 °C °C °C °C kV -65 -40 Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Recommended ESR SYMBOL CONDITIONS Fundamental or overtone* Die only F XIN C L (xtal) C0 RE 3 rd MIN. TYP. 100 MAX. UNITS 200 MHz 3.0 F XIN <160MHz and C0<3.0pF 3 30 F XIN <200MHz and C0<3.0pF F XIN <200MHz and C0<2.5pF 25 30 pF pF Ω Ω Ω * Note: 3 rd overtone crystals require an external resistor between XIN and XOUT to prevent the fundamental from oscillating. 3. General Electrical Specifications PARAMETERS Supply Current (Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current SYMBOL I DD CONDITIONS MIN. TYP. PECL/LVDS/CMOS V DD @ 50% V DD (CMOS) @ 1.25V (LVDS) @ V DD – 1.3V (PECL) 2.97 45 45 45 50 50 50 ±50 MAX. UNITS 100/80/40 mA 3.63 55 55 55 V % mA 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 5/10/07 Page 2 PLL620-00 Low Phase Noise XO with multipliers (for HF Fund. and 3 rd O.T.) 4. Jitter Specifications PARAMETERS CONDITIONS Period jitter RMS Period jitter peak-to-peak Accumulated jitter RMS Accumulated jitter peak-topeak Random Jitter Integrated jitter RMS at 155MHz Period jitter RMS Period jitter peak-to-peak Accumulated jitter RMS Accumulated jitter peak-topeak Random Jitter Integrated jitter RMS at 622MHz MIN. At 155.52MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 155.52MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. TYP. MAX. 2.5 18.5 2.5 20 24 27 “RJ” measured on Wavecrest SIA 3000 2.5 Integrated 12 kHz to 20 MHz 0.3 0.4 At 622.08MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles 11 45 11 49 24 27 At 622.08MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. “RJ” measured on Wavecrest SIA 3000 1.6 ps ps ps 3 Integrated 12 kHz to 20 MHz UNITS ps ps ps ps 1.8 ps Note: Higher Q factor of 3 rd overtone crystals will result in even better jitter performance. Measured on Wavecrest SIA 3000 5. Phase Noise Specifications PARAMETERS FREQUENCY Phase Noise relative to carrier @10Hz @100Hz @1kHz @10kHz @100kHz 155.52MHz -75 -95 -125 -140 -145 622.08MHz -75 -95 -110 -125 -120 UNITS dBc/Hz Note: Higher Q factor of 3 rd overtone crystals will result in even better phase noise performance. 6. CMOS Electrical Specifications PARAMETERS Output drive current (High Drive) Output drive current (Standard Drive) Output Clock Rise/Fall Time (Standard Drive) Output Clock Rise/Fall Time (High Drive) SYMBOL CONDITIONS MIN. TYP. MAX. UNITS I OH V OH = V DD -0.4V, V DD =3.3V 30 mA I OL I OH I OL V OL = 0.4V, V DD = 3.3V V OH = V DD -0.4V, V DD =3.3V V OL = 0.4V, V DD = 3.3V 30 10 10 mA mA mA 0.3V ~ 3.0V with 15 pF load 2.4 0.3V ~ 3.0V with 15 pF load 1.2 ns 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 5/10/07 Page 3 PLL620-00 Low Phase Noise XO with multipliers (for HF Fund. and 3 rd O.T.) 7. LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage V DD Magnitude Change MIN. TYP. MAX. UNITS V OD 247 355 454 mV ∆V OD -50 50 mV 1.6 V Output High Voltage V OH Output Low Voltage V OL Offset Voltage CONDITIONS 1.4 R L = 100 Ω (see figure) 0.9 1.1 V OS 1.125 1.2 1.375 V Offset Magnitude Change ∆V OS 0 3 25 mV Power-off Leakage I OXD ±1 ±10 uA Output Short Circuit Current I OSD -5.7 -8 mA V out = V DD or GND V DD = 0V V 8. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100 Ω C L = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50Ω VOD VOS VDIFF RL = 100Ω 50Ω CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 80% 0V 20% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 5/10/07 Page 4 PLL620-00 Low Phase Noise XO with multipliers (for HF Fund. and 3 rd O.T.) 9. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. Output High Voltage V OH V DD – 1.025 Output Low Voltage V OL R L = 50 Ω to (V DD – 2V) (see figure) MAX. UNITS V V DD – 1.620 V 10. PECL Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Clock Rise Time tr @20/80% - PECL 0.6 1.5 ns Clock Fall Time tf @80/20% - PECL 0.5 1.5 ns PECL Levels Test Circuit OUT PECL Output Skew VDD 50Ω OUT 2.0V 50% 50Ω OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 5/10/07 Page 5 PLL620-00 Low Phase Noise XO with multipliers (for HF Fund. and 3 rd O.T.) PAD ASSIGNMENT Pad # Name X (µ µ m) Y (µ µ m) Description 1 2 3 GND GND GND 248 361 473 109 109 109 Ground. Ground. Ground. 4 5 6 7 8 GND GND N/C GND GNDBUF 587 702 874 1042 1171 109 109 109 109 109 9 OE_SELECT 1400 125 10 LVDS 1400 259 Ground. Ground. No Connection. Ground. Ground, Buffer circuitry. Used to select between PECL or CMOS logic states for OE. See Output Selection and Enable table on page 1. Internal pull up. LVDS output. 11 12 13 14 15 16 PECL VDDBUF VDDBUF PECLB LVDSB CMOS 1400 1400 1400 1400 1400 1400 476 616 716 871 1089 1227 PECL output. 3.3V power supply, Buffer circuitry. 3.3V power supply, Buffer circuitry. Complementary PECL output. Complementary LVDS output. CMOS output 17 GNDBUF 1389 1365 18 OUTSEL1 1232 1365 19 SEL1 1042 1365 20 SEL0 854 1365 21 22 23 24 VDD VDD VDD VDD 659 559 459 358 1365 1365 1365 1365 25 OUTSEL0 194 1365 26 XIN 109 1223 Ground, Buffer Circuitry. Used to select CMOS, PECL or LVDS output type. See Output Selection and Enable table on page 1. Internal pull up. Used to select multiplication factor. See Frequency Selection table on page 1. Internal pull up. Used to select multiplication factor. See Frequency Selection table on page 1. Internal pull up. 3.3V power supply. 3.3V power supply. 3.3V power supply. 3.3V power supply. Used to select CMOS, PECL or LVDS output type. See Output Selection and Enable table on page 1. Internal pull up. Crystal input. See crystal specification page 2. 27 XOUT 109 1017 28 SEL3 109 858 29 SEL2 109 646 30 OE_CTRL 109 397 31 NC 109 181 Crystal output. See crystal specification page 2. Used to select multiplication factor. See Frequency Selection table on page 1. Internal pull up. Used to select multiplication factor. See Frequency Selection table on page 1. Internal pull up. Used to enable/disable the output(s). See Output Selection and Enable table on page 1. No Connection. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 5/10/07 Page 6 PLL620-00 Low Phase Noise XO with multipliers (for HF Fund. and 3 rd O.T.) ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL620-00 D C PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE D=DIE Order Number Marking Package Option PLL620-00DC P620-00DC Die – Waffle Pack PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 5/10/07 Page 7