PLL PLL620-88OC-R

PLL620-88/-89
Low Phase Noise XO (9.5-65MHz Output)
FEATURES
19MHz to 65MHz crystal input.
Output range: 9.5MHz – 65MHz
Complementary outputs: PECL or LVDS output.
Selectable OE Logic (enable high or enable low).
Supports 2.5V or 3.3V Power Supply.
Available in 16 pin TSSOP package.
VDD
1
16
DNC
XIN
2
15
DNC
XOUT
3
14
GNDBUF
DNC
4
13
QBAR
S2
5
12
VDDBUF
OE
6
11
Q
N/C
7
10
GNDBUF
GND
8
9
DESCRIPTION
The PLL620-88 (PECL) and PLL620-89 (LVDS) are
XO ICs specifically designed to work with
fundamental or 3 rd OT crystals between 19MHz and
65MHz. The selectable divide by two feature extends
the operation range from 9.5MHz to 65MHz. They
require very low current into the crystal resulting in
better overall stability. The OE logic feature allows
selection of enable high or enable low.
OE_SELECT
X+
Q
Oscillator
Amplifier
OE_CTRL
0
1 (Default)
O
E
Q
GND
OUTPUT SELECTION AND ENABLE
0
BLOCK DIAGRAM
PLL 620-8x
•
•
•
•
•
•
PIN CONFIGURATION
1 (Default)
0 (Default)
1
State
Tri-state
Output enabled
Output enabled
Tri-state
Input selection: Bond to GND to set to “0”, bond to VDD to set to “1”
No connection results to “default” setting through
internal pull-up/-down.
OE_CTRL:
Logical states defined by PECL levels if
OE_SELECT is “1”
Logical states defined by CMOS levels if
OE_SELECT is “0”
S2
X-
OUTPUT FREQUENCY DIVIDE BY
TWO SELECTOR
PLL620-8X Block Diagram
S2
Output
0
Intput/2
1
Input
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 1
PLL620-88/-89
Low Phase Noise XO (9.5-65MHz Output)
PIN AND PAD ASSIGNMENT
Name
Pin#
Description
VDD
XIN
XOUT
1
2
3
Power Supply.
Crystal input. See Crystal Specification on page 3.
Crystal output. See Crystal Specification on page 3.
DNC
4
S2
5
OE_CTRL
DNC
GND
6
8
9
Do Not Connect.
Output Divide by Two selector pin. See the OUTPUT DIVIDE BY TWO SELECTOR Table on
page 1.
Output Enable input. See OUTPUT SELECTION AND ENABLE TABLE on page 1.
Do Not Connect.
Ground.
GNDBUF
Q
VDDBUF
QBAR
GNDBUF
DNC
10
11
12
13
14
15
Ground for output buffer circuitry.
PECL or LVDS output.
Power supply for output buffer circuitry.
Complementary PECL or LVDS output.
Ground for output buffer circuitry.
Do Not Connect.
DNC
16
Do Not Connect.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
Supply Voltage
V DD
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
VI
VO
TS
TA
TJ
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
MIN.
-0.5
-0.5
-65
-40
MAX.
UNITS
4.6
V
V DD +0.5
V DD +0.5
150
85
125
V
V
°C
°C
°C
260
2
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 2
PLL620-88/-89
Low Phase Noise XO (9.5-65MHz Output)
2. Crystal Specifications
PARAMETERS
SYMBOL
Crystal Resonator Frequency
Crystal Loading Rating
CONDITIONS
F XIN
C L (xtal)
Interelectrode Capacitance
Recommended ESR
Fundamental
MIN.
TYP.
19
MAX.
UNITS
65
MHz
pF
5
30
pF
8.5
C0
RE
AT cut
Ω
3. General Electrical Specifications
PARAMETERS
SYMBOL
Supply Current (Loaded
Outputs)
Operating Voltage
I DD
CONDITIONS
MIN.
PECL/LVDS
V DD
2.97
45
45
@ 1.25V (LVDS)
@ V DD – 1.3V (PECL)
Output Clock Duty Cycle
TYP.
Short Circuit Current
50
50
±50
MAX.
UNITS
100/80
mA
3.63
55
55
V
%
mA
4. Jitter Specifications
PARAMETERS
CONDITIONS
Period jitter RMS at 27MHz
Period jitter peak-to-peak at 27MHz
Accumulated jitter RMS at 27MHz
Accumulated jitter peak-to-peak at
27MHz
Random Jitter
MIN.
With capacitive decoupling
between VDD and GND. Over
10,000 cycles
TYP.
MAX.
2.3
18.5
With capacitive decoupling
between VDD and GND. Over
1,000,000 cycles.
20
2.3
24
“RJ” measured on Wavecrest SIA
3000
25
2.3
UNITS
ps
ps
ps
Measured on Wavecrest SIA 3000
5. Phase Noise Specifications
PARAMETERS
Phase Noise relative
to carrier
FREQUENCY
@10Hz
@100Hz
@1kHz
@10kHz
@100kHz
UNITS
27MHz
-75
-100
-125
-140
-145
dBc/Hz
Note: Phase Noise measured on Agilent E5500
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 3
PLL620-88/-89
Low Phase Noise XO (9.5-65MHz Output)
6. LVDS Electrical Characteristics
PARAMETERS
SYMBOL
Output Differential Voltage
V DD Magnitude Change
MIN.
TYP.
MAX.
UNITS
V OD
247
355
454
mV
∆V OD
-50
50
mV
1.6
V
Output High Voltage
V OH
Output Low Voltage
V OL
Offset Voltage
CONDITIONS
1.4
R L = 100 Ω
(see figure)
0.9
1.1
V OS
1.125
1.2
1.375
V
Offset Magnitude Change
∆V OS
0
3
25
mV
Power-off Leakage
I OXD
±1
±10
uA
Output Short Circuit Current
I OSD
-5.7
-8
mA
V out = V DD or GND
V DD = 0V
V
7. LVDS Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Differential Clock Rise Time
tr
0.2
0.7
1.0
ns
Differential Clock Fall Time
tf
R L = 100 Ω
C L = 10 pF
(see figure)
0.2
0.7
1.0
ns
LVDS Levels Test Circuit
LVDS Switching Test Circuit
OUT
OUT
CL = 10pF
50Ω
VOD
VOS
VDIFF
50Ω
RL = 100Ω
CL = 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
VDIFF
80%
0V
20%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 4
PLL620-88/-89
Low Phase Noise XO (9.5-65MHz Output)
8. PECL Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
Output High Voltage
V OH
V DD – 1.025
Output Low Voltage
V OL
R L = 50 Ω to (V DD – 2V)
(see figure)
MAX.
UNITS
V
V DD – 1.620
V
9. PECL Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Clock Rise Time
tr
@20/80% - PECL
0.6
1.5
ns
Clock Fall Time
tf
@80/20% - PECL
0.5
1.5
ns
PECL Levels Test Circuit
OUT
PECL Output Skew
VDD
50Ω
OUT
2.0V
50%
50Ω
OUT
tSKEW
OUT
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 5
PLL620-88/-89
Low Phase Noise XO (9.5-65MHz Output)
PACKAGE INFORMATION
16 PIN TSSOP ( mm )
Symbol
A
A1
B
C
D
E
H
L
e
Min.
Max.
1.20
0.05
0.15
0.19
0.30
0.09
0.20
4.90
5.10
4.30
4.50
6.40 BSC
0.45
0.75
0.65 BSC
E
H
D
A
A1
C
e
L
B
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL620-8x
xC
PART NUMBER
TEMPERATURE
C=COMMERCIAL
I=INDUSTRIAL
PACKAGE TYPE
O=TSSOP
Order Number
Marking
PLL620-88OC-R
PLL620-88OC
PLL620-89OC-R
PLL620-89OC
P620-88
P620-88
P620-89
P620-89
Package Option
OC
OC
OC
OC
TSSOP
TSSOP
TSSOP
TSSOP
–
–
–
–
Tape and Reel
Tube
Tape and Reel
Tube
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems
without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 6