PTC PT6523_10

Tel:886-2-66296288
Fax:886-2-29174598
URL:http://www.princeton.com.tw
1/3 Duty General Purpose LCD Driver IC
PT6523
DESCRIPTION
PT6523 is an LCD Driver IC which can drive up to 156 segments. It can be used for frequency display
in microprocessor-controlled radio receiver and in other display applications. PT6523 supports both
1/2 bias, 1/3 duty and 1/3 duty, 1/3 bias. Pin assignments and application circuit are optimized for easy
PCB layout and cost saving advantages.
FEATURES
•
•
•
•
•
•
•
•
Up to 156 Segments Outputs
1/3 Duty - 1/2 Bias and 1/3 Duty - 1/3 Bias Drive Techniques
Power Saving Mode and all Segments OFF Function
Direct Display of Display Data without using a Decoder
RC Oscillation Circuit
Power Supply Voltage: 4.5 to 6V
LCD Drive Bias Voltage can be provided internally or externally
Available in 64 pins LQFP
APPLICATIONS
•
•
•
•
•
•
Electronic Dictionary / Translator
P.O.S.
Caller ID
Pager
Mini Compo
Electronic Equipment with LCD Display
PT6523 V1.8
-1-
July, 2007
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1/3 Duty General Purpose LCD Driver IC
BLOCK DIAGRAM
COM1 COM2 COM3
VDD1
VDD2
PT6523
SG52
COMMON
DRIVER
SG5
SG4
SG3
SG2
SG1
SEGMENT DRIVER & LATCH
/INH
OSC
CLOCK
GENERATOR
SHIFT REGISTER
DI
CLK
CE
ADDRESS
DETECTOR
VDD
VSS
PT6523 V1.8
-2-
July, 2007
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1/3 Duty General Purpose LCD Driver IC
PT6523
INPUT/OUTPUT CONFIGURATIONS
The schematic diagrams of the input and output circuits of the logic section are shown below:
INPUT PIN: CLK, CE, DI
VDD
VSS
OUTPUT PIN: COM1 TO COM3, SG1 TO SG52
VDD
VDD1
VDD2
VSS
PT6523 V1.8
-3-
July, 2007
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1/3 Duty General Purpose LCD Driver IC
PT6523
PIN CONFIGURATION
PT6523 V1.8
-4-
July, 2007
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1/3 Duty General Purpose LCD Driver IC
PT6523
PIN DESCRIPTION
Pin Name
SG1 to SG52
COM1 to COM3
VDD
I/O
/INH
I
VDD1
I
VDD2
I
VSS
OSC
CE
CLK
DI
I/O
I
I
I
O
-
Description
Segment Output Pins
Common Driver Output Pins
Power Supply
Display OFF Control Input Pin
When this pin is Low, the display is forcibly turned off.
(SG1~SG52, COM1~COM3 are set to Low) (see Note)
Used for the 2/3 Bias Voltage when the Bias Voltages are
provided externally. Connect to VDD2 when 1/2 bias is
used.
Used for 1/3 Bias Voltage when the Bias Voltage are
provided externally. Connect to VDD1 when 1/2 Bias is
used.
Ground Pin
Oscillation Input/Output Pin
Chip Enable Pin
Synchronization Clock
Transfer Data Pin
Pin No.
1 to 52
53 to 55
56
57
58
59
60
61
62
63
64
Note: When /INH = Low: Serial data transfers can be performed when the display is forcibly off.
PT6523 V1.8
-5-
July, 2007
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1/3 Duty General Purpose LCD Driver IC
PT6523
FUNCTION DESCRIPTION
SERIAL DATA TRANSFER
CONDITION 1: CLK IS TERMINATED AT THE “LOW” LEVEL
CONDITION 2: CLK IS TERMINATED AT THE “HIGH” LEVEL
Notes:
1. Address: 41H
2. D1 to D156 = Display Data
When D1 to D156 are set to “1”, Display is turned ON.
When D1 to D156 are set to “0”, Display is turned OFF.
3. DR = 1/2 Bias Drive or 1/3 Bias Drive Switching Control Data
4. SC = Segment ON/OFF Control Data
5. BU = Normal Mode/Power-Saving Control Data
6. x = Not Relevant
For example, there are 63 segments that are being used, the 63 bits of display data (D94 to D156)
must be sent. Please refer to the diagram below.
8 BITS
1
0
0
←------------
0
0
ADDRESS
67 BITS
0
1
0
D94
D95
D96
D154
D155
D156
DR
SC
BU
------------→
Note: x = Not Relevant
PT6523 V1.8
-6-
July, 2007
X
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1/3 Duty General Purpose LCD Driver IC
PT6523
CONTROL DATA
DR: 1/2 BIAS DRIVE OR 1/3 BIAS DRIVE SWITCHING CONTROL DATA.
DR is the 1/2 bias drive or 1/3 bias drive switching control data bit. It is used to select either 1/2 bias
drive or 1/3 bias drive. When this pin is set to “0” the 1/2 bias drive is selected. When this pin is set to “1’,
the 1/3 bias drive is selected. Please refer to the table below for the DR settings.
DR
“0”
“1”
Drive Type
1/2 Bias Drive
1/3 Bias Drive
SC: SEGMENT ON/OFF CONTROL DATA
SC is the Segment ON/OFF Control Data Bit. It is used to select the state of the segments. If the SC is
set to “0”, then the Segment Display are turned ON, however, if the SC is set to “1”, the Display State is
OFF. Please refer to the table below.
SC
“0”
“1”
Display State
ON
OFF
It should be noted that when the segments are turned off via the SC setting (SC=”1”), the segments are
turned off the outputting of the segment OFF waveforms from the Segment Output Pins.
BU: NORMAL MODE/POWER SAVING MODE CONTROL DATA BIT
BU is the Normal Mode/Power Saving Mode Control Data Bit. It is used to select either the Normal
Mode or the Power saving Mode. When the BU is set to “0”, the Normal Mode is enabled, however, if
the BU is set to “1”, the Power saving Mode is active. It should be noted that under the Power Saving
Mode, the Oscillation (OSC Pin) is stopped and the Common and Segment Pins output Vss levels.
BU
“0”
“1”
PT6523 V1.8
Mode Selected
Normal Mode
Power Saving Mode
-7-
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1/3 Duty General Purpose LCD Driver IC
PT6523
/INH AND DISPLAY CONTROL
When power is first applied, the PT6523 internal data are not defined (D1 to D156, DR, SC and BU).
The display is turned off (SG1 to SG52, COM1 to COM3 are all set to “Low” Level) by setting the /INH
pin to “Low” at the same time the power is applied. (Please note that when the /INH Pin is set to “LOW”,
the OSC Pin is not active.) As a result of this, irrelevant display at the time of the power ON can be
eliminated if not prevented by transferring the serial data from the controller while the display is OFF
and by setting the /INH pin after the transfer is completed. Please refer to figures below.
V DD
VDD
/I N H
V IL
t1
CE
I N T ER N AL
D ATA
D IS PL A Y & C ON TR O L
D ATA TR A N SF ER
R
t2
/INH
V IL
U N D EF IN E D
C
D EF IN E D
Figure 1
where:
1. t1 is determined by the value of C and R.
2. t2=10µs (minimum)
3. Vcc=4.5V to 6.0V
PT6523 V1.8
-8-
July, 2007
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1/3 Duty General Purpose LCD Driver IC
PT6523
DISPLAY DATA TO SEGMENT OUTPUT PIN CORRESPONDENCE
Segment Output Pin
SG1
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
SG14
SG15
SG16
SG17
SG18
SG19
SG20
SG21
SG22
SG23
SG24
SG25
SG26
SG27
SG28
SG29
SG30
SG31
SG32
SG33
SG34
SG35
SG36
SG37
SG38
SG39
SG40
SG41
PT6523 V1.8
-9-
COM3
D1
D4
D7
D10
D13
D16
D19
D22
D25
D28
D31
D34
D37
D40
D43
D46
D49
D52
D55
D58
D61
D64
D67
D70
D73
D76
D79
D82
D85
D88
D91
D94
D97
D100
D103
D106
D109
D112
D115
D118
D121
COM2
D2
D5
D8
D11
D14
D17
D20
D23
D26
D29
D32
D35
D38
D41
D44
D47
D50
D53
D56
D59
D62
D65
D68
D71
D74
D77
D80
D83
D86
D89
D92
D95
D98
D101
D104
D107
D110
D113
D116
D119
D122
COM1
D3
D6
D9
D12
D15
D18
D21
D24
D27
D30
D33
D36
D39
D42
D45
D48
D51
D54
D57
D60
D63
D66
D69
D72
D75
D78
D81
D84
D87
D90
D93
D96
D99
D102
D105
D108
D111
D114
D117
D120
D123
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1/3 Duty General Purpose LCD Driver IC
Segment Output Pin
SG42
SG43
SG44
SG45
SG46
SG47
SG48
SG49
SG50
SG51
SG52
PT6523
COM3
D124
D127
D130
D133
D136
D139
D142
D145
D148
D151
D154
COM2
D125
D128
D131
D134
D137
D140
D143
D146
D149
D152
D155
COM1
D126
D129
D132
D135
D138
D141
D144
D147
D150
D153
D156
For clarity, the table below gives an example of the segment output states for the SG11 Output Pins
D31
0
0
0
0
1
1
1
1
PT6523 V1.8
Display Data
D32
0
0
1
1
0
0
1
1
D33
0
1
0
1
0
1
0
1
- 10 -
Segment Output Pin (SG11)
State Correspondence
COM1 to COM3=OFF
COM1=ON
COM2=ON
COM1=COM2=ON
COM3=ON
COM1=COM3=ON
COM2=COM3=ON
COM1 to COM3=ON
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1/3 Duty General Purpose LCD Driver IC
PT6523
1/3 DUTY, 1/2 BIAS DRIVE WAVEFORMS
The 1/3 duty, 1/2 bias waveforms are shown below.
PT6523 V1.8
- 11 -
July, 2007
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1/3 Duty General Purpose LCD Driver IC
PT6523
1/3 DUTY, 1/3 BIAS DRIVE WAVEFORMS
PT6523 V1.8
- 12 -
July, 2007
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1/3 Duty General Purpose LCD Driver IC
PT6523
ABSOLUTE MAXIMUM RATING
(Unless otherwise stated, Ta=25℃, Vss=0V)
Parameter
Symbol
Maximum Supply Voltage
VDDmax
VIN1
Input Voltage
VIN2
Output Voltage
VOUT
IOUT1
Output Current
IOUT2
Allowable Power Dissipation
Pd max
Operating Temperature
Topr
Storage Temperature
Tstg
Condition
Ratings
VDD
-0.3 to +6.5
CE, CLK, DI , /INH -0.3 to VDD+0.3
OSC
-0.3 to VDD+0.3
OSC
-0.3 to VDD+0.3
SG1 to SG52
300
COM1 to COM3
3
Ta=85℃
200
-40 to +85
-65 to +150
Unit
V
V
V
V
uA
mA
mW
℃
℃
ALLOWABLE OPERATING RANGE
(Unless otherwise stated, Ta=25℃, Vss=0V)
Parameter
Symbol
Conditions
Supply Voltage
VDD
VDD
Input Voltage
VDD1
VDD1
Input Voltage
VDD2
VDD2
High Level Input Voltage
VIH
CE, CLK, DI, /INH
Low Level Input Voltage
VIL
CE, CLK, DI, /INH
Recommended External
Rosc
OSC
Resistance
Recommended External
Cosc
OSC
Capacitance
Guaranteed Oscillator
fosc
OSC
Range
Data Setup Time *
tds
CLK, DI: Figure 2
Data Hold Time *
tdh
CLK, DI: Figure 2
CE Wait Time *
tcp
CE, CLK: Figure 2
CE Setup Time *
tcs
CE, CLK: Figure 2
CE Hold Time *
tch
CE, CLK: Figure 2
High Level Clock Pulse
toH
CLK: Figure 2
Width *
Low Level Clock Pulse
toL
CLK: Figure 2
Width *
Rise Time *
tr
CE, CLK, DI: Figure 2
Fall Time*
tf
CE, CLK, DI: Figure 2
/INH, Switching Time
t2
/INH, CE: Figure 1
Min.
4.5
4.0
0
Typ.
2/3VDD
1/3VDD
-
Max.
6.0
VDD
VDD
VDD
0.7
Unit
V
V
V
V
V
-
47
-
KΩ
-
1000
-
pF
19
38
76
KHz
100
100
100
100
100
-
-
ns
ns
ns
ns
ns
100
-
-
ns
100
-
-
ns
10
100
100
-
-
ns
ns
µs
Note: * = Refer to the diagrams below.
PT6523 V1.8
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1/3 Duty General Purpose LCD Driver IC
PT6523
CONDITION 1: CLK IS TERMINATED AT “LOW” LEVEL
VIH
CE
toH
CLK
VIL
toL
VIH
VIH
50%
VIL
tr
tf
tcp
DI
VIH
VIH
VIL
VIL
tds
VIH
VIL
tcs
tcH
tdh
CONDITION 2: WHEN CLK IS TERMINATED AT “HIGH” LEVEL
VIH
CE
VIL
toL
CLK
DI
toH
VIH
50%
VIL
VIH
VIH
tr
tf
VIH
VIH
VIL
VIL
tds
VIL
tcp
tcs
tcH
tdh
Figure 2
PT6523 V1.8
- 14 -
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1/3 Duty General Purpose LCD Driver IC
PT6523
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated, Ta=25℃, VSS=0V)
Parameter
Symbol
Conditions
CE, CLK, DI,
High level input current
IIH
/INH, VI=6V
CE, CLK, DI,
Low level input current
IIL
/INH, VI=0V
OSC
Oscillator frequency
fosc
Rosc=47KΩ
CE, CLK, DI,
Hysteresis width
VH
/INH,VDD=5V
High level output
SG1 to SG52
VOH1
voltage
Io=-20µA
Low level output
SG1 to SG52
VOL1
voltage
Io=20µA
High level output
COM1 to COM3
VOH2
voltage
Io=-100µA
Low level output
COM1 to COM3
VOL2
voltage
Io=100µA
1/2 Bias,
COM1 to COM3
VMID1
Io=±100µA
1/3 Bias
COM1 to COM3
VMID2
Io=±100µA
1/3 Bias
Intermediate level
COM1 to COM3
VMID3
voltage *
Io=±100µA
1/3 Bias
SG1 to SG52
VMID4
Io=±20µA
1/3 Bias
SG1 to SG52
VMID5
Io=±20µA
IDD1
Power Saving Mode
f=38KHz, 1/2 Bias
IDD2
VDD=5V
f=38KHz, 1/3 Bias
IDD3
Supply current
VDD=5V
f=38KHz, 1/2Bias
IDD2
VDD=6V
f=38KHz, 1/3 Bias
IDD3
VDD=6V
PT6523 V1.8
- 15 -
Min.
Typ.
Max.
Unit
-
-
5
µA
-5
-
-
µA
-
38
-
KHz
0.3
-
-
V
VDD-1.0
-
-
V
-
-
1.0
V
VDD-1.0
-
-
V
-
-
1.0
V
1/2VDD-1.0
-
1/2VDD+1.0
V
2/3VDD -1.0
-
2/3VDD +1.0
V
1/3VDD-1.0
-
1/3VDD+1.0
V
2/3VDD-1.0
-
2/3VDD+1.0
V
1/3VDD-1.0
-
1/3VDD+1.0
V
-
-
5
µA
-
400
800
µA
-
300
600
µA
-
650
1300
µA
-
580
1200
µA
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1/3 Duty General Purpose LCD Driver IC
PT6523
Note: * = Except the Bias Voltage Generation Divider Resistors that are built-into the VDD1 and VDD2
(Please refer to the figures below)
VDD
VDD1
TO COMMON
& SEGMENT DRIVERS
VDD2
EXCEPT THESE
RESISTORS
PT6523 V1.8
- 16 -
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1/3 Duty General Purpose LCD Driver IC
PT6523
APPLICATION CIRCUITS
SG33 33
SG34 34
SG35 35
SG37 37
SG36 36
SG38 38
SG39 39
SG40 40
SG42 42
SG41 41
SG43 43
SG45 45
SG44 44
SG46 46
SG47 47
49 SG49
53 COM1
SG28 28
54 COM2
SG27 27
55 COM3
SG26 26
56 VDD
SG25 25
PT6523
57 /INH
59 VDD2
SG22 22
SG16
SG15
SG14
SG17 17
SG13
SG18 18
64 DI
SG12
SG19 19
63 CLK
SG11
62 CE
SG10
SG20 20
SG9
SG21 21
61 OSC
SG6
60 VSS
SG5
MCU
SG23 23
SG4
Open
SG24 24
58 VDD1
SG3
47K
SG29 29
SG1
1000pF
0.1 µ F
52 SG52
SG2
20p
SG30 30
SG8
R1
SG31 31
51 SG51
SG7
VDD
SG32 32
50 SG50
LCD Panel
SG48 48
1/3 BIAS (FOR SMALL DISPLAY PANEL)
Note: 39KΩ ≥ R1 ≥ 10KΩ
PT6523 V1.8
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1/3 Duty General Purpose LCD Driver IC
PT6523
SG33 33
SG34 34
SG35 35
SG37 37
SG36 36
SG38 38
SG39 39
SG40 40
SG42 42
SG41 41
SG43 43
SG45 45
SG44 44
SG46 46
SG47 47
49 SG49
SG28 28
54 COM2
SG27 27
55 COM3
SG26 26
56 VDD
SG25 25
PT6523
57 /INH
SG16
SG15
SG14
SG17 17
SG13
SG18 18
64 DI
SG12
SG19 19
63 CLK
SG11
62 CE
SG10
SG20 20
SG9
SG21 21
61 OSC
SG6
MCU
SG22 22
60 VSS
SG5
C
SG23 23
59 VDD2
SG4
C
SG24 24
58 VDD1
SG3
47K
SG29 29
53 COM1
SG1
1000pF
0.1 µ F
52 SG52
SG2
20p
SG30 30
SG8
R1
SG31 31
51 SG51
SG7
VDD
SG32 32
50 SG50
LCD Panel
SG48 48
1/3 BIAS (FOR NORMAL SIZE DISPLAY PANELS)
Notes:
1. 39KΩ ≥ R1 ≥ 10KΩ
2. C ≥ 0.047µF
PT6523 V1.8
- 18 -
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1/3 Duty General Purpose LCD Driver IC
PT6523
SG33 33
SG34 34
SG35 35
SG36 36
SG37 37
SG38 38
SG39 39
SG40 40
SG42 42
SG41 41
SG43 43
SG44 44
SG45 45
SG46 46
SG47 47
49 SG49
SG25 25
PT6523
57 /INH
SG24 24
58 VDD1
SG23 23
59 VDD2
SG22 22
SG16
SG15
SG17 17
SG14
SG18 18
64 DI
SG13
SG19 19
63 CLK
SG12
62 CE
SG11
SG20 20
SG10
SG21 21
61 OSC
SG9
60 VSS
SG8
MCU
SG26 26
56 VDD
SG7
47K
R
SG27 27
55 COM3
SG6
R
C
SG28 28
54 COM2
SG1
1000pF
C
SG29 29
53 COM1
SG5
0.1 µ F
52 SG52
SG4
20p
R
SG30 30
SG3
R1
SG31 31
51 SG51
SG2
VDD
SG32 32
50 SG50
LCD Panel
SG48 48
1/3 BIAS (FOR LARGE PANELS)
Notes:
1. 39KΩ ≥ R1 ≥ 10KΩ
2. C ≥ 0.047µF
3. 10KΩ ≥ R ≥ 1KΩ
PT6523 V1.8
- 19 -
July, 2007
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1/3 Duty General Purpose LCD Driver IC
PT6523
ORDER INFORMATION
Valid Part Number
PT6523-HQ
PT6523-LQ
PT6523 V1.8
Package Type
64 Pins, LQFP(14x14mm)
64 Pins, LQFP(10x10mm)
- 20 -
Top Code
PT6523-HQ
PT6523-LQ
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1/3 Duty General Purpose LCD Driver IC
PT6523
PACKAGE INFORMATION
64 PINS, LQFP PACKAGE (BODY SIZE: 14MM X 14MM, PITCH: 0.80MM)
Symbol
A
A1
A2
b
c
D
D1
E
E1
e
L
θ
PT6523 V1.8
Min.
0.05
1.80
0.300
0.110
13.900
17.050
13.900
17.050
Max.
2.45
0.250
2.200
0.420
0.230
14.100
17.350
14.100
17.350
0.80BSC.
0.730
1.030
0°
7°
- 21 -
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1/3 Duty General Purpose LCD Driver IC
PT6523
64 PINS, LQFP PACKAGE (BODY SIZE: 10MM X 10MM, PITCH:0.50MM,
THK BODY: 1.40MM)
D
D1
A
A2
A1
-B-
-A-
L1
E1
E
-D-
e
c
b
θ1
C SEATING PLANE
θ
ccc
θ2
C
R1
R2
-H-
GAUGE PLANE
0.25mm
S
L
θ3
PT6523 V1.8
- 22 -
July, 2007
Tel:886-2-66296288
Fax:886-2-29174598
URL:http://www.princeton.com.tw
1/3 Duty General Purpose LCD Driver IC
Symbol
c
L
L1
A
A1
A2
b
D
D1
E
E1
e
R1
R2
S
θ
θ1
θ2
θ3
ccc
Min.
0.09
0.45
PT6523
Nom.
0.60
1.00 REF.
1.40
0.22
12.00 BSC.
10.00 BSC.
12.00 BSC.
10.00 BSC.
0.50 BSC.
3.5°
12°
12°
0.08
0.05
1.35
0.17
0.08
0.08
0.20
0°
0°
11°
11°
Max.
0.20
0.75
1.60
0.15
1.45
0.27
0.20
7°
13°
13°
Notes:
1. All dimensioning and tolerancing conform to ASME Y14.5M - 1994.
2. Datums A-B and D to be determined at datum plane H.
3. Dimensions D1 and E1 do not include mold prortrusion. Allowable protrusion is 0.25mm per side.
Dimensions D1 and E1 do include mold mismatch and are determined at the datum plane H.
4. Controlling Dimension: MILLIMETERS.
5. Dimension b does not include dambar protrusion. The dambar protrusion (s) shall not cause the
lead width to exceed b maximum by more than 0.08 mm. Dambar cannot be located on the lower
radius or the lead foot. minimum space between protrusion and as adjacent lead is 0.07 mm for
0.4mm and 0.5mm pitch packages.
6. A1 is defined as the distance from the seating plane to the lowest point of the package body.
7. Refer to JEDEC MS-026 Variation BCD.
JEDEC is the TRADEMARK OF JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.
PT6523 V1.8
- 23 -
July, 2007