PT6555 LCD Driver IC DESCRIPTION PT6555 is a high performance Liquid Crystal Display (LCD) Driver IC utilizing CMOS Technology specially designed with Key Input Function. It can drive up to a maximum of 164 segments and control up to 4 general purpose output ports. It includes a Key Scan Circuit that can support up to 30 key inputs and provides On-Chip Voltage Detection Type Reset Circuit which prevents incorrect display. Display Data can be directly displayed without using any decoder. PT6555 also supports both 1/4 duty-1/2 bias and 1/4 duty-1/3 bias drive techniques. Pin assignments and application circuit are optimized for easy PCB Layout and cost saving advantages. APPLICATIONS • FEATURES • CMOS Technology • PT6555: 48-pin, up to 140 Segment Drivers (4 Com x 35 Seg) • PT6555-LQ: 64-pin, up to 164 Segment Drivers (4 Com x 41 Seg) • Up to 4 General Purpose Output Ports • Key Input Function (Only PT6555-LQ) • 1/4 Duty-1/2 Bias and 1/4 Duty-1/3 Bias Drive Techniques • Sleep Mode & All Segment OFF Function • On-Chip Voltage Detection Type Reset Circuit • RC Oscillation Circuit • Power supply voltage: 4.5 to 6V • COMS/TTL compatible logic input pins • Available in 64 pins LQFP; 48 pins LQFP Package Electronic Equipment with LCD Display BLOCK DIAGRAM Note: *= Only PT6555-LQ has KI1~KI5, SG36~SG39, KS1~KS6, DO pins. Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan PT6555 APPLICATION CIRCUIT 1 Notes: 1. A capacitor must be added to the power line so that both the power supply voltage (VDD) rise time when power is applied and the power supply voltage (VDD) fall time when power drops are at least 1ms. 2. DO is an open - drain output and requires a pull-high resistor between 1KΩ to 10KΩ. The pull-up resistor value must be appropriate to the capacitor of the external wiring so that the signal wave forms are not degraded. V1.1 2 August, 2009 PT6555 APPLICATION CIRCUIT 2 Notes: 1. A capacitor must be added to the power line so that both the power supply voltage (VDD) rise time when power is applied and the power supply voltage (VDD) fall time when power drops are at least 1ms. 2. DO is an open – drain output and requires a pull-high resistor between 1KΩ to 10KΩ. The pull-up resistor value must be appropriate to the capacitor of the external wiring so that the signal wave forms are not degraded. V1.1 3 August, 2009 PT6555 APPLICATION CIRCUIT 3 Notes: 1. A capacitor must be added to the power line so that both the power supply voltage (VDD) rise time when power is applied and the power supply voltage (VDD) fall time when power drops are at least 1ms. 2. DO is an open-drain output and requires a pull-high resistor between 1KΩ to 10KΩ. The pull-up resistor value must be appropriate to the capacitor of the external writing so that the signal wave forms are not degraded. 3. R1=R2=R3, the resistance value must be decide by the LCD panel size. V1.1 4 August, 2009 PT6555 ORDER INFORMATION Valid Part Number PT6555-LQ PT6555 Package Type 64 Pin, LQFP 48 Pin, LQFP Top Code PT6555-LQ PT6555 PIN CONFIGURATION 64 PIN, LQFP 48 PIN, LQFP V1.1 5 August, 2009 PT6555 PIN DESCRIPTION Pin Name I/O Active SG1/P1~ SG4/P4 SG5~SG39 O - COM1~ COM4 O - SG40/KS1, SG41/KS2, KS3 to KS6 O - KI1~KI5 I H TEST I - VDD - - VDD1 I - VDD2 I - VSS - - OSC I/O - DO O - CE I H CLK I DI I V1.1 - Description Segment outputs for displaying the display data transferred by serial data input. The SG1/P1 to SG4/P4 pins can be used as general-purpose output ports under serial data control. Common driver outputs The frame frequency fO is given by: fO=(fosc/512)Hz Key scan outputs Although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these outputs will not be damaged by shorting when these outputs are used to from a key matrix. The SG40/KS1 and SG41/KS2 pins can be used as segment outputs when so specified by the control data Key scan inputs These pins have built-in pull-down resistors. This pin must be connected to ground. Power supply connection. Provide a voltage of between 4.5 and 6.0V Used for applying the LCD drive 2/3 bias voltage externally. Must be connected to VDD2 when a 1/2 bias drive scheme is used. Used for applying the LCD drive 1/3 bias voltage externally. Must be connected to VDD1 when a 1/2 bias drive scheme is used. Power supply connection. Connect to ground. Oscillator connection An oscillator circuit is formed by connecting an external resistor and capacitor at this pin. Serial data interface connections to the controller. Note that DO, being an open-drain output, requires a pull-up resistor. CE: Chip enable CLK: Synchronization clock DI: Transfer data DO: Output data 6 Handling when unused Pin No. PT6555 PT6555-LQ Open 1~ 35 1~39 Open 36~39 40~43 Open - 44 ~49 GND - 50~54 - 40 55 - 41 56 Open 42 57 Open 43 58 - 44 59 VDD 45 60 Open - 61 - 46 62 - 47 63 - 48 64 August, 2009 PT6555 INPUT/OUPUT CONFIGURATIONS The schematic diagrams of the input and output circuits of the logic section are shown below: V1.1 CLK, CE, DI Pins KI1 to KI5 Pins(only PT6555-LQ) DO Pin (only PT6555-LQ) SG1/P1 to SG4/P4, SG5 to SG39, SG40/KS1, SG41/KS2 Pins KS3 to KS6 Pins (only PT6555-LQ) COM1 TO COM4 Pins 7 August, 2009 PT6555 FUNCTION DESCRIPTION CONTROL DATA BITS SLEEP CONTROL BITS: S0, S1 S0 and S1 are control bits used to select either the Normal or Sleep Mode as well as set the state of the key scan output pins, namely: KS1 to KS6 during the key scan stand-by. Please refer to the table below. Control data OSC Segment outputs Output pin states during key scan stand-by Mode controller Common outputs S0 S1 KS1 KS2 KS3 KS4 KS5 KS6 0 0 Normal Operating Operating H H H H H H 0 1 Sleep Stopped L L L L L L H 1 0 Sleep Stopped L L L L L H H 1 1 Sleep Stopped L H H H H H H Notes: 1. This table is under the assumption that the pins - SG40/KS1 and SG41/KS2 are used as Key Scan Output Pins. 2. Only PT6555-LQ has the KS1~KS6 pins KEY SCAN OUTPUT / SEGMENT DRIVER OUTPUT SELECT BIT: K0, K1 K0 and K1 are control bits used to select the function of the pins - SG40/KS1 and SG41/KS2. These pins (SG40/KS1 and SG41/KS2) may either be used as Key Scan Output Pins or Segment Driver Output Pins. Please refer to the following table. Control data Output pin state Maximum number of input keys K0 K1 SG40/KS1 SG41/KS2 0 0 KS1 KS2 30 0 1 SG40 KS2 25 1 X SG40 SG41 20 Notes: 1. X = Not Relevant 2. Only PT6555-LQ has the SG40/KS1, SG41/KS2 pins SEGMENT DRIVER OUTPUT / GENERAL PURPOSE OUTPUT PORT SELECT BIT: P0, P1 P0 and P1 are control bits used to select the function of the pins - SG1/P1 to SG4/P4. These pins (SG1/P1 to SG4/P4) may be used either as Segment Driver Output Pins or General Purpose Output Ports. Please refer to the table below. Control data Output state P0 P1 SG1/P1 SG2/P2 SG3/P3 SG4/P4 0 0 SG1 SG2 SG3 SG4 0 1 P1 P2 SG3 SG4 1 0 P1 P2 P3 SG4 1 1 P1 P2 P3 P4 When the output pins (SG1/P1 to SG4/P4) are used as General Output Ports, the correspondence between the display data and these pins are shown in the table below. Output pin Corresponding display data SG1/P1 D1 SG2/P2 D5 SG3/P3 D9 SG4/P4 D13 To further clarify the table above, the following example is given. If the output pin - SG1/P1 is used as a General Output Port, then SG1/P1 Pin will output a “HIGH” Level if the corresponding Display Data, D1 - is set to “1”. Likewise, if the output pin - SG4/P4 is used as a General Output Port, then the SG4/P4 Pin will output “HIGH” Level, if the corresponding Display Data, D13 - is set to “1”. V1.1 8 August, 2009 PT6555 SEGMENT ON / OFF CONTROL BIT: SC SC is the control bit used to control the state (ON or OFF) of the Segment Drivers. Please refer to the table below. It should be noted that turning OFF the Segment by setting SC Bit means that the Segments are turned OFF by outputting segment OFF waveforms from the Segment Driver Output Pins. SC Display state 0 On 1 Off 1/2 BIAS OR 1/3 BIAS DRIVE TECHNIQUE SELECT BIT: DR DR is the control bit used to select either the 1/2 or 1/3 Bias Drive Technique. Please refer to the table below. DR Drive scheme 0 1/3 bias drive 1 1/2 bias drive KEY OUTPUT DATA BITS: KD1 TO KD30 KD1 to KD30 are key data bits of the key matrix formed by the KS1 to KS6 lines and the KI1 to KI5 lines. Please refer to the table below for the correspondence between the output pins - KS1 to KS6, input pins KI1 to KI5 and the Key Data Bits KD1 to KD30. KI1 KI2 KI3 KI4 KI5 SG40/KS1 KD1 KD2 KD3 KD4 KD5 SG41/KS2 KD6 KD7 KD8 KD9 KD10 KS3 KD11 KD12 KD13 KD14 KD15 KS4 KD16 KD17 KD18 KD19 KD20 KS5 KD21 KD22 KD23 KD24 KD25 KS6 KD26 KD27 KD28 KD29 KD30 Notes: 1. Output Pins - SG40/KS1 and SG41/KS2 are used as Key Scan Output Pins. 2. Only PT6555-LQ has the KI1~KI5 pins. As stated earlier, key matrix having up to a maximum of 30 keys may be constructed using the KS1 to KS6 and KI1 to KI5 lines. If any one of the keys is pressed, the corresponding key output data is set to 1. For example, the key data bit, KD23 is set to “1”, when the corresponding key is pressed. If the output pins, SG40/KS1 and SG41/KS2 are used as Segment Driver Output Pins (by setting the K1 and K0 control bits), a key matrix having up to a maximum of 20 keys may be constructed using the KS3 to KS6 and KI1 to KI5 lines. The key output data bits KD1 to KD10 are set to 0. SLEEP ACKNOWLEDGE DATA BIT: SA SA is an output data bit that is used to set the state when the key is pressed. When DO is in “LOW” state and the serial data is inputted, then the mode can be set either to Normal or Sleep Mode during this period. SA will be “1” in sleep mode and “0” in normal mode. V1.1 9 August, 2009 PT6555 DISPLAY DATA & OUTPUT PIN CORRESPONDENCE Output SG1/P1 SG2/P2 SG3/P3 SG4/P4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 SG13 SG14 SG15 SG16 SG17 SG18 SG19 SG20 COM1 D1 D5 D9 D13 D17 D21 D25 D29 D33 D37 D41 D45 D49 D53 D57 D61 D65 D69 D73 D77 COM2 D2 D6 D10 D14 D18 D22 D26 D30 D34 D38 D42 D46 D50 D54 D58 D62 D66 D70 D74 D78 COM3 D3 D7 D11 D15 D19 D23 D27 D31 D35 D39 D43 D47 D51 D55 D59 D63 D67 D71 D75 D79 COM4 D4 D8 D12 D16 D20 D24 D28 D32 D36 D40 D44 D48 D52 D56 D60 D64 D68 D72 D76 D80 Output SG21 SG22 SG23 SG24 SG25 SG26 SG27 SG28 SG29 SG30 SG31 SG32 SG33 SG34 SG35 *SG36 *SG37 *SG38 *SG39 *SG40/KS1 COM1 D81 D85 D89 D93 D97 D101 D105 D109 D113 D117 D121 D125 D129 D133 D137 D141 D145 D149 D153 D157 COM2 D82 D86 D90 D94 D98 D102 D106 D110 D114 D118 D122 D126 D130 D134 D138 D142 D146 D150 D154 D158 COM3 D83 D87 D91 D95 D99 D103 D107 D111 D115 D119 D123 D127 D131 D135 D139 D143 D147 D151 D155 D159 COM4 D84 D88 D92 D96 D100 D104 D108 D112 D116 D120 D124 D128 D132 D136 D140 D144 D148 D152 D156 D160 Note: *=Only PT6555-LQ does not have the SG36~KS2/SG41 pins. To provide further clarity, an example is given in the table below showing the SG11 - Segment Driver Output State and its corresponding Display Data - D41, D42, D43, D44 relationship. Display data Output pin state D41 D42 D43 D44 SG11 0 0 0 0 The LCD segments for COM1, COM2, COM3 and COM4 are off. 0 0 0 1 The LCD segment for COM4 is on. 0 0 1 0 The LCD segment for COM3 is on. 0 0 1 1 The LCD segments for COM3 and COM4 are on. 0 1 0 0 The LCD segment for COM2 is on. 0 1 0 1 The LCD segments for COM2 and COM4 are on. 0 1 1 0 The LCD segments for COM2 and COM3 are on. 0 1 1 1 The LCD segments for COM2, COM3 and COM4 are on. 1 0 0 0 The LCD segment for COM1 is on. 1 0 0 1 The LCD segments for COM1 and COM4 are on. 1 0 1 0 The LCD segments for COM1 and COM3 are on. 1 0 1 1 The LCD segments for COM1, COM3 and COM4 are on. 1 1 0 0 The LCD segments for COM1 and COM2 are on. 1 1 0 1 The LCD segments for COM1, COM2 and COM4 are on. 1 1 1 0 The LCD segments for COM1, COM2 and COM3 are on. 1 1 1 1 The LCD segments for COM1, COM2, COM3 and COM4 are on. V1.1 10 August, 2009 PT6555 SERIAL DATA INPUT CASE 1: CLK IS TERMINATED AT “LOW” LEVEL Notes: 1. Address: 42H (At the PT6555, the display data D141~D164 must be set to 0) 2. Display Data Bits: D1 to D164 3. Sleep Control Data: S0, S1 4. Key Scan Output / Segment Driver Output Select Bits: K0, K1(Only for PT6555-LQ) 5. Segment Driver Output / General Purpose Output Port Select Bits: P0, P1 6. Segment ON / OFF Control Bit: SC 7. 1/2 Bias or 1/3 Bias Drive Select Bit: DR V1.1 11 August, 2009 PT6555 CASE 2: CLK IS TERMINATED AT “HIGH” LEVEL Notes: 1. Address: 42H (At the PT6555, the display data D141~D164 must be set to 0) 2. Display Data Bits: D1 to D164 3. Sleep Control Data: S0, S1 4. Key Scan Output / Segment Driver Output Select Bits: K0, K11(Only for PT6555-LQ) 5. Segment Driver Output / General Purpose Output Port Select Bits: P0, P1 6. Segment ON / OFF Control Bit: SC 7. 1/2 Bias or 1/3 Bias Drive Select Bit: DR V1.1 12 August, 2009 PT6555 SERIAL DATA OUTPUT(ONLY PT6555-LQ) CASE 1: CLK IS TERMINATED AT “LOW” LEVEL Notes: 1. Address: 43H 2. Key Output Data Bits: KD1 to KD30 3. Sleep Acknowledge Bit: SA 4. If the Key Data Read Operation is executed when DO is in “HIGH” state, then the Read Key Data Bits (KD1 to KD30) and the Sleep Acknowledge Bit (SA) will not be valid. 5. Only PT6555-LQ has the DO pin. CASE 2: CLK IS TERMINATED AT “HIGH” LEVEL Notes: 1. Address: 43H 2. Key Output Data Bits: KD1 to KD30 3. Sleep Acknowledge Bit: SA 4. If the Key Data Read Operation is executed when DO is in “HIGH” state, then the Read Key Data Bits (KD1 to KD30) and the Sleep Acknowledge Bit (SA) will not be valid. 5. Only PT6555-LQ has the DO pin. SLEEP MODE The Sleep Mode is enabled when any one of the Sleep Acknowledge Control Bits – S0 or S1 is set to “1”. Under the Sleep Mode, the all the segment and common driver outputs are set to “LOW” level and the oscillation operation is terminated. Oscillation operation will only commence again if a key is pressed. Please note that this reduces power dissipation. The Sleep Mode is cleared when both control bits - S0 and S1 are set to “0”. It should be noted, however, that the output pins - SG1/P1 and SG2/P2 might still be used as General Purpose Output Ports by setting the control bits - P0 and P1 even under the Sleep Mode. In other words, the Sleep Mode does not in anyway affect the SG1/P1 and SG2/P2 pins from being used as General Purpose Output Ports. V1.1 13 August, 2009 PT6555 KEY SCAN OPERATION KEY SCAN TIMING PT6555-LQ scans the keys twice (reads the key data twice) and if the key data matches, this key is defined as PRESSED (or ON). A key scan period is equivalent to 384T (s). 800T (s) after the key scan commences, PT6555-LQ outputs a key data read request. If the key data from the does not match and a key was pressed at that point, the keys are scanned again. It must be noted that PT6555-LQ cannot detect a key which is pressed shorter than 800T (s). Notes: 1. T=1/fosc where fosc=oscillation frequency 2. The Sleep Mode, the state of these pins is determined by the control bits- S0 and S1. Key Scan signals are not outputted from pins that are set to “LOW” Level. 3. Only PT6555-LQ has KS1~KS6 pins. KEY SCAN OPERATING UNDER THE NORMAL MODE Under the Normal Mode, the Key Scan Output Pins - KS1 to KS6 are set to HIGH. When a key is pressed, a key scan operation commences. The keys are scanned until all keys are released. For multiple key press operation, a multiple key press is valid only if multiple key data bits have set and verified by the key scan. If a key is pressed longer than 800T(s), PT6555-LQ outputs a key read data request (DO is set to “LOW” level) to the controller. The controller acknowledges the request and reads the key data. It must be noted that if CE is HIGH during a serial data transfer, then DO is set to “HIGH”. After the controller reads the key data, the key data request is cleared (DO is set to HIGH) and another key scan operation is performed. Notes: 1. T=1/fosc, where fosc is the oscillation frequency. 2. DO is an open - drain output and requires a pull-high resistor between 1KΩ to 10KΩ. 3. Only PT6555-LQ has the DO pin. V1.1 14 August, 2009 PT6555 KEY SCAN OPERATION UNDER THE SLEEP MODE Under the Sleep Mode, the key scan output pins-KS1 to KS6 are set either to HIGH or LOW” State by the Sleep Acknowledge Control Bits-S0 and S1. If a key that is located on one of the lines corresponding to a KS1 to KS6 pin that has been set to “HIGH” is pressed, then the oscillation commences and the key scan operation is executed. The keys are scanned until all keys are released. For multiple key press operation, a multiple key press is valid only if multiple key data bits have been set and verified by the key scan. If a key is pressed longer than 800T (s), PT6555-LQ outputs a key read data request (DO is set to LOW” level) to the controller. The controller acknowledges the request and reads the key data. It must be noted that if CE is “HIGH” during a serial data transfer, then DO is set to “HIGH”. After the controller reads the key data, the key data request is cleared (DO is set to “HIGH”) and another key scan operation is performed. It must be noted that the Sleep Mode is not cleared. Please refer to the Sleep Mode Key Scan example given below. In the example below, Sleep Mode: S0=0, S1=1, KS6 Pin=”HIGH”. Notes: 1. T=1/fosc, where fosc is the oscillation frequency. 2. In order to prevent erroneous operation due to sneak current in the KS6 scan output signal when keys on the KS1 to KS5 lines are pressed at the same time, diodes must be connected as shown in the diagram above. 3. Only PT6555-LQ has the KS1~KS6 pin, KI1~KI5 pins Notes: 1. DO is an open - drain output and requires a pull-high resistor between 1KΩ to 10KΩ. 2. Only PT6555-LQ has DO pin. V1.1 15 August, 2009 PT6555 KEY SCAN OPERATION FOR MULTIPLE KEY PRESSES For dual key press operation, PT6555-LQ can perform key scan operations without any need for a diode to be connected. For triple key press on the KI 1 to KI5 lines, multiple key presses on the KS1 to KS6 lines, and other multiple key presses require a diode to be connected in series with each key. Connecting a diode will ensure that only the keys that were pressed will be recognized. Applications that cannot determine triple or more multiple key presses must check the key data for three or more 1 bit and ignore such data. VOLTAGE DETECTION TYPE RESET CIRCUIT (VDET) The Voltage Detection Type Reset Circuit generates an output signal and resets the system when power is applied for the first time and when voltage drops (that is, for example, the power supply voltage is less than or equal to the power down detection voltage (VDET=3.0V typ).) To ensure that this reset function works properly, it is recommended that a capacitor be connected to the power supply line such that both the power supply voltage (VDD) rise time when power is first applied and the power supply voltage (VDD) fall time when the voltage drops are at least 1ms. SYSTEM RESET If the supply voltage (VDD) rise time when power is first applied is at least 1ms, then the VDET output signal will initiate a system reset when the supply voltage is increased. Likewise, if the supply voltage (VDD) fall time when power drops is at least 1ms, then the VDET output signal will initiate a system reset when the supply voltage is decreased. It must be noted that the reset function is cleared at the point when all the serial data (Display Data - D1 to D164 and the control data) have been completely transferred. Please refer to the figure below. Notes: Power supply voltage VDD rise time: t1 > 1ms Power supply voltage VDD fall time: t2 > 1ms During the reset period, the internal states of the various blocks of PT6555 are enumerated below. It should be noted that the Address Interface, Control Register and the Shift Register Blocks are not reset during this period since serial data transfer is possible. (Please also refer to the Block Diagram Section) CLOCK GENERATOR BLOCK When the reset function is applied, the base clock is terminated. The state of the OSC pin (either Normal or Sleep Mode) is determined after the control bits - S0 and S1 have been transferred. COMMON DRIVER, SEGMENT DRIVER & LATCH BLOCKS When the reset function is applied the display is turned OFF. It should be noted, however, that the display data may be inputted to the latch circuit during the reset period. KEY SCAN BLOCK When the reset function is applied, the key scan circuit is set to the initial state and the key scan operation is disabled. KEY BUFFER BLOCK When the reset function is applied, all the key data are set to “LOW”. CONTROL REGISTER & SHIFT REGISTER Since serial data transfer is possible, these circuits are not reset. V1.1 16 August, 2009 PT6555 During the reset period the states of the output pins are listed in the table below. Output Pin SG1/P1 to SG4/P4 SG5 to SG39 COM1 to COM4 SG40/KS1, SG41/KS2 KS3 to KS5 KS6 DO State during reset L (Note 1) L L L (Note 1) X (Note 2) H H (Note 3) Notes: 1. These output pins are forcibly set to be used as Segment Driver Output Pins and are held at “LOW” State. 2. When power is first applied, these pins are not defines until the control bits - S0 and S1 have been completely transferred. 3. DO is an open - drain output and requires a pull-high resistor between 1KΩ to 10KΩ. It is kept at “HIGH” state during the reset period even if a key data read operation is executed. V1.1 17 August, 2009 PT6555 1/4 DUTY, 1/2 BIAS DRIVE TECHNIQUE V1.1 18 August, 2009 PT6555 1/4 DUTY, 1/3 BIAS DRIVE TECHNIQUE V1.1 19 August, 2009 PT6555 CONTROLLER KEY DATA READ TECHNIQUES When the controller receives a key data read request from PT6555, it performs a key data read acquisition operation using either the Timer Based Key Data Acquisition or the Interrupt Based Key Data Acquisition. TIMER BASED KEY DATA ACQUISITION TECHNIQUE Under the Timer Based Key Data Acquisition Technique, the controller uses a timer to determine the states of the keys (ON or OFF) and read the key data. Please refer to the flowchart below. Every t7 period, the controller checks the state of DO when the CE is at “LOW” level. If DO is “LOW”, then the controller validates that a key has been pressed and performs a key data read operation. Please refer to the timing diagram below. It must be noted that if the key data read operation is performed when the DO is “HIGH”, the read key data (KD1 to KD30) and the sleep acknowledge bit will not be valid. V1.1 20 August, 2009 PT6555 INTERRUPT BASED KEY DATA ACQUISITION TECHNIQUE Under the Interrupt Based Key Data Acquisition Technique, the controller uses interrupts to determine the state of the keys (ON or OFF) and read the key data. Please refer to the flow chart diagram below. V1.1 21 August, 2009 PT6555 Every t8 period, the controller checks the state of the DO Pin when CE is at “LOW” state. If the DO is at “LOW” level, then the controller validates that a key has been pressed and a key data read operation is performed. Please refer to the timing diagram below. It must be noted however, that if a key data read operation is performed when DO is held “HIGH”, the read key data - KD1 to KD30 and the sleep acknowledge bit SA will not be valid. V1.1 22 August, 2009 PT6555 ABSOLUTE MAXIMUM RATINGS (Unless otherwise specified, Ta=25℃, Vss=0V) Parameter Symbol Conditions Maximum supply voltage VDDmax VDD VIN1 CE, CLK, DI Input voltage VIN2 OSC, KI1 to KI5, TEST, VDD1, VDD2 VOUT1 DO Output voltage VOUT2 OSC, SG1 to SG41, COM1 to COM4, P1 to P4 IOUT1 SG1 to SG41 IOUT2 COM1 to COM4 Output current IOUT3 KS1 to KS6 IOUT4 P1 to P4 Allowable power dissipation Pd max Ta = 85℃ Operating temperature Topr Storage temperature Tstg - Rating -0.3 to +7.0 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to VDD +0.3 300 3 1 5 200 -40 to +85 -65 to +150 Unit V V V V V µA mA mA mA mW ℃ ℃ Typ 2/3VDD 1/3VDD 62 680 50 160 160 - Unit V V V V V V KΩ pF KHz ns ns ns ns ns ns ns ns ns µs µs Note: Only PT6555-LQ has KI1~KI15, SG36~SG41, KS1~KS6, DO, and I/O pins. ALLOWABLE OPERATING CONDITIONS (Unless otherwise specified, Ta=25℃, Vss=0V) Parameter Symbol Supply voltage VDD VDD1 Input voltage VDD2 VIH1 Input high level voltage VIH2 Input low level voltage VIL Recommended external resistance ROSC Recommended external capacitance COSC Guaranteed oscillation range fOSC Data setup time tds Data hold time tdh CE wait time tcp CE setup time tcs CE hold time tch High level clock pulse width toH Low level clock pulse width toL Rise time Fall time DO output delay time tdc DO rise time tdr V1.1 Conditions VDD VDD1 VDD2 CE, CLK, DI KI1 to KI5 CE, CLK, DI, KI1 to KI5 OSC OSC OSC CLK, DI CLK, DI CE, CLK CE, CLK CE, CLK CLK CLK CE, CLK, DI CE, CLK, DI DO, RPU=4.7kΩ, CL=10pF DO, RPU=4.7kΩ, CL=10pF 23 Min. 4.5 2.8 0.7VDD 0 25 160 160 160 160 160 160 160 - Max. 6.0 VDD VDD VDD VDD 0.7 100 1.5 1.5 August, 2009 PT6555 ELECTRICAL CHARACTERISTICS FOR THE ALLOWABLE OPERATING CONDITIONS (Unless otherwise specified, Ta=25℃, VSS=0V) Parameter Hysteresis Power-down detection voltage Input high level voltage Input high level current Pull-down resistance Output off leakage current Output high level voltage Output low level voltage Symbol VH VDET IIH IIL RPD IOFFH VOH1 VOH2 VOH3 VOH4 VOL1 VOL2 VOL3 VOL4 VOL5 VMID1 VMID2 Output middle level voltage *2 VMID3 VMID4 VMID5 Oscillator frequency fOSC IDD1 Current drain IDD2 IDD3 Conditions CE, CLK, DI CE, CLK, DI: VI=VDD CE, CLK, DI: VI=0V KI1 to KI5: VDD=5.0V DO: VO=6.0V KS1 to KS6: IO=-500µA P1 to P4: IO=-1mA SG1 to SG41: IO=-20µA COM1 to COM4: IO=-100µA KS1 to KS6: IO=25µA P1 to P4: IO=1mA SG1 to SG41: IO=20µA COM1 to COM4: IO=100 µA DO: IO=1mA COM1 to COM4:1/2 bias, IO=±100µA SG1 to SG41:1/3 bias, IO=±20µA SG1 to SG41:1/3 bias, IO=±20µA COM1 to COM4:1/3 bias, IO=±100µA COM1 to COM4:1/3 bias, IO=±100µA OSC:R=62KΩ, C=680pF Sleep mode VDD=6.0V, output open, 1/2 bias, fOSC=50KHz VDD=6.0V, output open, 1/3 bias, fOSC=50KHz Min. 2.7 -5.0 50 VDD -1.2 VDD -1.0 VDD -1.0 VDD -1.0 0.2 - Typ. 0.1VDD 3.0 100 VDD -0.5 0.5 0.1 Max. 5.0 250 6.0 VDD -0.2 1.5 1.0 1.0 1.0 0.5 Unit V V µA µA KΩ µA V V V V V V V V V 1/2VDD -1.0 - 1/2VDD +1.0 V 2/3VDD -1.0 - 2/3VDD +1.0 V 1/3VDD -1.0 - 1/3VDD +1.0 V 2/3VDD -1.0 - 2/3VDD +1.0 V 1/3VDD -1.0 - 1/3VDD +1.0 V 40 - 50 60 100 KHz µA - 250 500 µA - 200 400 µA Notes: 1. A capacitor must be added to the power line so that both the power supply voltage (VDD) rise time when power is applied and the power supply voltage (VDD) fall time when power drops are at least 1ms. 2. DO is an open – drain output and requires a pull-high resistor between 1KΩ to 10KΩ. The pull-up resistor value must be appropriate to the capacitor of the external wiring so that the signal wave forms are not degraded. 3. Only PT6555-LQ has KI1~KI5, SG36~SG41, KS1~KS6, DO pins. V1.1 24 August, 2009 PT6555 CASE 1: WHEN CLK IS TERMINATED AT LOW LEVEL. CASE 2: WHEN CLK IS TERMINATED AT HIGH LEVEL. The Bias Voltage Generation Driver built-into VDD1 and VDD2 are not included. Please refer to the diagram below. V1.1 25 August, 2009 PT6555 PACKING INFORMATION 48 PINS, LQFP Symbol A A1 A2 b c D D1 E E1 e L L1 θ Min. 0.05 1.35 0.17 0.09 Nom. 1.40 0.22 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.50 BSC 0.60 1.00 REF. 3.5° 0.45 0° Max. 1.60 0.15 1.45 0.27 0.20 0.75 7° Notes: 1. All dimensions are in millimeter. 2. Refer to JEDEC MS-026BBC V1.1 26 August, 2009 PT6555 64 PINS, LQFP Symbol A A1 A2 b c D D1 E E1 e L L1 Min. 0.05 1.35 0.17 0.09 θ 0° 0.45 Nom. 1.40 0.22 12.00 BSC 10.00 BSC 12.00 BSC 10.00 BSC 0.50 BSC 0.60 1.00 REF Max. 1.60 0.15 1.45 0.27 0.20 3.5° 7° 0.75 Notes: 1. All dimensions are in millimeter. 2. Refer to JEDEC MS-026BCD V1.1 27 August, 2009 PT6555 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V1.1 28 August, 2009