SN54LVC646A-SP www.ti.com ............................................................................................................................................................................................. SCAS865 – OCTOBER 2008 RAD-TOLERANT CLASS V OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS FEATURES 1 • • • • • • • • • • • (1) W PACKAGE (TOP VIEW) Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 7.4 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Ioff Supports Partial Power-Down-Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Rad Tolerant: 50kRad (Si) TID (1) – TID Dose Rate 0.10 rad/s QML-V Qualified, SMD 5962-97626 CLKAB SAB DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 V CC CLKBA SBA OE B1 B2 B3 B4 B5 B6 B7 B8 Radiation tolerance is a typical value based upon initial device qualification. Radiation Lot Acceptance Testing is available – contact factory for details. DESCRIPTION/ORDERING INFORMATION The SN54LVC646A octal bus transceiver and register is designed for 2.7-V to 3.6-V VCC operation. This device consists of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 shows the four fundamental bus-management functions that are performed with the SN54LVC646A device. ORDERING INFORMATION TA –55°C to 125°C (1) (2) PACKAGE CFP – W (1) (2) Tube of 85 ORDERABLE PART NUMBER 5962-9762601VKA TOP-SIDE MARKING 5962-9762601VKA For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated SN54LVC646A-SP SCAS865 – OCTOBER 2008 ............................................................................................................................................................................................. www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port is stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data is stored in one register and B data can be stored in the other register. When an output function is disabled, the input function still is enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE INPUTS (1) 2 DATA I/O OE DIR CLKAB CLKBA SAB SBA A1–A8 X X ↑ X X X Input (1) B1–B8 OPERATION OR FUNCTION Unspecified (1) Store A, B unspecified (1) Input Store B, A unspecified (1) ↑ X X ↑ ↑ X X Input Input Store and B data H or L H or L X X Input disabled Input disabled Isolation, hold storage X X X L Output Input Real-time B data to A bus X H or L X H Output Input Stored B data to A bus H X X L X Input Output Real-time A data to B bus H H or L X H X Input Output Stored A data to B bus X X H X H X L L L L L L X Unspecified The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN54LVC646A-SP SN54LVC646A-SP 21 OE L 3 DIR L 1 23 CLKAB CLKBA X X 2 SAB X BUS B BUS A BUS A BUS B www.ti.com ............................................................................................................................................................................................. SCAS865 – OCTOBER 2008 22 SBA L 21 OE L 3 DIR H 3 DIR X X X 1 23 CLKAB CLKBA X ↑ X ↑ ↑ ↑ 2 SAB X X X STORAGE FROM A, B, OR A AND B 2 SAB L 22 SBA X BUS B BUS A BUS A 21 OE X X H 23 CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A 1 CLKAB X 22 SBA X X X 21 OE L L 3 DIR L H 1 CLKAB X H or L 23 CLKBA H or L X 2 SAB X H 22 SBA H X TRANSFER STORED DATA TO A AND/OR B Figure 1. Bus-Management Functions Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN54LVC646A-SP 3 SN54LVC646A-SP SCAS865 – OCTOBER 2008 ............................................................................................................................................................................................. www.ti.com LOGIC DIAGRAM (POSITIVE LOGIC) OE DIR CLKBA SBA CLKAB SAB 21 3 23 22 1 2 One of Eight Channels 1D C1 A1 4 20 B1 1D C1 To Seven Other Channels Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V –0.5 VCC + 0.5 (2) (3) VO Voltage range applied to any output in the high or low state IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current Continuous current through VCC or GND Tstg (1) (2) (3) 4 Storage temperature range –65 V ±50 mA ±100 mA 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN54LVC646A-SP SN54LVC646A-SP www.ti.com ............................................................................................................................................................................................. SCAS865 – OCTOBER 2008 Recommended Operating Conditions (1) Operating VCC Supply voltage VIH High-level input voltage VCC = 2.7 V to 3.6 V VIL Low-level input voltage VCC = 2.7 V to 3.6 V VI Input voltage Data retention only VO Output voltage IOH High-level output current IOL Low-level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature (1) MIN MAX 2 3.6 UNIT V 1.5 2 V 0.8 V 0 5.5 V High or low state 0 VCC 3-state 0 5.5 VCC = 2.7 V –12 VCC = 3 V –24 VCC = 2.7 V 12 VCC = 3 V 24 –55 V mA mA 10 ns/V 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS 2.7 V to 3.6 V IOH = –4 mA 1.65 V IOH = –8 mA 2.3 V IOH = –12 mA IOH = –24 mA Control inputs II UNIT V 2.2 3V 2.4 3V 2.2 2.7 V to 3.6 V 0.2 IOL = 4 mA 1.65 V IOL = 8 mA 2.3 V IOL = 12 mA 2.7 V 0.4 IOL = 24 mA 3V 0.55 VI = 0 to 5.5 V V 3.6 V VI or VO = 5.5 V 0 IOZ (2) VO = 0 to 5.5 V 3.6 V VI = VCC or GND IO = 0 3.6 V ≤ VI ≤ 5.5 V (3) One input at VCC – 0.6 V, Other inputs at VCC or GND ΔICC MAX VCC – 0.2 2.7 V Ioff ICC TYP (1) 1.65 V to 3.6 V IOL = 100 µA VOL MIN 1.65 V to 3.6 V IOH = –100 µA VOH VCC ±5 µA µA ±15 10 3.6 V 10 2.7 V to 3.6 V 500 µA µA µA Ci Control inputs VI = VCC or GND 3.3 V 4.5 pF Cio A or B port VO = VCC or GND 3.3 V 7.5 pF (1) (2) (3) All typical values are at VCC = 3.3 V, TA = 25°C. For I/O ports, the parameter IOZ includes the input leakage current. This applies in the disabled state only. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN54LVC646A-SP 5 SN54LVC646A-SP SCAS865 – OCTOBER 2008 ............................................................................................................................................................................................. www.ti.com Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN MAX MIN UNIT MAX fclock Clock frequency tw Pulse duration 3.3 150 3.3 150 MHz ns tsu Setup time, data before CLK↑ 1.6 1.5 ns th Hold time, data after CLK↑ 1.7 1.7 ns Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) FROM (INPUT) PARAMETER VCC = 2.7 V TO (OUTPUT) MIN fmax MAX 150 A or B tpd CLK SBA or SAB B or A A or B VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz 7.9 1 7.4 8.8 1 8.4 9.9 1 8.6 ns ten OE A 10.2 1 8.2 ns tdis OE A 8.9 1 7.5 ns ten DIR B 10.4 1 8.3 ns tdis DIR B 8.7 1 7.9 ns Operating Characteristics TA = 25°C PARAMETER Cpd (1) 6 Power dissipation capacitance per transceiver TEST CONDITIONS Outputs enabled Outputs disabled VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP (1) (1) 75 (1) (1) 9 f = 10 MHz UNIT pF This information was not available at the time of publication. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN54LVC646A-SP SN54LVC646A-SP www.ti.com ............................................................................................................................................................................................. SCAS865 – OCTOBER 2008 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V∆ VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN54LVC646A-SP 7 PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing 5962-9762601VKA ACTIVE CFP W Pins Package Eco Plan (2) Qty 24 1 TBD Lead/Ball Finish A42 MSL Peak Temp (3) N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54LVC646A-SP : • Catalog: SN54LVC646A NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 MECHANICAL DATA MCFP007 – OCTOBER 1994 W (R-GDFP-F24) CERAMIC DUAL FLATPACK 0.375 (9,53) 0.340 (8,64) Base and Seating Plane 0.006 (0,15) 0.004 (0,10) 0.090 (2,29) 0.045 (1,14) 0.045 (1,14) 0.026 (0,66) 0.395 (10,03) 0.360 (9,14) 0.360 (9,14) 0.240 (6,10) 1 0.360 (9,14) 0.240 (6,10) 24 0.019 (0,48) 0.015 (0,38) 0.050 (1,27) 0.640 (16,26) 0.490 (12,45) 0.030 (0,76) 0.015 (0,38) 12 13 30° TYP 1.115 (28,32) 0.840 (21,34) 4040180-5 / B 03/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD Index point is provided on cap for terminal identification only. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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