TI CLVCH16652AIDGGREP

SN74LVCH16652A-EP
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS743A – DECEMBER 2003 – REVISED AUGUST 2005
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(1)
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Member of the Texas Instruments Widebus™
Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 6.3 ns at 3.3 V
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2 V at
VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With
3.3-V VCC)
Ioff Supports Partial-Power-Down Mode
Operation
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DGG PACKAGE
(TOP VIEW)
1OEAB
1CLKAB
1SAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2SAB
2CLKAB
2OEAB
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1CLKBA
1SBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2SBA
2CLKBA
2OEBA
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DESCRIPTION/ORDERING INFORMATION
This 16-bit bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVCH16652A consists of D-type flip-flops and control circuitry arranged for multiplexed transmission of
data directly from the data bus or from the internal storage registers. The device can be used as two 8-bit
transceivers or one 16-bit transceiver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated
SN74LVCH16652A-EP
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS743A – DECEMBER 2003 – REVISED AUGUST 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
Complementary output-enable (OEAB and OEBA) inputs control the transceiver functions. Select-control (SAB
and SBA) inputs select whether real-time or stored data is transferred. A low input level selects real-time data,
and a high input level selects stored data. The circuitry used for select control eliminates the typical decoding
glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the
four fundamental bus-management functions that can be performed with the SN74LVCH16652A.
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable
inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the
internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output
reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of
bus lines remains at its last-level configuration.
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sinking/current-sourcing capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input
circuit and is not disabled by OE or DIR.
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
(1)
TSSOP – DGG
ORDERABLE PART NUMBER
Tape and reel
CLVCH16652AIDGGREP
TOP-SIDE MARKING
CH16652AEP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
DATA I/O (1)
INPUTS
OEBA
CLKAB
CLKBA
SAB
SBA
A1–A8
B1–B8
L
H
H or L
H or L
X
X
Input
Input
Isolation
L
H
↑
↑
X
X
Input
Input
Store A and B data
X
H
↑
H or L
X
X
Input
Unspecified (2)
Store A, hold B
H
H
↑
↑
X (2)
X
Input
Output
Store A in both registers
L
X
H or L
↑
X
X
Unspecified (2)
Input
Hold A, store B
L
L
↑
↑
X
X (2)
Output
Input
Store B in both registers
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
(1)
(2)
2
OPERATION OR FUNCTION
OEAB
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real-time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus and
stored B data to A bus
The data-output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always
are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
Select control = L, clocks can occur simultaneously. Select control = H, clocks must be staggered to load both registers.
SN74LVCH16652A-EP
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
OEAB OEBA
L
L
CLKAB CLKBA SAB
X
X
X
BUS B
BUS A
BUS A
BUS B
SCAS743A – DECEMBER 2003 – REVISED AUGUST 2005
SBA
L
OEAB OEBA
H
H
OEBA
H
X
H
CLKAB CLKBA SAB
X
X
↑
X
X
↑
X
↑
↑
STORAGE FROM
A, B, OR A AND B
SAB
L
SBA
X
BUS B
BUS A
BUS A
OEAB
X
L
L
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
CLKAB
X
SBA
X
X
X
OEAB
H
OEBA
L
CLKAB
H or L
CLKBA
H or L
SAB
H
SBA
H
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
3
SN74LVCH16652A-EP
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS743A – DECEMBER 2003 – REVISED AUGUST 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
1OEBA
1OEAB
1CLKBA
1SBA
1CLKAB
1SAB
56
1
55
54
2
3
One of Eight Channels
1A1
1D
C1
5
52
1B1
1D
C1
To Seven Other Channels
2OEBA
2OEAB
2CLKBA
2SBA
2CLKAB
2SAB
29
28
30
31
27
26
One of Eight Channels
2A1
15
42
1D
C1
To Seven Other Channels
4
1D
C1
2B1
SN74LVCH16652A-EP
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS743A – DECEMBER 2003 – REVISED AUGUST 2005
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range (2)
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
state (2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Voltage range applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
θJA
Package thermal
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
impedance (4)
–65
V
64
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
VCC
Supply voltage
VIH
High-level input voltage
Operating
Data retention only
VCC = 1.65 V to 1.95 V
MIN
MAX
1.65
3.6
1.5
Low-level input voltage
VI
1.7
VCC = 2.7 V to 3.6 V
2
VO
Output voltage
0.35 × VCC
0.7
VCC = 2.7 V to 3.6 V
0.8
0
5.5
High or low state
0
VCC
3-state
0
5.5
VCC = 1.65 V
IOH
High-level output current
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
V
V
–4
VCC = 2.3 V
–8
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 1.65 V
IOL
V
VCC = 2.3 V to 2.7 V
Input voltage
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 1.65 V to 1.95 V
VIL
UNIT
mA
4
VCC = 2.3 V
8
VCC = 2.7 V
12
VCC = 3 V
24
–40
mA
10
ns/V
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
SN74LVCH16652A-EP
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS743A – DECEMBER 2003 – REVISED AUGUST 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –100 µA
VOH
1.65 V to 3.6 V
Control inputs
II
1.2
IOH = -8 mA
2.3 V
1.7
2.7 V
2.2
3V
2.4
IOH = –24 mA
3V
2.2
IOL = 100 µA
1.65 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
3V
0.55
VI = 0 to 5.5 V
1.65 V
45
V (3)
Ioff
VI or VO = 5.5 V
IOZ (4)
VO = 0 V or (VCC to 5.5 V)
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V (5)
IO = 0
µA
–45
75
3V
VI = 2 V
∆ICC
µA
(2)
2.3 V
VI = 1.7 V
VI = 0.8 V
ICC
±5
V
(2)
VI = 0.7 V
VI = 0 to 3.6
V
3.6 V
VI = 1.07 V
A or B port
UNIT
VCC – 0.2
1.65 V
VI = 0.58 V
II(hold)
TYP (1) MAX
IOH = –4 mA
IOH = –12 mA
VOL
MIN
–75
3.6 V
±500
0
±10
µA
3.6 V
±10
µA
20
3.6 V
One input at VCC – 0.6 V, Other inputs at VCC or GND
20
2.7 V to 3.6 V
500
µA
µA
Ci
Control inputs
VI = VCC or GND
3.3 V
5
pF
Cio
A or B port
VO = VCC or GND
3.3 V
8
pF
(1)
(2)
(3)
(4)
(5)
All typical values are at VCC = 3.3 V, TA = 25°C.
This information was not available at the time of publication.
This is the bus-hold maximum dynamic current required to switch the input from one state to another.
For the total leakage current in an I/O port, please consult the II(hold) specification for the input voltage condition 0 V < VI < VCC, and the
IOZ specification for the input voltage conditions VI = 0 V or VI = VCC to 5.5 V. The bus-hold current, at input voltage greater than VCC, is
negligible.
This applies in the disabled state only.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
VCC = 1.8 V
± 0.15 V
MIN
fclock
MAX
VCC = 2.5 V
± 0.2 V
MIN
(1)
Clock frequency
MAX
VCC = 2.7 V
MIN
(1)
MAX
VCC = 3.3 V
± 0.3 V
MIN
150
UNIT
MAX
150
MHz
tw
Pulse duration, CLK high or low
(1)
tsu
Setup time, A or B before CLKAB↑ or CLKBA↑
(1)
(1)
3.4
3
ns
Hold time, A or B after CLKAB↑ or CLKBA↑
(1)
(1)
0
0.2
ns
th
(1)
6
This information was not available at the time of publication.
(1)
3.3
3.3
ns
SN74LVCH16652A-EP
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS743A – DECEMBER 2003 – REVISED AUGUST 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
(1)
MIN
VCC = 2.5 V
± 0.2 V
MAX
(1)
fmax
tpd
VCC = 1.8 V
± 0.15 V
MIN
MAX
(1)
VCC = 2.7 V
MIN
MAX
150
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
150
MHz
A or B
B or A
(1)
(1)
(1)
(1)
6.4
1.4
6.3
CLKAB or CLKBA
A or B
(1)
(1)
(1)
(1)
7.3
2.4
6.4
(1)
(1)
(1)
ns
SAB or SBA
B or A
(1)
8.8
1.9
7.4
ten
OE or OE
A or B
(1)
(1)
(1)
(1)
6.6
1.6
6.3
ns
tdis
OE or OE
A or B
(1)
(1)
(1)
(1)
6.6
1.2
6.2
ns
This information was not available at the time of publication.
Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
(1)
Power dissipation capacitance
per transceiver
Outputs enabled
Outputs disabled
f = 10 MHz
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
TYP
TYP
TYP
(1)
(1)
55
(1)
(1)
12
UNIT
pF
This information was not available at the time of publication.
7
SN74LVCH16652A-EP
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS743A – DECEMBER 2003 – REVISED AUGUST 2005
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
8
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CLVCH16652AIDGGREP
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V62/04710-01XE
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVCH16652A-EP :
• Catalog: SN74LVCH16652A
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
CLVCH16652AIDGGREP TSSOP
DGG
56
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.6
15.6
1.8
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CLVCH16652AIDGGREP
TSSOP
DGG
56
2000
346.0
346.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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