XE1201A TLA TLB FILTERING + IO OFFSET REDUCTION RFA AVDD QO AGND DVDD DGND RXD RFB DEMODULATOR SYMBOL SYNCHRO CLKD SD SC BUS CONTROL POWER MANAGEMENT DE 90 DEG EN RXTX RF POWER AMP RFOUT TXD DDS VREF 90 DEG LO CLOCK TPA TPB RFGND RFVDD TKA TKB TKC SWA SWB LOGND XTAL XE1201A 300-500 MHz Low-Power UHF Transceiver Features • • • • • • • • General Description The XE1201A is a half-duplex FSK transceiver for operation in the 433 MHz ISM band (optimized) and in the 300-500 MHz band. The modulation used is the Continuous Phase, 2 level Frequency Shift Keying (CPFSK). The direct conversion (zero IF) receiver architecture enables on-chip channel filtering. very low-power half-duplex operation data rate up to 64 kbit/s high sensitivity few external components internal bit synchronizer 3-wire bus for easy microcontroller interface output power programmable via bus The XE1201A includes a bit synchronizer so that glitch free data with synchronized clock can directly be read by a low cost / low complexity micro-controller. The transmitted power level can also be controlled via the bus. The XE1201A meets the I-ETS300-220 standard and is available in a TQFP32 package. Applications • • • • • • telemetry RF security systems wireless data link door openers remote control wireless sensing Quick Reference Data • • • • Ordering Information Part XE1201AI026TR Temperature range -40 to 70° C Pin-package supply voltage RF sensitivity data rate transmitted power 2.4 V -109 dBm 64 kbits/s +5 dBm TQFP32 Rev 1 August 2005 www.semtech.com 1 XE1201A 1. DETAILED PIN DESCRIPTION PIN NAME DESCRIPTION 1 EN Chip enable 2 DE Bus data enable 3 AVDD Supply voltage for analog 4 TPA Power amplifier tank circuit 5 TPB Power amplifier tank circuit 6 AGND Ground for analog 7 SC Bus clock 8 SD Bus data input 9 LOGND Ground for local oscillator 10 TKA Oscillator tank circuit 11 TKB Oscillator tank circuit 12 TKC Oscillator tank circuit 13 SWA SAW resonator 14 SWB SAW resonator 15 RXTX Receiver / transmitter enable 16 VREF Voltage stabilizer decoupling 17 TXD Data input stream 18 CLKD Received data clock 19 RXD Received data output 20 DGND Ground for digital 21 XTAL Reference oscillator 22 XTAL Reference oscillator 23 DVDD Supply voltage for digital 24 QO Test pin 25 IO Test pin 26 RFA RF input 27 RFB RF input 28 RFGND Ground for RF 29 RFOUT Transmitter output 30 TLA Low noise amplifier tank circuit 31 TLB Low noise amplifier tank circuit 32 RFVDD Supply voltage for RF © Semtech 2005 www.semtech.com 2 EN IO RFA RFB RFGND TLA RFOUT TLB RFVDD XE1201A QO DE DVDD AVDD XTAL XTAL TPA DGND TPB RXD AGND VREF RXTX SWA SWB TKC TXD TKB SD TKA CLKD LOGND SC fig. 2: TQFP 32L package 2 ABSOLUTE RATINGS • supply voltage 2.4 V to 6 V • storage temperature -55°C to 150°C • operating temperature -40°C to 70°C 3. ELECTRICAL CHARACTERISTICS Tamb = 25° C; VDD = 3.0 V; FLO = 433.92 MHz; +/- 125 kHz frequency deviation; 16 kbit/s pseudo random bit sequence unless otherwise specified SYMBOL PARAMETER CONDITIONS Min Typ Max Units VDD Operating supply voltage 2.4 3.0 5.5 V IDDR Reception supply current 4.5 6 7.5 mA IDDT Transmission supply current - 15 dBm output power - 5 dBm output power + 2.5 dBm output power + 5 dBm output power IDDS Standby current Clock running Clock stopped FR Frequency range TP Transmitter output power RFS ZIN RF sensitivity RF input impedance 5.5 8 11 13.5 - 55 0.2 65 1 µA 300 - 500 MHz C13 = 0 ; C12 = 0 C13 = 0 ; C12 = 1 C13 = 1 ; C12 = 0 C13 = 1 ; C12 = 1 BER=1%, Rsource = 50Ω 8 kbit/s 16 kbit/s 64 kbit/s Parallel real part © Semtech 2005 mA mA mA mA -15 -5 +2 +5 µA dBm dBm dBm dBm -106 -104 -99 -109 -107 -102 - dBm dBm dBm - 1 - kΩ www.semtech.com 3 XE1201A SYMBOL PARAMETER CONDITIONS Min Typ Max Units Parallel capacitive part - 4 - pF - 2.4 - pF ZOUT RF output impedance Parallel capacitive part CCR Co-channel rejection Funw =FLO ±125 kHz RFlevel = RFS+3dB -12 -7 - dB BI Blocking immunity Funw =FRF ±1MHz RFlevel = RFS+3dB 39 43 - dB ML Maximum receiver input level 1 channel, BER=1% 0 - - dBm BW Baseband filter bandwidth 3 dB cutoff frequency 250 330 410 kHz LOD Local oscillator drift -40 < Tamb < +70° C - -4 - ppm/° C LOS Local oscillator shift TBW DDS anti-alias filter bandwidth FDEV Frequency deviation DR Data rate LOL - +/-8 +/-15 KHz - 160 - kHz programmable by 3-wire bus +/-4 - programmable by 3-wire bus 4 - 64 kbit/s Digital input/output low level 0 - 0.4 V HIL Digital input/output high level 2.6 - 3 V Tclk Clock wake-up time from cold start (see fig. 5) - 2 3.5 ms Rwu Receiver wake-up time from oscillator running (see fig. 4) bit synchronizer bypassed - 60 75 µs Twu Transmitter wake-up time from oscillator running (see fig. 4) - 60 75 µs Tsu Data set-up time (see fig. 3) 125 - - ns Trt Receive to transmit switching time (see fig. 4) - 15 25 µs Ttr Transmit to receive switching time (see fig. 4) bit synchronizer bypassed - 60 75 µs Tr SC bus clock rise time - - 50 ns Tf SC bus clock fall time - - 50 ns SC bus clock frequency - - 4 MHz FSC 2.4 V < Vdd < 3.6 V © Semtech 2005 +/-200 kHz www.semtech.com 4 XE1201A 4. HANDLING All pins withstand the ESD test in accordance with the MIL-STD-883F method 3015.6 (all pins towards substrate), human body model (2000V). The RF output (pin 29) is only protected against negative voltage (no protection device towards VDD). 5. FUNCTIONAL DESCRIPTION The XE1201A is controlled via the 3-wire serial bus by a microcontroller that addresses the 3 wires (SD - Serial Data, SC Serial Clock, DE - Data enable) according to the format shown in Figure 3 a bit stream of 16 bits is fed into the internal register (SD - pin8) with the Most Significant Bit (MSB) first and is shifted during the low to high transition of the clock (SC - pin7). This serial programming is enabled by the Data Enable pin (DE - pin2) which must be set to zero before the data transfer. The low to high transition of the Data Enable validates the register filling. Data is retained as long as the supply voltage (Vdd) is present. 6. 3-WIRE BUS DATA FORMAT The first two bits (D15 and D14) determine the A, B or C register access according to the truth table below (table 1). D15 D14 REGISTER NAME 0 0 REGISTER A 0 1 REGISTER B 1 0 REGISTER C 1 1 NOT USED table 1: Register Address These three registers are filled by the data A13 to A0, B13 to B0 or C13 to C0 according to the value of D15 and D14. Register A is used to set the XE1201A mode (transmission, reception and standby modes) and to select the receiver data rate. Register B is used for central frequency adjustment during transmission. Register C is used for frequency deviation set-up, transmitted power adjustment and other auxiliary functions. 7. “A” REGISTER FORMAT (D15=0, D14=0) D15 D14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 table 2: “A” Register Format ∗ A13 - CONTROL MODE BIT When set to 0, this bit enables the XE1201A transmit/receive mode and chip enable control to be addressed via the pin15 (RXTX) and pin1 (EN). For further information on this control mode, please refer to RXTX pin and EN pin description on page 7. When set to 1, the transmit/receive mode and chip enable controls are addressed by bit A10 and A11. In this mode, the levels applied on pin 15 and pin 1 have no effect. ∗ A12 - CLOCK CONTROL This bit is used for XE1201A internal clock start-up. When set to 1, the clock is always running whatever the state of the chip enable bit (A11 when A13=1 or pin1 when A13=0). When set to 0, the clock activity is determined by the chip enable bit (A11). ∗ A11 - CHIP ENABLE When set to 0, all the blocks of XE1201A are deactivated (except the clock if the bit A12 is set to 1). However, the 3-wire bus can be programmed in disabled mode as long as Vdd is present. This bit replaces the Chip Enable (pin1) when A13=1. © Semtech 2005 www.semtech.com 5 XE1201A ∗ A10 - TRANSMIT/RECEIVE MODE When set to 1, the XE1201A is set in receiving mode and in transmitting mode when set to 0. This bit replaces the RXTX (pin15) when A13=1 ∗ A9, A8, A7, A6 – DEMODULATOR AND BIT SYNCHRONIZER BYPASSING These bits are used in applications where the bit synchronizer is not needed for e.g. decrease the receiver wake-up time a) The receiver is in normal mode but the demodulator is bypassed. The outputs I and Q of the limiters are available on pin19 (I output) and pin 18 (Q output). Bits A9 to A6 must be set according to table 3 below. A9 0 A8 1 A7 0 A6 0 table 3: Receiver Mode with Demodulator Bypassed b) The receiver is in normal mode but the internal bit synchronizer is switched off. Raw data are available at RXD output (pin19). The CLKD (pin18) is meaningless. In this mode, no preamble is required for clock synchronization of the bit synchronizer so that the minimum receiver wake-up time is accessed. Bits A9 to A6 must be set according to table 4. A9 0 A8 1 A7 0 A6 1 table 4: Receiver Mode with Bit Synchronizer Switched Off ∗ A5, A4, A3, A2, A1, A0 - RECEIVER DATA RATE These bits are used to set the bit synchronizer data rate according to the following formula: = DR 65574 • 2 ⎛ − n ⎞ ⎜ ⎟ ⎝ 8 ⎠ [Hz] Where n is the unsigned decimal value of bits A5 to A0 (A5=MSB). The inverse function gives the value of n for a wanted data rate DR (in Hz) as showed below: n = ⎛ ⎡ ⎜ − 8 • Log ⎢ 61• DR ⎜ ⎢⎣ 4 • 10 6 ROUND ⎜ ⎜ Log 2 ⎜ ⎜ ⎝ ⎤ ⎥ ⎥⎦ ⎞ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎠ The rate of the data to be transmitted should then be fed accordingly in TXD (pin17). Note: when the bit synchronizer is bypassed (bits A9,A8,A7,A6), it is not necessary to program the data rate. The data are demodulated accordingly to the incoming data rate. 8. “B” REGISTER FORMAT (D15=0, D14=1) D15 D14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 table 5: “B” register format ∗ B13, B12, B11, B10, B9, B8, B7 - OFFSET FREQUENCY These bits can be used to calibrate the oscillator central frequency (e.g. related to SAW resonator initial accuracy). A frequency offset can be added or subtracted to the frequency of the Local Oscillator while transmitting according to the following formula: © Semtech 2005 www.semtech.com 6 XE1201A DFC = 3906.25 • n [Hz] where n is the signed value of bits B13 to B7 (from -64 to +63). Bits B13 to B7 are expressed in 2’s complement 7 bits representation. The offset can thus range from -250000 Hz (1000000) to 246093.75 Hz (0111111). ∗ B6, B5, B4, B3, B2, B1, B0 – TEST BITS These bits are for test purpose only. They must be set to zero. 9. “C” REGISTER FORMAT (D15=1, D14=0) D15 D14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 table 6: “C” register format ∗ C13, C12 - TRANSMITTED OUTPUT POWER The output power available at RFOUT (pin29) can be adjusted with C13 and C12 according to table 7 below. C13 0 0 1 1 C12 0 1 0 1 OUTPUT POWER - 15 dBm - 5 dBm + 2.5 dBm + 5 dBm table 7: transmitter output power control bits ∗ C11 - DATA INVERSION BIT The received data stream is inverted when this bit is set to 1. ∗ C10, C9 - TEST BITS These bits must always be set to C10=1 and C9=0 ∗ C8 - TRANSMITTED OUTPUT AMPLIFIER ENABLE When set to 0, this bit disables the transmitter output amplifier whatever the transceiver state is. ∗ C7 - TRANSMITTED DATA BIT This bit replaces the TXD (pin17) when bit A13 of register A is set to 1 and thus allows a data transmission via the 3-wire bus. ∗ C6, C5, C4, C3, C2, C1, C0 - MODULATOR FREQUENCY DEVIATION These bits are used to adjust the frequency deviation of the modulator according to the following formula: FDEV = 3906 . 25 • n [Hz] Where n is the unsigned decimal value of bits C6 to C0. The frequency deviation of the transmitter can be theoretically adjusted up to 496093.75 Hz. However, it should be noticed that for proper behavior of the XE1201A demodulator, the frequency deviation must be greater than the data rate (FDEV>DR) and smaller than the baseband filter bandwidth (BW). In addition, the FDEV must be smaller than the DDS anti-alias filter bandwidth (TBW). © Semtech 2005 www.semtech.com 7 XE1201A 10. BUS REGISTERS DEFAULT VALUES After Vdd is applied, the internal 3-wire bus registers A, B and C are initialized with the values shown in tables 8, 9 and 10 below. A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 1 A3 0 A2 0 A1 0 A0 0 table 8: register “A” default value B13 0 B12 0 B11 0 B10 0 B9 0 B8 0 B7 0 B6 0 B5 0 B4 0 B3 0 B2 0 B1 0 B0 0 table 9: register “B” default value C13 0 C12 1 C11 0 C10 1 C9 0 C8 1 C7 0 C6 0 C5 1 C4 0 C3 0 C2 0 C1 0 C0 0 table 10: register “C” default value After power-up, the XE1201A is in the following initial state: RXTX (pin15) and EN (pin1) control mode, clock stopped, 16 kbits/s data rate, -5 dBm output power and 125 kHz frequency deviation. Ready to transmit or receive. 11. RXTX (PIN15) AND EN (PIN1) RXTX (receive/transmit) and EN (chip enable) are activated when the control bit (A13) is set to zero. In this mode, the XE1201A can be switched on, switched off and set to the transmit or receive mode with pin 1 (EN) and 15 (RXTX) as explained in table 11 and figure 4. EN 0 1 1 RXTX X 0 1 MODE CHIP DISABLED TRANSMIT MODE RECEIVE MODE table 11: EN and RXTX pins truth table 12. BIT SYNCHRONIZATION IN RECEIVING MODE The operation is based on an advanced digital PLL controlled by an ALU. Care must be taken while using it, particularly when the receiver is in permanent listening mode (please refer to the XE1201A application information documentation). The internal demodulator of the XE1201A needs a frame of 20 synchronization bits to ensure proper clock synchronization. The synchronization frame must be a sequence of 0 and 1 sent alternatively. © Semtech 2005 www.semtech.com 8 XE1201A 13. WAKE-UP TIME The wake-up time depends on the clock state. If the clock is kept running (A12=1), the wake-up time is 75 µs max. If the clock is off, the clock has to be switched on before the wake-up of the rest of the XE1201A as explained in figure 5. © Semtech 2005 www.semtech.com 9 XE1201A 14. TIMING FIGURES Tsu Tsu DE Tsu SC SD D15 D14 A,B,C13 A,B,C12 A,B,C1 MSB A,B,C0 LSB Figure 3: timing diagram for 3-wire bus ready to receive Rwu Ttr ready to transmit EN RXTX RECEIVE MODE TRANSMIT MODE Figure 4: timing diagram for RXTX and EN control pins ready to transmit or receive EN Tclk Twu Figure 5: timing diagram for chip wake-up (from cold start) © Semtech 2005 www.semtech.com 10 XE1201A RXD (pin 19) Measurement conditions: 16 kbit/s - RFlevel = -102 dBm Figure 6: Received data stream with internal bit synchronizer bypassed RXD (pin 19) CLKD (pin 18) Measurement conditions: 16 kbit/s - RFlevel = -102 dBm Figure 7: Received data stream with internal bit synchronizer and synchronized data clock output © Semtech 2005 www.semtech.com 11 XE1201A components side (front) copper side (back) Figure 8: reference board layout (not actual scale) © Semtech 2005 www.semtech.com 12 XE1201A 15. ANALOG PIN DESCRIPTION Vdd 1k2 p i n4 Vdd 1k3 1k2 pi n10 pi n12 pi n1 3 pi n1 4 p i n5 1k3 p i n11 p in 4 a n d 5 : p o w e r a m p lif ie r p in 1 0 , 1 1 , 1 2 , 1 3 a n d 1 4 : o s c illa t o r pi n21 2p2 pin22 5p 3p p i n16 p in 1 6 : vo lt a g e s t a b il iz e r p in 2 1 a n d 2 2 : c lo c k o s c illa t o r p i n2 6 p i n27 p i n2 4 , 2 5 p in 2 4 a n d 2 5 : I an d Q o u t p u t s p in 2 6 a n d 2 7 : R F a m p lif ie r in p u t s pi n3 0 pi n3 1 pin29 p in 2 9 : t r a n s m it t e r o u tp u t p in 3 0 an d 3 1 : L N A t an k Figure 9: analog pins description © Semtech 2005 www.semtech.com 13 XE1201A 16. APPLICATION INFORMATION VDD 12nH ustrip 12nH ustrip 2.7 pF VDD 10nF 50 OHM 2.2pF TLB TLA FILTERING+ OFFSET REDUCTION RFA FROM ANTENNA 18nH ustrip IO QO AVDD AGND DVDD DGND RFB RXD 2.2pF DEMODULATOR SYMBOL SYNCHRO DATA OU TPUT CLKD 2.2pF SD SC BUS CONTROL POWER MANAGEMENT 90 DEG CHIP CONTROL DE VDD EN 3.3pF 18nH ustrip 50 OHM RF POWER AMP RXTX RFOUT TXD DDS 2.2pF DATA INPUT TO ANTENNA VREF 10nF 90 DEG LO CLOCK TPB 2.2pF RFGND RFVDD TKA TKC SWA SWB LOGND XTAL 27nH 2 - 6pF 10nF 12nH TKB VDD TPA 12nH 12nH 12nH SAW RESON ATOR RFM R02101A 4 MHz IQD HC43 10nF VDD Figure 10: application information © Semtech 2005 www.semtech.com 14 XE1201A 17. MECHANICAL DATA PACKAGE DIMENSIONS Body Thickness Footprint (Body+) A A1 A2 D D1 E E1 L e b ccc ddd 0 VALUE 1.00 2.00 1.20 0.05 min/0.15 max 1.00 9.00 7.00 9.00 7.00 0.60 0.80 0.35 0.10 0.20 0°-7° TOLERANCE MAX ±0.05 ±0.25 ±0.10 ±0.25 ±0.10 +0.15/-0.10 BASIC ±0.05 MAX MAX Package Information for TQFP 32L © Semtech 2005 www.semtech.com 15 XE1201A © Semtech 2005 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech. assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. Contact Information Semtech Corporation Wireless and Sensing Products Division 200 Flynn Road, Camarillo, CA 93012 Phone (805) 498-2111 Fax : (805) 498-3804 © Semtech 2005 www.semtech.com 16