ETC SLD2083CZ

Preliminary
Product Description
SLD2083CZ
The SLD2083CZ is a 10 Watt high performance
LDMOS transistor designed for operation to
2700MHz. It is an excellent solution for applications requiring high linearity and efficiency at a
low cost. The SLD2083CZ is typically used in
the design of driver stages for power amplifiers,
repeaters, and RFID applications. The power
transistor is fabricated using Sirenza’s high performance XeMOS IITM process.
Pb
RoHS Compliant
& Green Package
10 Watt Discrete LDMOS Device
Ceramic Package
Product Features
Functional Schematic Diagram
•
•
•
•
•
•
ESD
Protection
10 Watt Output P1dB
Single Polarity Supply Voltage
High Gain: 18 dB Typical
High Efficiency
Advanced, XeMOS II LDMOS
Integrated ESD Protection, Class 1A
Applications
•
•
•
Case Flange = Ground
Base Station PA driver
Repeater
RFID
RF Specifications
Parameter
Frequency
Gain
Efficiency
IRL
Linearity
Description: Test Conditions in Sirenza Evaluation
Board VDS = 28.0V, IDQ = 125mA, TFlange = 25ºC
Unit
Frequency of Operation
Min
Typ
Max
MHz
-
-
2700
10 Watt CW, 902MHz-928MHz
dB
17
18
-
Drain Efficiency at 10 Watt CW, 915MHz
%
40
47
-
Input Return Loss, 10 Watt Output Power, 915MHz
dB
-
-15
-10
3rd Order IMD at 10 Watt PEP (Two Tone), 915MHz
dBc
-
-28
-26
1dB Compression (P1dB), 915MHz
Watt
10
11
-
ACPR=-55dB, IS-95
Watt
1.8
1.6
-
ACPR=-45dB, IS-95
Watt
3.2
3.6
-
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions.
Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without
notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product
for use in life-support devices and/or systems.
Copyright 2005 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
1
http://www.sirenza.com
EDS-103754 Rev D
Preliminary
SLD2083CZ 10 Watt LDMOS FET
DC Specifications
Parameter
Unit
Forward Transconductance @ 125mA IDQ
Min
Typical
mA / V
590
IDS=3mA
Volt
3.8
1mA IDS current
Volt
65
Ciss
Input Capacitance (Gate to Source) VGS=0V, VDS=28V
pF
27.5
Crss
Reverse Capacitance (Gate to Drain) VGS=0V, VDS=28V
pF
0.81
Coss
Output Capacitance (Drain to Source) VGS=0V, VDS=28V
pF
14.65
Drain to Source Resistance, VGS=10V, VDS=250mV
Ω
0.6
gm
VGSThreshold
VDS Breakdown
RDSon
Max
Quality Specifications
Parameter
Unit
ESD Rating
Human Body Model
Volts
500
85oC Leadframe, 200oC Channel
Hours
1.2 X 106
Thermal Resistance (Junction to Case)
ºC/W
4
MTTF
RTH
Min
Typical
Max
Pin Description
Pin #
Function
Description
1
Gate
Transistor RF input and gate bias voltage. The gate bias voltage must be temperature compensated to maintain constant bias current over the operating temperature range. Care must be taken to protect against video
transients that exceed the recommended maximum input power or voltage. .
2
Drain
Transistor RF output and drain bias voltage. Typical voltage is 28V.
Flange
Source, Gnd
Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the
board for optimum thermal and RF performance. See mounting instructions for recommendation.
Absolute Maximum Ratings
Pin Diagram
Parameters
Value
Unit
Drain Voltage (VDS )
35
V
Gate Voltage (VGS)
20
V
RF Input Power
+33
dBm
Load Impedance for Continuous Operation
Without Damage
10:1
VSWR
Output Device Channel Temperature
+200
ºC
Lead Temperature During Solder Reflow
+270
ºC
Operating Temperature Range
-20 to +90
ºC
Storage Temperature Range
-40 to +100
ºC
ESD
Protection
Pin 1
Operation of this device beyond any one of these limits may
cause permanent damage. For reliable continuous operation see
typical setup values specified in the table on page one.
Pin 2
Case Flange = Ground
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
2
http://www.sirenza.com
EDS-103754 Rev D
Preliminary
SLD2083CZ 10 Watt LDMOS FET
Typical EVB Test Data
Gain, Efficiency vs. Output Power
20
60
19.9
50
19.8
40
19.7
30
19.6
20
Gain
19.5
Efficiency (%)
Gain (dB)
Freq=915MHz, Temp=25oC, VDS=28V, IDQ=125mA
10
Efficiency
19.4
0
0
2
4
6
8
10
12
14
Output Power (W)
Gain vs. Frequency and Temperature
Pout=10W, VDS=28V, IDQ=125mA
20
Gain (dB)
19.5
19
18.5
90 Deg C
25 Deg C
-20 Deg C
18
17.5
900
905
910
915
920
925
930
Frequency (MHz)
Two Tone IM3 vs. Output Power
Freq=915/916MHz, Temp=25 oC, VDS=28V, IDQ=125mA
-20.0
902MHz
-25.0
915MHz
IMD3(dBc)
-30.0
928MHz
-35.0
-40.0
-45.0
-50.0
-55.0
0.0
2.0
4.0
6.0
Average Output Power (W)
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
3
http://www.sirenza.com
EDS-103754 Rev D
Preliminary
SLD2083CZ 10 Watt LDMOS FET
SLD2083CZ EVB Layout and BoM
Impedance Information (Typical)
Evaluation Board Bill of Materials
Description
Part
Frequency
(MHz)
Input R
(Ohms)
Input X
(Ohms)
Output R
(Ohms)
Output X
(Ohms)
R10
870
0.5
2.0
4.3
1.9
Polarized
J1
880
0.5
1.9
4.3
2.0
Inductor Coilcraft 1.6nH 0603
L1
900
0.8
1.8
4.4
2.0
Res, 0.0, 1/16W, 5%, 0603
R2, R4, R6, R7, R9, R11
930
0.7
1.7
4.5
2.0
Cap, 1000 pF, 100V, 10%, 0603
C7, C8
960
0.8
1.4
4.7
2.0
Cap, 0.01 uF, 100V, 5%, 0805
C10, C15
Cap, 0.5 pF, 250V, +/-.1pF, 0603
C11
Cap, 3.6 pF, 250V, +/-.1pF, 0603
C14
Cap, 12 pF, 250V, 1%, 0603
C2
Cap, 15 pF, 250V, 2%, 0603
C1
Cap, 68 pF, 250V, 5%, 0603
C3, C4, C5, C6
Res, 10 Ohm, 0402
R5, R15
CAP 0.22UF 50V CERAMIC X7R 1206
C13, C16
SLD2083CZ
Q1
Res, 10, 1/10W, 1%, 0805
g
Impedances are circuit impedances as seen
from device at device lead.
To download Gerber files, DXF drawings, a detailed BOM, and
assembly recommendations for the test board with fixture
contact Sirenza applications.
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
4
http://www.sirenza.com
EDS-103754 Rev D
Preliminary
SLD2083CZ 10 Watt LDMOS FET
Package Outline Drawings
Chamferred Lead
is FET Drain
0.290
Lead Coplanarity
Lead foot to backside
0.000 ± 0.002
0.160
0.000±0.002
R0.015
DETAIL A
TOP VIEW
0.200
0.160
0.100
0.090
0.140
0.050
0.008
0.160
SIDE VIEW
END VIEW
DETAIL A
Recommended Landing Pads for the RF083 Package
Part Number Ordering Information
Part Number
Devices Per Reel
Reel Size
SLD2083CZ
500
7’’
All Dimensions are in inches
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
5
http://www.sirenza.com
EDS-103754 Rev D