SN54GTL16622A, SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999 D D D D D D D D D D Members of the Texas Instruments Widebus Family D-Type Flip-Flops With Qualified Storage Enable Translate Between GTL/GTL+ Signal Levels and LVTTL Logic Levels Support Mixed-Mode (3.3 V and 5 V) Signal Operation on A-Port and Control Inputs Ioff Supports Partial-Power-Down Mode Operation Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on A Port ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Latch-Up Performance Exceeds 250 mA Per JESD 17 Distributed VCC and GND-Pin Configuration Minimizes High-Speed Noise Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Ceramic Quad Flat (HV) Packages SN74GTL16622A . . . DGG PACKAGE (TOP VIEW) OEAB 1A1 GND 1A2 1A3 GND VCC 1A4 GND 1A5 1A6 GND 1A7 1A8 GND 1A9 2A1 GND 2A2 2A3 GND 2A4 2A5 GND 2A6 VCC GND 2A7 2A8 GND 2A9 OEBA description The ’GTL16622A devices are 18-bit registered bus transceivers that provide LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. They are partitioned as two separate 9-bit transceivers with individual clock-enable controls and contain D-type flip-flops for temporary storage of data flowing in either direction. The devices provide an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and output edge control (OEC). 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 CLKAB 1CEAB 1CEBA 1B1 GND 1B2 1B3 VCC 1B4 1B5 1B6 GND 1B7 1B8 GND 1B9 2B1 GND 2B2 2B3 GND 2B4 2B5 2B6 VREF 2B7 2B8 GND 2B9 2CEBA 2CEAB CLKBA The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OEC and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54GTL16622A, SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999 description (continued) Data flow in each direction is controlled by the output-enable (OEAB and OEBA) and clock (CLKAB and CLKBA) inputs. The clock-enable (CEAB and CEBA) inputs are designed to control each 9-bit transceiver independently, which makes the device more versatile. For A-to-B data flow, the device operates on the low-to-high transition of CLKAB if CEAB is low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, CLKBA, and CEBA. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54GTL16622A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74GTL16622A is characterized for operation from –40°C to 85°C. 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 GND 2A7 2A8 GND 2A9 OEBA NC CLKBA 2CEAB 2CEBA 2B9 GND 2B8 2B7 VREF 10 2A6 V CC GND 1A5 1A6 GND 1A7 1A8 GND 1A9 NC 2A1 GND 2A2 2A3 GND 2A4 2A5 GND GND 1A3 1A2 GND 1A1 OEAB NC CLKAB 1CEAB 1CEBA 1B1 GND 1B2 1B3 VCC 1A4 VCC SN54GTL16622A . . . HV PACKAGE (TOP VIEW) NC – No internal connection 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1B4 1B5 1B6 GND 1B7 1B8 GND 1B9 NC 2B1 GND 2B2 2B3 GND 2B4 2B5 2B6 SN54GTL16622A, SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999 FUNCTION TABLE† INPUTS CEAB OEAB CLKAB A OUTPUT B MODE X H X X Z Isolation H L X X X L H or L X B0‡ B0‡ Latched storage of A data L L ↑ L L L L ↑ H H Clocked storage of A data † A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, CLKBA, and CEBA. ‡ Output level before the indicated steady-state input conditions are established POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54GTL16622A, SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999 logic diagram (positive logic) VREF OEAB 1CEAB CLKAB CLKBA 1CEBA OEBA 1A1 40 1 63 64 33 62 32 CE 2 61 1D 1B1 CLK CE 1D CLK To Eight Other Channels 2CEAB 2CEBA 2A1 34 35 CE 17 1D CLK CE 1D CLK To Eight Other Channels Pin numbers shown are for the DGG package. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 48 2B1 SN54GTL16622A, SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): A-port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V B port and VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Voltage range applied to any output in the high or power-off state, VO (see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Current into any output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Current into any A-port output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Notes 4 through 6) SN54GTL16622A SN74GTL16622A MIN NOM MAX MIN NOM MAX 3.15 3.3 3.45 3.15 3.3 3.45 GTL 1.14 1.2 1.26 1.14 1.2 1.26 GTL+ 1.35 1.5 1.65 1.35 1.5 1.65 GTL 0.74 0.8 0.87 0.74 0.8 0.87 GTL+ 0.87 1 1.1 0.87 1 1.1 VCC Supply voltage VTT Termination voltage VREF Supply voltage VI Input voltage VIH High-level g input voltage B port VIL Low-level input voltage B port IIK Input clamp current IOH High-level output current IOL Low-level output current B port VTT 5.5 Except B port Except B port VREF+50 mV 2 VTT 5.5 VREF+50 mV 2 UNIT V V V V V VREF–50 mV 0.8 VREF –50 mV 0.8 V –18 –18 mA A port –24 –24 mA A port 24 24 B port 50 50 Except B port mA TA Operating free-air temperature –55 125 –40 85 °C NOTES: 4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5. Normal connection sequence is GND first and VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. 6. VTT and RTT can be adjusted to accommodate backplane impedances as long as they do not exceed the DC absolute IOL ratings. Similarly, VREF can be adjusted to optimize noise margins, but normally is 2/3 VTT. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54GTL16622A, SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999 electrical characteristics over recommended operating free-air temperature range for GTL/GTL+ (unless otherwise noted) PARAMETER VIK VOH A port VOL B port B port A-port and control inputs Ioff II(hold) ( ) IOZ§ IOZH ICC Ciio 3 15 V VCC = 3.15 –1.2 VCC–0.2 2.4 IOH = –12 mA IOH = –24 mA 0.2 0.4 0.5 0.5 VCC = 3.15 V to 3.45 V, IOL = 100 µA IOL = 10 mA 0.2 0.2 0.2 0.2 VCC = 3.45 V 3 45 V VCC = 3.45 IOL = 40 mA IOL = 50 mA VI = VTT or GND VI = VCC or GND VI = 5.5 V or GND VI or VO = 0 to 5.5 V A port VCC = 3.45 V‡, VCC = 3.45 V, VI = 0.8 V to 2 V VO = VCC or GND B port VCC = 3.45 V, Control inputs A port B port VCC = 3.45 V, IO = 0, VI = VCC or GND V 2 0.4 VCC = 3.15 V UNIT V 0.2 VCC = 3.15 3 15 V A or B port –1.2 VCC–0.2 2.4 2 VI = 0.8 V VI = 2 V A port SN74GTL16622A TYP† MAX MIN VCC = 3.15 V to 3.45 V, IOL = 100 µA IOL = 12 mA VCC = 3.15 3 15 V IOL = 24 mA VCC = 0, ∆ICC¶ Ci MIN VCC = 3.15 V, II = –18 mA VCC = 3.15 V to 3.45 V, IOH = –100 µA A port II SN54GTL16622A TYP† MAX TEST CONDITIONS 0.4 0.4 0.55 0.55 ±5 ±5 ±5 ±5 ±20 ±20 100 75 100 V µA µA 75 –75 µA –75 ±500 ±500 ±10 ±10 µA VO = 1.5 V Outputs high 10 10 µA 60 60 Outputs low 60 60 Outputs disabled 60 60 500 500 µA pF VCC = 3.45 V, A-port or control inputs at VCC or GND, One input at VCC – 0.6 V VI = 3.15 V or 0 2.5 3 2.5 3 6 8.5 6 8 7 9.5 6.5 8.5 15 V or 0 VO = 3 3.15 mA pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. § For I/O ports, the parameter IOZ includes the input leakage current. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54GTL16622A, SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999 timing requirements over recommended ranges of supply voltage and operating free-air temperature for GTL (unless otherwise noted) SN54GTL16622A MIN fclock tw Clock frequency Setup time th Hold time MIN 200 Pulse duration, CLK high or low tsu SN74GTL16622A MAX MAX 200 2.5 2.5 Data before CLK↑ 2.5 2.1 CE before CLK↑ 3.5 3.3 Data after CLK↑ 0.3 0.3 CE after CLK↑ 0.3 0 UNIT MHz ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature for GTL (see Figure 1) PARAMETER fmax tPLH tPHL tdis ten Slew rate tr tf FROM (INPUT) TO (OUTPUT) CLKAB B OEAB B SN54GTL16622A MIN TYP† MAX SN74GTL16622A MIN TYP† MAX UNIT 200 200 MHz 2.4 5.7 2.5 5.5 2.1 5.7 2.2 5.5 1.6 5 1.7 4.8 2.1 5.5 2.2 5.2 Both transitions (B port) 0.5 0.5 ns ns V/ns Transition time, B outputs (0.6 V to 1 V) 0.5 2.3 0.6 2.2 ns Transition time, B outputs (1 V to 0.6 V) 0.3 1.7 0.4 1.5 ns 1.9 5.5 2.1 5.3 1.8 5.3 2.1 5 1.6 5.3 1.7 5 2 5.8 2.3 5.5 tPLH tPHL CLKBA A ten tdis OEBA A ns ns † All typical values are at VCC = 3.3 V, TA = 25°C. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54GTL16622A, SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999 timing requirements over recommended ranges of supply voltage and operating free-air temperature for GTL+ (unless otherwise noted) SN54GTL16622A MIN fclock tw Clock frequency Setup time th Hold time MIN MAX 200 Pulse duration, CLK high or low tsu SN74GTL16622A MAX 200 2.5 2.5 Data before CLK↑ 2.5 2.4 CE before CLK↑ 3.4 3.2 Data after CLK↑ 0.3 0.2 CE after CLK↑ 0.1 0 UNIT MHz ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature for GTL+ (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL Slew rate tr tf FROM (INPUT) TO (OUTPUT) CLKAB B OEAB B SN54GTL16622A MIN TYP† MAX SN74GTL16622A MIN TYP† MAX UNIT 200 200 MHz 2.5 5.8 2.6 4 5.6 2.2 6.1 2.3 4 5.7 2.3 5.5 2.4 3.8 5.2 1.7 5.3 1.8 3.4 5 Both transitions (B port) 0.5 ns V/ns Transition time, B outputs (0.6 V to 1.3 V) 0.9 2.8 1 1.6 2.7 ns Transition time, B outputs (1.3 V to 0.6 V) 0.4 3.7 0.5 1.1 3.2 ns 1.9 5.5 2 3.8 5.3 1.8 5.3 1.9 3.6 5 1.8 5.3 1.9 3.6 5 2 5.8 2.1 4 5.5 tPLH tPHL CLKBA A ten tdis OEBA A † All typical values are at VCC = 3.3 V, TA = 25°C. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 8 0.5 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns SN54GTL16622A, SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION VTT 6V S1 500 Ω From Output Under Test Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND CL = 50 pF (see Note A) 500 Ω 25 Ω S1 Open 6V GND From Output Under Test CL = 30 pF (see Note A) LOAD CIRCUIT FOR A OUTPUTS Test Point LOAD CIRCUIT FOR B OUTPUTS tw 3V 3V Input 1.5 V 1.5 V Timing Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION Input (see Note B) 3V 1.5 V 1.5 V tsu th 3V Data Input A Port 1.5 V Data Input B Port VREF 1.5 V 0V VTT VREF 0V 0V tPLH VOLTAGE WAVEFORMS SETUP AND HOLD TIMES tPHL VOH Output VREF VREF VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (CLKAB to B port) Input (see Note B) 1.5 V 0V tPLH 1.5 V 1.5 V VOL tPLZ 3V 1.5 V Output Waveform 2 S1 at GND (see Note C) VOL + 0.3 V VOL tPHZ tPZH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (CLKBA to A port) 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note C) tPHL VOH Output 1.5 V tPZL 3V 1.5 V 3V Output Control (see Note B) 1.5 V VOH VOH – 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (OEBA to A port) NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated