SN54ALS29823, SN74ALS29823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS146B – JANUARY 1986 – REVISED JANUARY 1995 • • • • • • SN54ALS29823 . . . JT PACKAGE SN74ALS29823 . . . DW OR NT PACKAGE (TOP VIEW) Functionally Equivalent to AMD’s AM29823 Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance State Buffered Control Inputs Reduce dc Loading Effects Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs OE 1D 2D 3D 4D 5D 6D 7D 8D 9D CLR GND description 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q CLKEN CLK These 9-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers, parity bus interfacing, and working registers. With the clock-enable (CLKEN) input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock (CLK) input. Taking CLKEN high disables the clock buffer, latching the outputs. The ′ALS29823 have noninverting data (D) inputs. Taking the clear (CLR) input low causes the nine Q outputs to go low independently of the clock. A buffered output-enable (OE) input places the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs also are in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS29823 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ALS29823 is characterized for operation from 0°C to 70°C. FUNCTION TABLE (each flip-flop) INPUTS OE CLR CLKEN CLK D OUTPUT Q L L X X X L L H L ↑ H H L H L ↑ L L L H H X X Q0 H X X X X Z Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS29823, SN74ALS29823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS146B – JANUARY 1986 – REVISED JANUARY 1995 logic symbol† OE CLR CLKEN CLK 1D 2D 3D 4D 5D 6D 7D 8D 9D 1 11 14 13 2 EN R G1 1C2 23 2D 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OE CLR CLKEN CLK 1 11 14 R 13 C1 1D 2 1D To Eight Other Channels 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 1Q SN54ALS29823, SN74ALS29823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS146B – JANUARY 1986 – REVISED JANUARY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to a disabled high-impedance output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA: SN54ALS29823 . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54ALS29823 MIN NOM MAX 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 V High-level output current – 18 mA IOL Low-level output current 32 mA tw Pulse duration tsu Setup time before CLK↑ High-level input voltage th Hold time after CLK↑ TA Operating free-air temperature 2 CLR low 7 CLK high or low 8 CLR inactive 7 Data 4 CLKEN high or low 8 CLKEN 2 Data 4 – 55 V V ns ns ns 25 125 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 4.5 V, VOH VCC = 4 4.5 5V VOL IOZH VCC = 4.5 V, VCC = 5.5 V, IOZL II VCC = 5.5 V, VCC = 5.5 V, IIH IIL VCC = 5.5 V, VCC = 5.5 V, IOS§ VCC = 5.5 V, ICC VCC = 5.5 V II = – 18 mA IOH = – 12 mA IOH = – 18 mA IOL = 32 mA SN54ALS29823 MIN TYP‡ MAX – 1.2 2.4 3.3 VO = 2.4 V VO = 0.4 V 0.5 V 50 µA – 50 µA VI = 5.5 V VI = 2.7 V 0.1 mA 20 µA VI = 0.4 V VO = 0 – 0.5 mA – 250 mA – 75 Outputs high 90 Outputs low 105 Outputs open ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. POST OFFICE BOX 655303 V V 2 0.25 UNIT • DALLAS, TEXAS 75265 mA 115 3 SN54ALS29823, SN74ALS29823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS146B – JANUARY 1986 – REVISED JANUARY 1995 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS VCC = MIN to MAX†, TA = MIN to MAX† SN54ALS29823 MIN MAX 2 11.5 2 11.5 tPLH tPHL CLK An Q Any CL = 50 pF tPLH tPHL CLK 2 21 An Q Any CL = 300 pF 2 21 CLR Any Q CL = 50 pF 1 17.5 1 17 OE An Q Any CL = 50 pF 1 17 1 25 OE An Q Any CL = 300 pF 1 29.5 1 16 OE An Q Any CL = 50 pF 1 14 tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ 1 OE Any Q CL = 5 pF tPLZ 1 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. UNIT ns ns ns ns ns ns 12 ns 11 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA: SN74ALS29823 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN74ALS29823 VCC VIH Supply voltage VIL IOH Low-level input voltage IOL tw tsu High-level input voltage NOM MAX 4.75 5 5.25 2 UNIT V V 0.8 V High-level output current – 24 mA Low-level output current 48 mA Pulse duration Setup time before CLK↑ th Hold time after CLK↑ TA Operating free-air temperature 4 MIN CLR low 5 CLK high or low 5 CLR inactive 5 Data 2 CLKEN high or low 6 CLKEN 0 Data 2 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns ns 25 70 °C SN54ALS29823, SN74ALS29823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS146B – JANUARY 1986 – REVISED JANUARY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER SN74ALS29823 TYP† MAX TEST CONDITIONS VIK VCC = 4.75 V, VOH VCC = 4 4.75 75 V VOL IOZH VCC = 4.75 V, VCC = 5.25 V, IOZL II VCC = 5.25 V, VCC = 5.25 V, IIH IIL VCC = 5.25 V, VCC = 5.25 V, IOS‡ ICC VCC = 5.25 V, VCC = 5.25 V, MIN II = – 18 mA IOH = – 15 mA IOH = – 24 mA IOL = 48 mA – 1.2 2.4 3.3 2 3.1 0.5 V 20 µA – 20 µA 0.1 mA 20 µA VI = 5.5 V VI = 2.7 V VI = 0.4 V VO = 0 – 75 Outputs open 80 V V 0.35 VO = 2.4 V VO = 0.4 V UNIT – 0.2 mA – 250 mA 115 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS VCC = MIN to MAX§, TA = MIN to MAX§ SN74ALS29823 MIN MAX 2 10 2 10 tPLH tPHL CLK An Q Any CL = 50 pF tPLH tPHL CLK An Q Any CL = 300 pF 16 CLR Any Q CL = 50 pF 12 tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ 16 14 OE An Q Any CL = 50 pF OE An Q Any CL = 300 pF OE An Q Any CL = 50 pF OE Any Q CL = 5 pF 14 20 23 14 tPLZ § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12 9 9 UNIT ns ns ns ns ns ns ns 5 SN54ALS29823, SN74ALS29823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS146B – JANUARY 1986 – REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION Test Point VCC SWITCH POSITION TABLE S1 From Output Under Test RL = 180 Ω All Diodes 1N916 or 1N3064 R1 1 kΩ CL (see Note A) S2 TEST S1 S2 tPLH tPHL tPZH tPZL tPHZ tPLZ Closed Closed Open Closed Closed Closed Closed Closed Closed Open Closed Closed LOAD CIRCUIT 3V 1.5 V Timing Input High-Level Pulse 3V 1.5 V 0 0 tw th tsu 1.5 V 3V 3V 1.5 V 1.5 V Data Input 0 Low-Level Pulse 1.5 V 1.5 V 0 VOLTAGE WAVEFORMS PULSE DURATIONS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Output Control 1.5 V 1.5 V 0 tPZL tPLZ ≈ 4.5 V 3V Input 1.5 V 1.5 V 0 1.5 V 1.5 V VOL tPHZ VOH 1.5 V VOH Waveform 2 (see Note B) 1.5 V 1.5 V 0.5 V ≈ 1.5 V ≈0 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 0.5 V tPZH tPLH tPHL ≈ 1.5 V VOL VOH In-Phase Output 1.5 V tPHL tPLH Out-of-Phase Output Waveform 1 (see Note B) VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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