LP3871 LP3874 www.ti.com SNVS225G – FEBRUARY 2003 – REVISED APRIL 2013 LP3871/LP3874 0.8A Fast Ultra Low Dropout Linear Regulators Check for Samples: LP3871, LP3874 FEATURES DESCRIPTION • • • • • • The LP3871/LP3874 series of fast ultra low-dropout linear regulators operate from a +2.5V to +7.0V input supply. Wide range of preset output voltage options are available. These ultra low dropout linear regulators respond very quickly to step changes in load, which makes them suitable for low voltage microprocessor applications. The LP3871/LP3874 are developed on a CMOS process which allows low quiescent current operation independent of output load current. This CMOS process also allows the LP3871/LP3874 to operate under extremely low dropout conditions. 1 2 • • • • • • Ultra Low Dropout Voltage Low Ground Pin Current Load Regulation of 0.04% 10nA Quiescent Current in Shutdown Mode Specified Output Current of 0.8A DC Available in DDPAK/TO-263, TO-220 and SOT-223 Packages Output Voltage Accuracy ±1.5% Error Flag Indicates Output Status Sense Option Improves Load Regulation Minimum Output Capacitor Requirements Overtemperature/Overcurrent Protection −40°C to +125°C Junction Temperature Range Dropout Voltage: Ultra low dropout voltage; typically 24mV at 80mA load current and 240mV at 0.8A load current. Ground Pin Current: Typically 6mA at 0.8A load current. APPLICATIONS • • • • • • • • Shutdown Mode: Typically 10nA quiescent current when the shutdown pin is pulled low. Microprocessor Power Supplies GTL, GTL+, BTL, and SSTL Bus Terminators Power Supplies for DSPs SCSI Terminator Post Regulators High Efficiency Linear Regulators Battery chargers Other Battery Powered Applications Error Flag: Error flag goes low when the output voltage drops 10% below nominal value. SENSE: Sense pin improves regulation at remote loads. Precision Output Voltage: Multiple output voltage options are available ranging from 1.8V to 5.0V with a ensured accuracy of ±1.5% at room temperature, and ±3.0% over all conditions (varying line, load, and temperature). TYPICAL APPLICATION CIRCUITS INPUT 3.3 V V OUT VIN CIN 10 µF + LP3871-2.5 SD SD* SENSE GND COUT 10 µF VOUT 2.5V, 0.8A ERROR* *SD and ERROR pins must be pulled high through a 10kΩ pull-up resistor. Connect the ERROR pin to ground if this function is not used. See application hints for more information. INPUT 3.3 V ± 10% V IN CIN 10 µF V OUT LP3874-2.5 SD* SD SENSE GND + C OUT 10 µF VOUT 2.5V, 0.8A *SD must be pulled high through a 10kΩ pull-up resistor. See application hints for more information. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2013, Texas Instruments Incorporated LP3871 LP3874 SNVS225G – FEBRUARY 2003 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. CONNECTION DIAGRAM Figure 1. 5-Lead TO-220 (Top View) See NDH0005D Package Figure 2. 5-Lead DDPAK/TO-263 (Top View) See KTT Package GND 5 1 2 3 SD VIN VOUT 4 ERROR /SENSE Figure 3. SOT-223 (Top View) See NDC0005A Package Table 1. PIN DESCRIPTIONS for TO-220 and DDPAK/TO-263 Packages Pin # LP3871 Name LP3874 Function Name Function 1 SD Shutdown SD Shutdown 2 VIN Input Supply VIN Input Supply 3 GND Ground GND Ground 4 VOUT Output Voltage VOUT Output Voltage 5 ERROR ERROR Flag SENSE Remote Sense Pin Table 2. PIN DESCRIPTIONS for SOT-223 Package Pin # 2 LP3871 Name LP3874 Function Name Function 1 SD Shutdown SD Shutdown 2 VIN Input Supply VIN Input Supply 3 VOUT 4 ERROR 5 GND Output Voltage ERROR Flag Ground Submit Documentation Feedback VOUT SENSE GND Output Voltage Remote Sense Pin Ground Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3871 LP3874 LP3871 LP3874 www.ti.com SNVS225G – FEBRUARY 2003 – REVISED APRIL 2013 BLOCK DIAGRAM Figure 4. LP3871 Figure 5. LP3874 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3871 LP3874 3 LP3871 LP3874 SNVS225G – FEBRUARY 2003 – REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS www.ti.com (1) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and specifications. VALUE / UNITS −65°C to +150°C Storage Temperature Range Lead Temperature (Soldering, 5 sec.) ESD Rating 260°C (2) Power Dissipation 2 kV (3) Internally Limited −0.3V to +7.5V Input Supply Voltage (Survival) −0.3V to 7.5V Shutdown Input Voltage (Survival) Output Voltage (Survival) (4) (5) −0.3V to +6.0V IOUT (Survival) Short Circuit Protected Maximum Voltage for ERROR Pin VIN Maximum Voltage for SENSE Pin VOUT (1) (2) (3) (4) (5) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is intended to be functional, but does not ensure specific performance limits. For specifications and test conditions, see Electrical Characteristics. The specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO-220 package must be derated at θjA = 50°C/W (with 0.5in2, 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the DDPAK/TO-263 surface-mount package must be derated at θjA = 60°C/W (with 0.5in2, 1oz. copper area), junction-to-ambient. The SOT-223 package must be derated at θjA = 90°C/W (with 0.5in2, 1oz. copper area), junction-to-ambient If used in a dual-supply system where the regulator load is returned to a negative supply, the output must be diode-clamped to ground. The output PMOS structure contains a diode between the VIN and VOUT terminals. This diode is normally reverse biased. This diode will get forward biased if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can typically withstand 200mA of DC current and 1Amp of peak current. RECOMMENDED OPERATING CONDITIONS VALUE / UNITS Input Supply Voltage (1) 2.5V to 7.0V −0.3V to 7.0V Shutdown Input Voltage Maximum Operating Current (DC) 0.8A −40°C to +125°C Junction Temperature (1) 4 The minimum operating value for VIN is equal to either [VOUT(NOM) + VDROPOUT] or 2.5V, whichever is greater. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3871 LP3874 LP3871 LP3874 www.ti.com SNVS225G – FEBRUARY 2003 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS — LP3871/LP3874 Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, IL = 10 mA, COUT = 10µF, VSD = 2V. Symbol Parameter Conditions Typ (1) LP3871/4 (2) Min Max -1.5 -3.0 +1.5 +3.0 Units VO Output Voltage Tolerance (3) ΔV OL Output Voltage Line Regulation (3) VOUT + 1V ≤ VIN ≤ 7.0V 0.02 0.06 % ΔVO/ ΔIOUT Output Voltage Load Regulation (3) 0.04 0.1 % VIN - VOUT Dropout Voltage IGND IGND IO(PK) VOUT +1V ≤ VIN ≤ 7.0V, 10 mA ≤ IL ≤ 0.8A 10 mA ≤ IL ≤ 0.8A 0 IL = 80 mA 24 35 40 IL = 0.8A 240 300 350 IL = 80 mA 5 9 10 IL = 0.8A 6 14 15 0.01 10 (4) Ground Pin Current In Normal Operation Mode Ground Pin Current In Shutdown Mode VSD ≤ 0.3V Peak Output Current VO ≥ VO(NOM) - 4% -40°C ≤ TJ ≤ 85°C % mV mA µA 50 1 A 2.3 A Short Circuit Protection ISC Short Circuit Current Shutdown Input Output = High VIN Output = Low 0 Turn-off delay IL = 0.8A 20 Turn-on delay IL = 0.8A 25 µs SD Input Current VSD = VIN 1 nA VSDT Shutdown Threshold TdOFF TdON ISD 2 V 0.3 µs Error Flag (5) VT Threshold (5) 10 5 16 % VTH Threshold Hysteresis (5) 5 2 8 % VEF(Sat) Error Flag Saturation Td Flag Reset Delay 1 µs Ilk Error Flag Pin Leakage Current 1 nA Imax Error Flag Pin Sink Current VError = 0.5V 1 mA VIN = VOUT + 1V, COUT = 10µF, VOUT = 3.3V, f = 120Hz 73 VIN = VOUT + 0.5V, COUT = 10µF, VOUT = 3.3V, f = 120Hz 57 f = 120Hz 0.8 BW = 10Hz – 100kHz, VOUT = 2.5V 150 BW = 300Hz – 300kHz, VOUT = 2.5V 100 Isink = 100µA 0.02 0.1 V AC Parameters PSRR Ripple Rejection ρn(l/f) Output Noise Density en Output Noise Voltage (1) (2) (3) (4) (5) dB µV µV (rms) Typical numbers are at 25°C and represent the most likely parametric norm. Limits are specified by testing, design, or statistical correlation. Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage. Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in load current. The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the output voltage tolerance specification. Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. Dropout voltage specification applies only to output voltages of 2.5V and above. For output voltages below 2.5V, the drop-out voltage is nothing but the input to output differential, since the minimum input voltage is 2.5V. Error Flag threshold and hysteresis are specified as percentage of regulated output voltage. See Application Hints. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3871 LP3874 5 LP3871 LP3874 SNVS225G – FEBRUARY 2003 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS Unless ohterwise specified: TJ = 25°C, COUT = 10µF, CIN = 10µF, S/D pin is tied to VIN, VOUT = 2.5V, VIN = VO(NOM) + 1V, IL = 10 mA Ground Current vs Output Voltage IL = 800mA Dropout Voltage vs Output Load Current 500 6 o 125 C 300 25oC 200 -40oC 100 5 GROUND PIN CURRENT (mA)_ DROPOUT VOLTAGE (mV) 400 4 3 2 1 0 0 0.5 0 1.8 1.0 2.3 2.8 3.3 3.8 4.3 5.0 LOAD CURRENT (A) OUTPUT VOLTAGE (V) Figure 6. Figure 7. Shutdown IQ vs Junction Temperature Errorflag Threshold vs Junction Temperature 14 ERROR THRESHOLD (% of VOUT) 10 SHUTDOWN IQ (PA) 1 0.1 0.01 0.001 -40 -20 12 10 8 6 4 2 0 0 20 40 60 80 -40 -20 100 125 TEMPERATURE ( C) 40 60 80 100 125 Figure 9. DC Load Reg. vs Junction Temperature DC Line Regulation vs Temperature 3 ' VOUT/VOLT CHANGE in VIN (mV) DC LOAD REGULATION (mV/A) 20 Figure 8. 3 2.5 2 1.5 1 0.5 0 -40 -20 0 20 40 60 80 2.5 2 1.5 1 0.5 100 125 o 6 0 JUNCTION TEMPERATURE (oC) o 0 -40 -20 0 20 40 60 80 100 125 o JUNCTION TEMPERATURE ( C) JUNCTION TEMPERATURE ( C) Figure 10. Figure 11. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3871 LP3874 LP3871 LP3874 www.ti.com SNVS225G – FEBRUARY 2003 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless ohterwise specified: TJ = 25°C, COUT = 10µF, CIN = 10µF, S/D pin is tied to VIN, VOUT = 2.5V, VIN = VO(NOM) + 1V, IL = 10 mA Load Transient Response CIN =COUT = 10µF, OSCON Noise vs Frequency 3.000 VOUT 100mV/DIV 2.500 MAGNITUDE NOISE (PV/ Hz ( IL = 100mA CIN = COUT = 10PF 2.000 1.500 1.000 ILOAD 1A/DIV 0.500 0.000 100 1k 10k TIME (50Ps/DIV) 100k FREQUENCY (Hz) Figure 12. Figure 13. Load Transient Response CIN =COUT = 100µF, OSCON Load Transient Response CIN =COUT = 100µF, POSCAP VOUT 100mV/DIV MAGNITUDE MAGNITUDE VOUT 100mV/DIV ILOAD 1A/DIV ILOAD 1A/DIV TIME (50Ps/DIV) TIME (50Ps/DIV) Figure 14. Figure 15. Load Transient Response CIN =COUT = 10µF, TANTALUM Load Transient Response CIN =COUT = 100µF, TANTALUM VOUT 100mV/DIV MAGNITUDE MAGNITUDE VOUT 100mV/DIV ILOAD 1A/DIV ILOAD 1A/DIV TIME (50Ps/DIV) TIME (50Ps/DIV) Figure 16. Figure 17. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3871 LP3874 7 LP3871 LP3874 SNVS225G – FEBRUARY 2003 – REVISED APRIL 2013 www.ti.com Application Hints EXTERNAL CAPACITORS Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be correctly selected for proper performance. INPUT CAPACITOR: An input capacitor of at least 10µF is required. Ceramic, Tantalum, or Electrolytic capacitors may be used, and capacitance may be increased without limit. OUTPUT CAPACITOR: An output capacitor is required for loop stability. It must be located less than 1 cm from the device and connected directly to the output and ground pins using traces which have no other currents flowing through them (see PCB Layout section). The minimum value of output capacitance that can be used for stable full-load operation is 10µF, but it may be increased without limit. The output capacitor must have an ESR value as shown in the stable region of the curve (below).Tantalum capacitors are recommended for the output capacitor. 10 COUT ESR (:) 1.0 COUT > 10PF STABLE REGION 0.1 .01 .001 0 0.2 0.4 0.6 0.8 1 LOAD CURRENT (A) Figure 18. ESR Curve SELECTING A CAPACITOR It is important to note that capacitance tolerance and variation with temperature must be taken into consideration when selecting a capacitor so that the minimum required amount of capacitance is provided over the full operating temperature range. In general, a good Tantalum capacitor will show very little capacitance variation with temperature, but a ceramic may not be as good (depending on dielectric type). Aluminum electrolytics also typically have large temperature variation of capacitance value. Equally important to consider is a capacitor's ESR change with temperature: this is not an issue with ceramics, as their ESR is extremely low. However, it is very important in Tantalum and aluminum electrolytic capacitors. Both show increasing ESR at colder temperatures, but the increase in aluminum electrolytic capacitors is so severe they may not be feasible for some applications (see Capacitor Characteristics Section). CAPACITOR CHARACTERISTICS CERAMIC: For values of capacitance in the 10 to 100 µF range, ceramics are usually larger and more costly than tantalums but give superior AC performance for bypassing high frequency noise because of very low ESR (typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a function of voltage and temperature. Z5U and Y5V dielectric ceramics have capacitance that drops severely with applied voltage. A typical Z5U or Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. The Z5U and Y5V also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of the temperature range. X7R and X5R dielectric ceramic capacitors are strongly recommended if ceramics are used, as they typically maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage. Of course, they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance. 8 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3871 LP3874 LP3871 LP3874 www.ti.com SNVS225G – FEBRUARY 2003 – REVISED APRIL 2013 TANTALUM: Solid Tantalum capacitors are recommended for use on the output because their typical ESR is very close to the ideal value required for loop compensation. They also work well as input capacitors if selected to meet the ESR requirements previously listed. Tantalums also have good temperature stability: a good quality Tantalum will typically show a capacitance value that varies less than 10-15% across the full temperature range of 125°C to −40°C. ESR will vary only about 2X going from the high to low temperature limits. The increasing ESR at lower temperatures can cause oscillations when marginal quality capacitors are used (if the ESR of the capacitor is near the upper limit of the stability range at room temperature). ALUMINUM: This capacitor type offers the most capacitance for the money. The disadvantages are that they are larger in physical size, not widely available in surface mount, and have poor AC performance (especially at higher frequencies) due to higher ESR and ESL. Compared by size, the ESR of an aluminum electrolytic is higher than either Tantalum or ceramic, and it also varies greatly with temperature. A typical aluminum electrolytic can exhibit an ESR increase of as much as 50X when going from 25°C down to −40°C. It should also be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance specified at a higher frequency (between 20 kHz and 100 kHz) should be used for the LP387X. Derating must be applied to the manufacturer's ESR specification, since it is typically only valid at room temperature. Any applications using aluminum electrolytics should be thoroughly tested at the lowest ambient operating temperature where ESR is maximum. TURN-ON CHARACTERISTICS FOR OUTPUT VOLTAGES PROGRAMMED TO 2.0V OR BELOW As Vin increases during start-up, the regulator output will track the input until Vin reaches the minimum operating voltage (typically about 2.2V). For output voltages programmed to 2.0V or below, the regulator output may momentarily exceed its programmed output voltage during start up. Outputs programmed to voltages above 2.0V are not affected by this behavior. PCB LAYOUT Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops. The input and output capacitors must be directly connected to the input, output, and ground pins of the regulator using traces which do not have other currents flowing in them (Kelvin connect). The best way to do this is to lay out CIN and COUT near the device with short traces to the VIN, VOUT, and ground pins. The regulator ground pin should be connected to the external circuit ground so that the regulator and its capacitors have a "single point ground". It should be noted that stability problems have been seen in applications where "vias" to an internal ground plane were used at the ground points of the IC and the input and output capacitors. This was caused by varying ground potentials at these nodes resulting from current flowing through the ground plane. Using a single point ground technique for the regulator and it's capacitors fixed the problem. Since high current flows through the traces going into VIN and coming from VOUT, Kelvin connect the capacitor leads to these pins so there is no voltage drop in series with the input and output capacitors. RFI/EMI SUSCEPTIBILITY RFI (radio frequency interference) and EMI (electromagnetic interference) can degrade any integrated circuit's performance because of the small dimensions of the geometries inside the device. In applications where circuit sources are present which generate signals with significant high frequency energy content (> 1 MHz), care must be taken to ensure that this does not affect the IC regulator. If RFI/EMI noise is present on the input side of the regulator (such as applications where the input source comes from the output of a switching regulator), good ceramic bypass capacitors must be used at the input pin of the IC. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3871 LP3874 9 LP3871 LP3874 SNVS225G – FEBRUARY 2003 – REVISED APRIL 2013 www.ti.com If a load is connected to the IC output which switches at high speed (such as a clock), the high-frequency current pulses required by the load must be supplied by the capacitors on the IC output. Since the bandwidth of the regulator loop is less than 100 kHz, the control circuitry cannot respond to load changes above that frequency. This means the effective output impedance of the IC at frequencies above 100 kHz is determined only by the output capacitor(s). In applications where the load is switching at high speed, the output of the IC may need RF isolation from the load. It is recommended that some inductance be placed between the output capacitor and the load, and good RF bypass capacitors be placed directly across the load. PCB layout is also critical in high noise environments, since RFI/EMI is easily radiated directly into PC traces. Noisy circuitry should be isolated from "clean" circuits where possible, and grounded through a separate path. At MHz frequencies, ground planes begin to look inductive and RFI/EMI can cause ground bounce across the ground plane. In multi-layer PCB applications, care should be taken in layout so that noisy power and ground planes do not radiate directly into adjacent layers which carry analog power and ground. OUTPUT NOISE Noise is specified in two waysSpot Noise or Output noise density is the RMS sum of all noise sources, measured at the regulator output, at a specific frequency (measured with a 1Hz bandwidth). This type of noise is usually plotted on a curve as a function of frequency. Total output Noise or Broad-band noise is the RMS sum of spot noise over a specified bandwidth, usually several decades of frequencies. Attention should be paid to the units of measurement. Spot noise is measured in units µV/√Hz or nV/√Hz and total output noise is measured in µV(rms). The primary source of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a low frequency component and a high frequency component, which depend strongly on the silicon area and quiescent current. Noise can be reduced in two ways: by increasing the transistor area or by increasing the current drawn by the internal reference. Increasing the area will decrease the chance of fitting the die into a smaller package. Increasing the current drawn by the internal reference increases the total supply current (ground pin current). Using an optimized trade-off of ground pin current and die size, LP3871/LP3874 achieves low noise performance and low quiescent current operation. The total output noise specification for LP3871/LP3874 is presented in the Electrical Characteristics table. The Output noise density at different frequencies is represented by a curve under typical performance characteristics. SHORT-CIRCUIT PROTECTION The LP3871 and LP3874 are short circuit protected and in the event of a peak over-current condition, the shortcircuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to the section on thermal information for power dissipation calculations. ERROR FLAG OPERATION The LP3871/LP3874 produces a logic low signal at the Error Flag pin when the output drops out of regulation due to low input voltage, current limiting, or thermal limiting. This flag has a built in hysteresis. The timing diagram in Figure 19 shows the relationship between the ERROR flag and the output voltage. In this example, the input voltage is changed to demonstrate the functionality of the Error Flag. The internal Error flag comparator has an open drain output stage. Hence, the ERROR pin should be pulled high through a pull up resistor. Although the ERROR flag pin can sink current of 1mA, this current is energy drain from the input supply. Hence, the value of the pull up resistor should be in the range of 10kΩ to 1MΩ. The ERROR pin must be connected to ground if this function is not used. It should also be noted that when the shutdown pin is pulled low, the ERROR pin is forced to be invalid for reasons of saving power in shutdown mode. 10 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3871 LP3874 LP3871 LP3874 www.ti.com SNVS225G – FEBRUARY 2003 – REVISED APRIL 2013 Figure 19. Error Flag Operation SENSE PIN In applications where the regulator output is not very close to the load, LP3874 can provide better remote load regulation using the SENSE pin. Figure 20 depicts the advantage of the SENSE option. LP3871 regulates the voltage at the output pin. Hence, the voltage at the remote load will be the regulator output voltage minus the drop across the trace resistance. For example, in the case of a 3.3V output, if the trace resistance is 100mΩ, the voltage at the remote load will be 3.22V with 0.8A of load current, ILOAD. The LP3874 regulates the voltage at the sense pin. Connecting the sense pin to the remote load will provide regulation at the remote load, as shown in Figure 20. If the sense option pin is not required, the sense pin must be connected to the VOUT pin. Figure 20. Improving remote load regulation using LP3874 SHUTDOWN OPERATION A CMOS Logic level signal at the shutdown ( SD) pin will turn-off the regulator. Pin SD must be actively terminated through a 10kΩ pull-up resistor for a proper operation. If this pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin if not used. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3871 LP3874 11 LP3871 LP3874 SNVS225G – FEBRUARY 2003 – REVISED APRIL 2013 www.ti.com DROPOUT VOLTAGE The dropout voltage of a regulator is defined as the minimum input-to-output differential required to stay within 2% of the nominal output voltage. For CMOS LDOs, the dropout voltage is the product of the load current and the Rds(on) of the internal MOSFET. REVERSE CURRENT PATH The internal MOSFET in LP3871 and LP3874 has an inherent parasitic diode. During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is pulled above the input in an application, then current flows from the output to the input as the parasitic diode gets forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to 200mA continuous and 1A peak. POWER DISSIPATION/HEATSINKING LP3871 and LP3874 can deliver a continuous current of 0.8A over the full operating temperature range. A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. The total power dissipation of the device is given by: PD = (VIN−VOUT)IOUT+ (VIN)IGND where IGND is the operating ground current of the device (specified under Electrical Characteristics). The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the application, and the maximum allowable junction temperature (TJmax): TRmax = TJmax− TAmax The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the formula: θJA = TRmax / PD LP3871 and LP3874 are available in TO-220 and DDPAK/TO-263 packages. The thermal resistance depends on amount of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥ 60 °C/W for TO-220 package and ≥ 60 °C/W for DDPAK/TO-263 package no heatsink is needed since the package can dissipate enough heat to satisfy these requirements. If the value for allowable θJA falls below these limits, a heat sink is required. HEATSINKING TO-220 PACKAGE The thermal resistance of a TO-220 package can be reduced by attaching it to a heat sink or a copper plane on a PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for DDPAK/TO-263 package. The heatsink to be used in the application should have a heatsink to ambient thermal resistance, θHA≤ θJA − θCH − θJC. In this equation, θCH is the thermal resistance from the case to the surface of the heat sink and θJC is the thermal resistance from the junction to the surface of the case. θJC is about 3°C/W for a TO-220 package. The value for θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. If the exact value is unknown, 2°C/W can be assumed. HEATSINKING DDPAK/TO-263 PACKAGE The DDPAK/TO-263 package uses the copper plane on the PCB as a heatsink. The tab of these packages are soldered to the copper plane for heat sinking. Figure 21 shows a curve for the θJA of DDPAK/TO-263 package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat sinking. 12 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3871 LP3874 LP3871 LP3874 www.ti.com SNVS225G – FEBRUARY 2003 – REVISED APRIL 2013 Figure 21. θJA vs Copper (1 Ounce) Area for DDPAK/TO-263 package As shown in the figure, increasing the copper area beyond 1 square inch produces very little improvement. The minimum value for θJA for the DDPAK/TO-263 package mounted to a PCB is 32°C/W. Figure 22 shows the maximum allowable power dissipation for DDPAK/TO-263 packages for different ambient temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C. Figure 22. Maximum power dissipation vs ambient temperature for DDPAK/TO-263 package HEATSINKING SOT-223 PACKAGE Figure 23 shows a curve for the θJA of SOT-223 package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat sinking. Figure 23. θJA vs Copper(1 Ounce) Area for SOT-223 package The following figures show different layout scenarios for SOT-223 package. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3871 LP3874 13 LP3871 LP3874 SNVS225G – FEBRUARY 2003 – REVISED APRIL 2013 www.ti.com Figure 24. SCENARIO A, θJA = 148°C/W Figure 25. SCENARIO B, θJA = 125°C/W 14 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3871 LP3874 LP3871 LP3874 www.ti.com SNVS225G – FEBRUARY 2003 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision F (April 2013) to Revision G • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 13 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3871 LP3874 15 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP3871EMP-1.8/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LH6B LP3871EMP-2.5/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LH7B LP3871EMP-3.3/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LH8B LP3871EMP-5.0/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LH9B LP3871EMPX-2.5/NOPB ACTIVE SOT-223 NDC 5 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LH7B LP3871EMPX-3.3/NOPB ACTIVE SOT-223 NDC 5 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LH8B LP3871ES-1.8/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3871ES -1.8 LP3871ES-2.5/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3871ES -2.5 LP3871ES-3.3/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3871ES -3.3 LP3871ESX-1.8/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3871ES -1.8 LP3871ESX-2.5/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3871ES -2.5 LP3871ESX-3.3/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3871ES -3.3 LP3874EMP-1.8/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LHEB LP3874EMP-2.5/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LHFB LP3874EMP-3.3 NRND SOT-223 NDC 5 1000 TBD Call TI Call TI -40 to 125 LHHB LP3874EMP-3.3/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LHHB LP3874EMP-5.0/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LHJB Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 1-Nov-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP3874EMPX-1.8/NOPB ACTIVE SOT-223 NDC 5 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LHEB LP3874EMPX-2.5/NOPB ACTIVE SOT-223 NDC 5 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LHFB LP3874EMPX-3.3/NOPB ACTIVE SOT-223 NDC 5 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LHHB LP3874EMPX-5.0/NOPB ACTIVE SOT-223 NDC 5 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LHJB LP3874ES-2.5 NRND DDPAK/ TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3874ES -2.5 LP3874ES-2.5/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3874ES -2.5 LP3874ES-3.3 NRND DDPAK/ TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3874ES -3.3 LP3874ES-3.3/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3874ES -3.3 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP3871EMP-1.8/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3871EMP-2.5/NOPB SOT-223 NDC 5 1000 330.0 LP3871EMP-3.3/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 16.4 7.0 7.5 2.2 12.0 16.0 LP3871EMP-5.0/NOPB SOT-223 NDC 5 1000 Q3 330.0 16.4 7.0 7.5 2.2 12.0 16.0 LP3871EMPX-2.5/NOPB SOT-223 NDC 5 Q3 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3871EMPX-3.3/NOPB SOT-223 NDC 5 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3871ESX-1.8/NOPB DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 LP3871ESX-2.5/NOPB DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 LP3871ESX-3.3/NOPB DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 LP3874EMP-1.8/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3874EMP-2.5/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3874EMP-3.3 SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3874EMP-3.3/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3874EMP-5.0/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3874EMPX-1.8/NOPB SOT-223 NDC 5 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3874EMPX-2.5/NOPB SOT-223 NDC 5 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP3874EMPX-3.3/NOPB SOT-223 NDC 5 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3874EMPX-5.0/NOPB SOT-223 NDC 5 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3871EMP-1.8/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3871EMP-2.5/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3871EMP-3.3/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3871EMP-5.0/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3871EMPX-2.5/NOPB SOT-223 NDC 5 2000 367.0 367.0 35.0 LP3871EMPX-3.3/NOPB SOT-223 NDC 5 2000 367.0 367.0 35.0 LP3871ESX-1.8/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP3871ESX-2.5/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP3871ESX-3.3/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP3874EMP-1.8/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3874EMP-2.5/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3874EMP-3.3 SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3874EMP-3.3/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3874EMP-5.0/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3874EMPX-1.8/NOPB SOT-223 NDC 5 2000 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3874EMPX-2.5/NOPB SOT-223 NDC 5 2000 367.0 367.0 35.0 LP3874EMPX-3.3/NOPB SOT-223 NDC 5 2000 367.0 367.0 35.0 LP3874EMPX-5.0/NOPB SOT-223 NDC 5 2000 367.0 367.0 35.0 Pack Materials-Page 3 MECHANICAL DATA NDC0005A www.ti.com MECHANICAL DATA KTT0005B TS5B (Rev D) BOTTOM SIDE OF PACKAGE www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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