LP3891 www.ti.com SNVS235D – SEPTEMBER 2003 – REVISED APRIL 2013 LP3891 0.8A Fast-Response Ultra Low Dropout Linear Regulators Check for Samples: LP3891 FEATURES DESCRIPTION • • • • • • The LP3891 is a high current, fast response regulator which can maintain output voltage regulation with minimum input to output voltage drop. Fabricated on a CMOS process, the device operates from two input voltages: Vbias provides voltage to drive the gate of the N-MOS power transistor, while Vin is the input voltage which supplies power to the load. The use of an external bias rail allows the part to operate from ultra low Vin voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an N-MOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability. 1 2 • • Ultra Low Dropout Voltage (100mV at 0.8A typ) Low Ground Pin Current Load Regulation of 0.04%/A 60 nA Typical Quiescent Current in Shutdown 1.5% Output Accuracy (25°C) TO-220, DDPAK/TO-263 and SO PowerPAD-8 Packages Over Temperature/Over Current Protection −40°C to +125°C Junction Temperature Range APPLICATIONS • • • • • • • DSP Power Supplies Server Core and I/O Supplies PC Add-in-Cards Local Regulators in Set-Top Boxes Microcontroller Power Supplies High Efficiency Power Supplies SMPS Post-Regulators The fast transient response of these devices makes them suitable for use in powering DSP, Microcontroller Core voltages and Switch Mode Power Supply post regulators. The parts are available in TO-220, DDPAK/TO-263 and SO PowerPAD-8 packages. Dropout Voltage: 100 mV (typ) at 0.8A load current. Ground Pin Current: 3 mA (typ) at full load. Shutdown Current: 60 nA (typ) when S/D pin is low. Precision Output Voltage: 1.5% room temperature accuracy. TYPICAL APPLICATION CIRCUIT At least 10 µF of input and output capacitance is required for stability. *Tantalum capacitors are recommended. Aluminum electrolytic capacitors may be used for restricted temperature range. See application hints. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2013, Texas Instruments Incorporated LP3891 SNVS235D – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. CONNECTION DIAGRAM Figure 1. TO-220, Top View Figure 2. DDPAK/TO-263, Top View VOUT 1 VOUT 2 VBIAS 3 GND 4 GND 8 N/C 7 VIN 6 S/D 5 GND Figure 3. SO PowerPAD-8, Top View white space white space white space white space BLOCK DIAGRAM 2 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3891 LP3891 www.ti.com SNVS235D – SEPTEMBER 2003 – REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS (1) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and specifications. VALUE / UNITS −65°C to +150°C Storage Temperature Range Lead Temp. (Soldering, 5 seconds) 260°C ESD Rating Human Body Model Machine Model (3) 2 kV 200V Power Dissipation (2) (4) Internally Limited VIN Supply Voltage (Survival) −0.3V to +6V VBIAS Supply Voltage (Survival) −0.3V to +7V −0.3V to +7V Shutdown Input Voltage (Survival) IOUT (Survival) Internally Limited −0.3V to +6V Output Voltage (Survival) −40°C to +150°C Junction Temperature (1) (2) (3) (4) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For specifications, see Electrical Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions. The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin. The machine model is a 220 pF capacitor discharged directly into each pin. The machine model ESD rating of pin 5 is 100V. At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values. θJ-A for TO-220 devices is 65°C/W if no heatsink is used. If the TO-220 device is attached to a heatsink, a θJ-S value of 4°C/W can be assumed. θJ-A for TO-263 devices is approximately 40°C/W if soldered down to a copper plane which is at least 1.5 square inches in area. θJ-A value for typical SO PowerPAD-8 PC board mounting is 166°C/W. If power dissipation causes the junction temperature to exceed specified limits, the device will go into thermal shutdown. RECOMMENDED OPERATING CONDITIONS VALUE / UNITS VIN (VOUT + VDO) to 5.5V Shutdown 0 to +6V IOUT 0.8A −40°C to +125°C Junction Temperature VBIAS 4.5V to 6V Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3891 3 LP3891 SNVS235D – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA, CIN = COUT = 10 µF, VS/D = VBIAS. Symbol VO Parameter Conditions 10 mA ≤ IL ≤ 0.8A, VO(NOM) + 1V ≤ VIN ≤ 5.5V, 4.5V ≤ VBIAS ≤ 6V Output Voltage Tolerance (3) ΔVO/ΔVIN Output Voltage Line Regulation ΔVO/ΔIL Output Voltage Load Regulation (4) VDO (5) Dropout Voltage IQ(VIN) MIN (6) Quiescent Current Drawn from VIN Supply (1) 1.198 1.186 ISC Quiescent Current Drawn from VBIAS Supply Short-Circuit Current (2) MAX (1) 1.216 1.234 1.246 1.478 1.455 1.5 1.522 1.545 1.773 1.746 1.8 1.827 1.854 Units V VO(NOM) + 1V ≤ VIN ≤ 5.5V 0.01 %/V 10 mA ≤ IL ≤ 0.8A 0.04 0.06 %/A IL = 0.8A (TO220 and TO263 only) 100 300 400 IL = 0.8A (SO PowerPAD only) 115 320 430 3 7 8 mA 0.03 1 30 µA 1 2 3 mA VS/D ≤ 0.3V 0.03 1 30 µA VOUT = 0V 2.5 10 mA ≤ IL ≤ 0.8A VS/D ≤ 0.3V IQ(VBIAS) Typical 10 mA ≤ IL ≤ 0.8A mV A Shutdown Input VSDT Output Turn-off Threshold Output = ON 1.3 0.7 Output = OFF 0.7 Td (OFF) Turn-OFF Delay RLOAD X COUT << Td (OFF) 20 Td (ON) Turn-ON Delay RLOAD X COUT << Td (ON) 15 IS/D S/D Input Current VS/D =1.3V 1 VS/D ≤ 0.3V −1 Ripple Rejection for VIN Input Voltage VIN = VOUT +1V, f = 120 Hz 80 VIN = VOUT + 1V, f = 1 kHz 65 Ripple Rejection for VBIAS Voltage VBIAS = VOUT + 3V, f = 120 Hz 70 VBIAS = VOUT + 3V, f = 1 kHz 65 0.3 V µs µA AC Parameters PSRR (VIN) PSRR (VBIAS) en (1) (2) (3) (4) (5) (6) 4 Output Noise Density f = 120 Hz Output Noise Voltage BW = 10 Hz − 100 kHz, VOUT = 1.8V 150 BW = 300 Hz − 300 kHz, VOUT = 1.8V 90 1 dB µV/root− Hz µV (rms) Limits are specified through testing, statistical correlation, or design. Typical numbers represent the most likely parametric norm for 25°C operation. Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage. If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground. Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load. Dropout voltage is defined as the minimum input to output differential required to maintain the output with 2% of nominal value. The SO PowerPAD-8 package devices have a slightly higher dropout voltage due to increased band wire resistance. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3891 LP3891 www.ti.com SNVS235D – SEPTEMBER 2003 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified: TJ = 25°C, COUT = 10 µF, Cin = 10µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V IGND vs VSD VOUT vs Temperature Figure 4. Figure 5. DC Load Regulation Line Regulation vs VIN Figure 6. Figure 7. Line Regulation vs VBIAS IBIAS vs IL 1.20 IBIAS (mA) 125oC 1.10 VBIAS = 5V _ VIN = 2.3V 25oC 1.00 -40oC 0.90 _ 0.80 0 0.2 _ 0.4 _ 0.6 _ 0.8 ILOAD (A) Figure 9. Figure 8. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3891 5 LP3891 SNVS235D – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, COUT = 10 µF, Cin = 10µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V 6 IGND vs VSD Noise Measurement Figure 10. Figure 11. VOUTStartup Waveform Line Regulation vs VBIAS Figure 12. Figure 13. Line Regulation vs VBIAS VIN PSRR Figure 14. Figure 15. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3891 LP3891 www.ti.com SNVS235D – SEPTEMBER 2003 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, COUT = 10 µF, Cin = 10µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V VIN PSRR VBIAS PSRR Figure 16. Figure 17. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3891 7 LP3891 SNVS235D – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com Application Hints EXTERNAL CAPACITORS To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit. OUTPUT CAPACITOR At least 10µF of output capacitance is required for stability (the amount of capacitance can be increased without limit). The output capacitor must be located less than 1cm from the output pin of the IC and returned to a clean analog ground. The ESR (equivalent series resistance) of the output capacitor must be within the "stable" range as shown in the graph below over the full operating temperature range for stable operation. 10 COUT ESR (:) 1.0 COUT > 10 PF STABLE REGION 0.1 .01 .001 0 0.2 0.4 0.6 0.8 LOAD CURRENT (A) Figure 18. Minimum ESR vs Output Load Current Tantalum capacitors are recommended for the output as their ESR is ideally suited to the part's requirements and the ESR is very stable over temperature. Aluminum electrolytics are not recommended because their ESR increases very rapidly at temperatures below 10°C. Aluminum caps can only be used in applications where lower temperature operation is not required. A second problem with Al caps is that many have ESR's which are only specified at low frequencies. The typical loop bandwidth of a linear regulator is a few hundred kHz to several MHz. If an Al cap is used for the output cap, it must be one whose ESR is specified at a frequency of 100 kHz or more. Because the ESR of ceramic capacitors is only a few milli Ohms, they are not suitable for use as output capacitors on LP389X devices. The regulator output can tolerate ceramic capacitance totaling up to 15% of the amount of Tantalum capacitance connected from the output to ground. INPUT CAPACITOR The input capacitor must be at least 10 µF, but can be increased without limit. It's purpose is to provide a low source impedance for the regulator input. Ceramic capacitors work best for this, but Tantalums are also very good. There is no ESR limitation on the input capacitor (the lower, the better). Aluminum electrolytics can be used, but their ESR increase very quickly at cold temperatures. They are not recommended for any application where temperatures go below about 10°C. BIAS CAPACITOR The 0.1µF capacitor on the bias line can be any good quality capacitor (ceramic is recommended). BIAS VOLTAGE The bias voltage is an external voltage rail required to get gate drive for the N-FET pass transistor. Bias voltage must be in the range of 4.5 - 6V to assure proper operation of the part. UNDER VOLTAGE LOCKOUT The bias voltage is monitored by a circuit which prevents the regulator output from turning on if the bias voltage is below approximately 4V. 8 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3891 LP3891 www.ti.com SNVS235D – SEPTEMBER 2003 – REVISED APRIL 2013 SHUTDOWN OPERATION Pulling down the shutdown (S/D) pin will turn-off the regulator. Pin S/D must be actively terminated through a pull-up resistor (10 kΩ to 100 kΩ) for a proper operation. If this pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin if not used. POWER DISSIPATION/HEATSINKING A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. The total power dissipation of the device is given by: PD = (VIN−VOUT)IOUT+ (VIN)IGND (1) where IGND is the operating ground current of the device. The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the application, and the maximum allowable junction temperature (TJmax): TRmax = TJmax− TAmax (2) The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the formula: θJA = TRmax / PD (3) These parts are available in TO-220 and DDPAK/TO-263 packages. The thermal resistance depends on amount of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥ 60 °C/W for TO-220 package and ≥ 60 °C/W for DDPAK/TO-263 package no heatsink is needed since the package can dissipate enough heat to satisfy these requirements. If the value for allowable θJA falls below these limits, a heat sink is required. HEATSINKING TO-220 PACKAGE The thermal resistance of a TO-220 package can be reduced by attaching it to a heat sink or a copper plane on a PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for DDPAK/TO-263 package. The heatsink to be used in the application should have a heatsink to ambient thermal resistance, θHA≤ θJA − θCH − θJC. (4) In this equation, θCH is the thermal resistance from the case to the surface of the heat sink and θJC is the thermal resistance from the junction to the surface of the case. θJC is about 3°C/W for a TO220 package. The value for θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. If the exact value is unknown, 2°C/W can be assumed. HEATSINKING DDPAK/TO-263 PACKAGE The DDPAK/TO-263 package uses the copper plane on the PCB as a heatsink. The tab of these packages are soldered to the copper plane for heat sinking. Figure 19 shows a curve for the θJA of DDPAK/TO-263 package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat sinking. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3891 9 LP3891 SNVS235D – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com Figure 19. θJA vs Copper (1 Ounce) Area for DDPAK/TO-263 Package As shown in Figure 20, increasing the copper area beyond 1 square inch produces very little improvement. The minimum value for θJA for the DDPAK/TO-263 package mounted to a PCB is 32°C/W. Figure 20 shows the maximum allowable power dissipation for DDPAK/TO-263 packages for different ambient temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C. Figure 20. Maximum Power Dissipation vs Ambient Temperature for DDPAK/TO-263 Package HEATSINKING SO PowerPAD PACKAGE Heatsinking for the SO PowerPAD-8 package is accomplished by allowing heat to flow through the ground slug on the bottom of the package into the copper on the PC board. The heat slug must be soldered down to a copper plane to get good heat transfer. It can also be connected through vias to internal copper planes. Since the heat slug is at ground potential, traces must not be routed under it which are not at ground potential. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. Figure 21 shows a curve for the θJA of the SO PowerPAD package for different copper area sizes using a typical PCB with one ounce copper in still air. 10 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3891 LP3891 www.ti.com SNVS235D – SEPTEMBER 2003 – REVISED APRIL 2013 QJA (oC/W) 180 130 80 30 0 0.5 1 1.5 COPPER AREA (sq. in.) Figure 21. θJA vs Copper (1 ounce) Area for SO PowerPAD Package Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3891 11 LP3891 SNVS235D – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision C (April 2013) to Revision D • 12 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 11 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3891 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) LP3891EMR-1.2 NRND Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SO PowerPAD DDA 8 95 TBD Call TI Call TI -40 to 125 3891E MR1.2 LP3891EMR-1.2/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS & no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 125 3891E MR1.2 LP3891EMR-1.8/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS & no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 125 3891E MR1.8 LP3891EMRX-1.2/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS & no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 125 3891E MR1.2 LP3891ES-1.2 NRND DDPAK/ TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3891ES -1.2 LP3891ES-1.2/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3891ES -1.2 LP3891ES-1.5/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3891ES -1.5 LP3891ESX-1.2/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3891ES -1.2 LP3891ESX-1.5/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3891ES -1.5 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP3891EMRX-1.2/NOPB SO Power PAD DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP3891ESX-1.2/NOPB DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 LP3891ESX-1.5/NOPB DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3891EMRX-1.2/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0 LP3891ESX-1.2/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP3891ESX-1.5/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA DDA0008B MRA08B (Rev B) www.ti.com MECHANICAL DATA KTT0005B TS5B (Rev D) BOTTOM SIDE OF PACKAGE www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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