SHARP LH1684F

SHARP
L08 8 1 32
Aug. 29. 1996
[ SPEC No. 1 E
ISSUE:
1
SPECIFICATIONS
Product
Type
Model
No.
5 V Drive 240 Outputs
TFT-LCD Source Driver’
LH1684F
Kl’his specifications
contains 34 pages including
the cover and appendix.
If you have any objections,please
contact us before issuing purchasing order.
CUSTOMERS
ACCEPTANCE
DATE:
BY:-
PRESENTED
Y. SHIOTAw
Dept. General
Manager
REVIEWED
BY:
PREPARED
BY:
,_ ---. - ._
ENGINEERING
DEPARTMENT
! ..--
;*
- -___.
LOGIC IC ENGINEERING CENTER
TENRIINTEGRATED
CIRCUITS(I0 GRQUP7'::
SHARP CORPORATION
‘-;
--._
.
,
-.”
SHARP
LH1684F
GHandIe this document carefully for it contains material protected by international copyright law.
Any reproduction , full or in part , of this material is prohibited without the express written
permission of the company.
OWhen using the produc?s covered herein , please observe the conditions written herein and the
precautions outlined in the following paragraphs. In no event shall the company be iiable for
any damages resulting from failure to strictly adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application
areas. When using the products covered herein for the equipment listed in Paragraph
(2) , even for the following application areas , be sure to observe the precautions given
in Paragraph (2) . Never use the products for the equipment listed in Paragraph (3) .
* Office electronics
- Instrumentation and measuring equipment
* Machine tools
* Audiovisual equipment
* Home appliances
* Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment which
demands high reliability, should first contact a sales representative of the company and
then accept responsibility for incorporating into the design fail-safe operation , redundancy
, and other appropriate measures for ensuring reliability and safety of the equipment and
the overall system.
* Control and safety devices for airplanes , trains , automobiles, and other
transportation equipment
- Mainframe computers
- Traffic control systems
- Gas leak detectors and automatic cutoff devices
* Rescue and security equipment
- Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands
extremely high performance in terms of functionality , reliability , or accuracy.
- Aerospace equipment
+ Communications equipment for trunk lines
* Control equipment for the nuclear power industry
- Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation
Paragraphs to a sales representative
of the company.
of the above three
OPlease direct all queries regarding the products covered herein to a sales representative
company.
of the
SHARP
LH1684F
Contents
1.
Summary . . .. . . . . .. . .. . . . . .. . . . . .._.....................................................................
2
2.
Features
3.
Pin Configuration
4.
Block Diagram . .. . . . .. . . .. .._.__..___.....___._.._..._........_.......................................
3
5.
Description of Pins .................................................................................
5.1
Designation of pins .......................................................................
5.2
Input/output circuit types ...............................................................
4
4
5
6.
Description of Functions and Operations ..................................................
6.1
Functions of pin ............................................................................
6.2
Operation of function ....................................................................
6.3
Outline of operation timing ...........................................................
Timing chart for normal sampling operation ....................................
6.4
6.5
Timing chart for 3-point simultaneous sampling operation.. ............
6.6
Precautions.. ..............................................................................
7.
Absolute Maximum Ratings . . . . .. .. . . .. . . . . . . . .. . . . .. . . . . . .. . . .. . . .. . . .. . . . .. . . .. . . . . . .. . . . .. . 21
8.
Recommended
9.
Electrical Characteristics ........................................................................
9.1
DC characteristics ........................................................................
9.2
AC characteristics .......................................................................
9.3
Timing diagram ...........................................................................
.. . . .. . . . .. . . .. . . .. . . . . . .. . . . . .. . . . . .. . . . . . . .. . . . . .. . . . .. .. . .. . .. . . . .. . . .. . . .. .. . . .. . . . . . .. . . .. . 2
.. . . ..._........................_............................................_.....
Operating Conditions
2
6
6
7
11
12
16
20
. . . . . .. . . . . .. . . . . .. .. .. . .. . . .. . . . .. . . . .. . . . . . .. . . . . 21
21
21
.22
.23
10.
Example of System Configuration
. .. . . . . . . .. . . . . .. . . . . . .. . . .. . .. . . .. . . . .. . . . .. . . . . .. . . . . .. . 24
1 1..
Example of Typical Characteristics
.. . . . . . .. .. . . . . .. . . . . .. . . .. . .. . . .. . . . . .. . . . .. . . . . .. . . . . .. 25
12.
Package and Packing Specification
. . . .. .. . . . . .. . . . . .. . . . .. . . .. . .. . . . .. . . . .. . . . . .. . . . .. . . . 26
SHARP
2
LH1684F
1.
Summary
The LH1684F is a source driverforthe TFT liquid crystal panel used for LCD unit such as aTV set
and has 240 LCD drive outputs.
The LH1684F samples and holds three video signalsof R, G, and B by the sample and hold circuits
at the synchronized with the clock CK , and output simultaneously the output voltage from all
output pins.
2.
Features
. No. of LCD drive outputs :
. Supply voltage :
* Output amplitude voltage :
+Sampling frequency :
+Video signals sampling :
240 outputs
4.5to5.5v
4.0 VP-P (at 5.0 V supply voltage)
2 0 MHz (MAX)
Shift direction can be selected.
(OS 1 -
OS240 or OS240 -
OS 1)
* Sampling timing :
Normalsampling operation and 3-point simultaneous sampling
operation can be selected.
Compatible to stripe pixel array panels and delta pixel array panels
* Video signal setting :
by mode setting circuit.
Max. 4 cascades (Internal counting system)
. Cascade connection :
* Package:
263 pinsTCP (Tape Carrier Package)
CMOS silicon gate (p-type silicon substrate)
* Process configuration :
- Not designed or rated as radiation hardened.
3
Pin
Configuration
5 Dummy
Pi0
(Does
not
prescribeTCP
outline)
$j?5Dummy
pins
;5 _-.-----__----__--_-____________________--------------------------------- s:
On
Notes: 1. This TCP has 14 dummy pins which are not electrically connected.
2. The above pin configuration shows the pins asseen from the TCP surface.
SHARP
LH 1684F
4.
Block
3
1
Diagram
Numerals in circles indicate the pin number.
Bkdirectional
RL
CSl
cs2
TST
TSTl
TST2
TST3
shift
Control
logic
............................
6, --_-_-_-____------_-vcc
Block name
Control logic
Bi-directional
shift register
Sampling signal creation circuit
Mode setting circuit
Sample and hold circuit
Output circuit
GND
OS1 . .. .. .. .. .. .. .. . .. .. . .. .. . OS240
I
Block function
i
I Used to create signals necessary for controlling cascade sequence
’ and for discharge signal and sampling signals creation circuits, etc.
~Used as transfer circuit of video sampling start signals.
’ It is possible to set the direction of sampling start signals sequence
/ by setting the FVL pin, from OS1 to OS240 or from OS240 to OS1 .
Used to create the sampling signals corresponding
j pin based on the sampling start signals transferred
i directional shift register.
to each output
by the bi-
/ Used to set the form of the video signals to be sent to the sample
1and hold circuits.
Used to sample the video signals input from the mode setting circuit I
I
: at the timing of the sampling signals and hold the sampling datas
I until the next sampling operation.
i The circuit comprises an operational amplifier and an output buffer
1and outputs the voltage corresponding to the data held in the
/ sample and hold circuit.
i
I
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LH 1684F
5.
Description
5.1 Designation
of pins
Pin No.
I
1 to 240
/ OS1 to OS240
Pinsymbol
0
LCD drive output pins
TSTl
/
I
LSI test pin
242
j
TST2
/
I
LSI test pin
243
(
TST3
j
I
LSI test pin
TST4
~
I
LSI test pin
244
j Remarks
I
Designation
/ I/O
j
241
1
of Pins
I
i
245,263
’
vcc
/ -
Power supply pins
246,262
247
1
1
GND
i / I
GNDpins
Horizontal scanning start pulse input pin
j
I
Horizontal shift clock input pin
Analog circuit operation selecting pin
248
’
SP
CK
249
~
CTR
/
I
250
/
TST
j
I
LSI test pin
I
I
I
I
.
I
I
SAM
!
I
Sampling mode selecting pin
252
RL
:
I
Sampling sequence
selecting pin
253
CSl
I
I
Cascade sequence
setting pin 1
I
Cascade sequence setting pin 2
,
Bias voltage setting pin for output operational amplifiers ’
/
Bias voltage setting pin for output buffers
251
:
’
’
cs2
~
Vbl
1
I
I
Vb2
MODE
1
I
I
Video signals form setting pin
258
TST5
j
I
LSI test pin
259
VA
I
Video signal input pin
254
255
256
257
I
//
/
!
I
/
1
I
260
:
VB
/
I
Video signal input pin
I
261
i
vc
I
I
Video signal input pin
I
SHARP
’ “‘684F
l-1
5.2
input/output
(1)
circuit
I
IL-
.
types
Input pin 1 (SP, CK, CTR, RL, SAM, CSl, CS2, MODE, TST, TSTl, TST2, TSTS, TST4, and
TST5 pins)
Note that SP, CK, CTP, and MODE pins do not have pull-up functions.
TheTST.5 pin has the pull-down function.
Internal logic
Input pin
Input buffer
(2) Input pin 2 (VA, VB, VC, Vbl , and Vb2 pins)
Input pin BBp
fnternal logic
(3) Output pin (OS1 to OS240 pins)
vcc
Sample and
hold circuits
--,:I:-Operational ampwer
tput buffer
t
7k
4
Outpu pin
SHARP
Description
1 Functions
of Functions
and Operations
of pin
Pin symbol
vcc
GND
TST
TSTl to TST4
TST5
SP
CK
CTR
SAM
Pin functions
Used as power supply pin, which is normally connected to +5.6 V.
/ Used as GND pin, which is connected to OV.
: Used as pin for LSI testing. Must be connected to VCC.
I Used as pins for LSI testing. Must be connected to VCC.
: Used as pin for LSI testing. Must be connected to GND.
j Used as input pin of horizontal scanning start pulse.
j Used as input pin of horizontal shift clock.
/ Video signals are sampled in order at rise timing and fall timinglof CK.
i Used as input pin of selecting video signals sampling circuits and selecting input
/ signals of output operational amplifiers.
Used as input pin for setting the selecting of normal sampling operation
j simultaneous sampling operation.
or S-point
i For normal sampling operation, video signals are sampled in order 7 LCD drive output.
For 3-point simultaneous sampling operation, video signals are sampled in order
I simultaneously 3 LCD drive outputs.
i-
RL
CSl, cs2
j For either operation, sampling signals are shifted at every rise timing and fall timing of
j horfzontal shift clock of CK pin (half cfock) , and their sampling perfod is equal to the
period of one clock.
Used as input pin for setting the shift direction of video signals sampling sequence.
~Video signals are sampled in the order of from OS1 to OS240 when set to “H” and in tht
order of from OS.240 to OS1 when set to “L”.
1Used as input pins for setting of chip cascade sequence.
/ Set chip cascade sequence as shown in the table below.
’ Cascadesequence
I
3rd
Vbl
Vb2
VA, VB, VC
OS1 to OS240
cs1
I
H
L
I
!
H
H
H
;
L
1st
2nd
MODE
’
I
cs2
4th
/
L
j
L
I
; For details, refer to “6-2. Operation of function” on page 7.
’ Used as input pin for setting form of video signals for sampling.
/ By mode setting circuit, video signals are sampled and output with respect to OS1 to
i OS246 in the order of VB, VA, and VC when set to “H” and in the order of VC, VB, and
VA when set to ‘IL”.
/ For details, refer to “6-2. Operation of function” on page 7.
1 Do not use this function in “OPEN” condition.
r Used as pin for setting the bias voltage of operational amplifiers in output circuits.
i Used as pin for setting bias voltage of buffers in output circuits.
Used as input pins of video signals.
/ VB, VA, VC, ._. VB. VA, VC or VC, VB, VA. . .. VC, VB, VA are input with respect to LCD
; drive outputs OSl, OS2,OS3. ... 08238,05239,OS240
by MODE pin setting
1condition.
j Used as LCD drive output pins.
i All output pins discharge simultaneously at the timing of internal discharge
signal
and
; after discharge is completed, they output voltage corresponding to sampled video
: signals.
-.
SHARP
7
LH1684F
6.2
Operation
of function
(1) Examples of
cascadesequence
When RL=“H”
Horizontal
Cascade
scanning
direction
Cascade
e
Cascade
Cascade
I
I
TFT-LCD panel c‘,
When RL=“L”
Horizontal
scanning
direction
e
TFT-LCD panel =>
I
CSl=‘H’
CSP=‘H’
II
--I
Cascade
sequence
CSl=‘L
CSP=‘H’
Cascade
sequence
Cascade
sequence2nd
1st
CSl=‘H’
CSL=‘L
II
3rd
Cascade
sequence
4th
(2) Video signal mode setting function
With MODE pin condition, it is possible to set the fon of video signals corresponding to each
output pins by selecting the mode setting circuit.
When
MODE=“H”
j..
I
OS
1
OS
2
OS
3
I
I
I
OS
4
OS
5
OS
6
Output
circuit
When MODE=‘L”
Mode setting circuit
Output
ciicuits
LH 1684F
(3)
8
Output circuit type
The LH1684F samples video signals by the sample and hold circuits of 2 systems and outputs
the voltage corresponding
to the sampled data by the input switching operational amplifiers.
Sample and hold circuits and output circuits are as shown in the diagram below.
When CTR=“H”, the LH1684F samples the data to system A of the sample and hold circuits
and outputs the voltage corresponding
to the voltage sampled by capacitor B of system B.
When CTR=“L”, the LH1684F samples the data to system B of the sample and hold circuits
and outputs the voltage corresponding to the voltage sampled by capacitor A of system A.
System A of sample
r---------------------------------.
and hold circuits
.1
L_____________---__________________
System B of sampie and hold circuits
Therefore, it is necessary
to repeat
sampling
operation
and output operation by exchanging
CTR signal to “H” and “L” for every SP signal, usually.
When CTFI signal is set to “H” or “L” several times for SP signal, the same voltage is output
continuously during such period.
The output voltage corresponds to the data sampled by the previous sampling operation.
Timing of operation is as follows.
SP
CTR
I
4
System
A
Sampling
System
B
output
--A
1
0
output
Sampling
4
Sampling
1
2
output
2
3
Sampling
output
3’
2
output
Sampling
3’
4
SHARP
LH1684F
(4)
Examples of LCD panel connection
With the video signal mode setting function of (2) it is possible to connect LCD panel to the
stripe pixel array panel and delta pixel array panel as shown in the following examples.
(a) Example of stripe pixel array panel connection
Video signals
p
7
f
‘1st line
Sampling
data
2nd line m::;:-;;::
R G
1; 1d 1; 1Ii /
B
R
I 1 I
3rd line ~:]::-::::
R G B
I
I i I i
R
IB IR IG /B 1
I
I I I I
I
Connection
I
I
MODE=“H”
MODE=“H”
of video signal input pins
Videosignal
input pin
Video signal
; VA / VB 1 VC
‘G/RIB
Setting of video signals sampled by output circuits and MODE pin condition
1
/ After 4th line
lstline
I
2nd line
1 3rd line
OS(3n+l)
j
R
/
R
j
R
;
R
I
I
/
OS (3n+2)
G
G
I
G
G
I
/
B
OS (3n+3)
B
i
B
B
j
;.
U,,”
1
“,,”
;
MODE pin setting
“H”
!
“H”
(n=O, 1,2,. . . ,79)
SHARP
LH 1684F
(b) Examples of delta pixel array panel connection
VC
VA VB
LH1684F
f
Sampling
data
0
s
0
s
.....................................
1
2
3
___--_--_
0
s
0
s
0
s
238 239 240
MODE=“H”
1st line
b b IG b 1
2nd line
(
0
s
+&.$I
MOD E=“L”
___---L$g&&
3rd fine
MOD E=“H”
Connection of video signal input pins
Videosignal input pin ’ VA j VB ’ VC /
G’R,B;
Video signal
Setting of video signals sampled by output circuits and MODE pin condition
1
OS(3n+l)
OS(3n+2)
OS(3n+3)
!
/
/
MODE pin setting ’
lstline
2nd line
/
3rd line
I
After4th line
R
B
;
R
G
B
“HO,
R
;
!
;
G
/
/
B and Rare alternately selected.
R and G are alternately selected.
i
j
G
“L”
B
a,,”
/ G and B are alternately selected.
[ ‘L” and “H” are alternately selected. !
(n=O, 1,2,. . . ,79)
Note 1.
Note 2.
Set the MODE pin condition during output discharge period.
input the horizontal shift clock signal of CK pin by shifting the phase for each line
according to the shift of the pixels connected to the same source bus line.
ff the pixels connected to the same source bus line is shifted by half the pixels, change
the clock phase 180 degrees.
Clock phase must be changed during output discharge period.
11
LH1684F
6.3
Outline
(1)
of operation
timing
Overall operation timing
Horizontal
blanking
period
<
Video signals
4
Effective
display
period
One horizontal
scanning period
0‘)
>
One horizontal
scanning period
ti+l)
.1
>
DIS
(Internal discharge signal)
Sl
s240
(Internal sampling srgnals)
OS1 to OS240
(LCD drive outputs)
Output diszge
Sampling data
(j-l) output
period
Output diszge
Sampling data
0’) output
period
Output diszrge
Sampling data
(j+l) output
period
Video signals of one horizontal scanning period are sampied into the sampleand hold circuits
at the timing of the internal sampling pulses of each output circuits, outputs are discharged
once on the GND level by the internal discharge signal, and data corresponding to the
sampled data are output.
This discharge operation is performed simultaneously for all output pins.
(2) Timing of output discharge and video signal sampling
The output discharge period (period “H” of the internal discharge signal DIS) is after3 cycles
of clock CK from the “H” period of start pulse SPD. Therefore, the output discharge period is
almost the sameperiod as the “H” period of start pulse SPD.
lfthe normal sampling operation and cascade sequence is lst, the video signal sampling
(internal sampling signalSn) is started after 15 cycles of clock CK following the fall of start
pulse SPD.
CK
SP [
DIS
c--Output discharge- period
Sl (Normal sampling operation, cascade sequence 1 st)
Video signal sampling start
12
LH 1684F
6.4
Timing
(1)
When
chart
for
RL=“H”,
normal
sampling
CSl=“H”,
operation
and CS2=“H”
j
si39
S240
(Internal samplrng signals) i
OS1 to OS240
Sampling data
output period
(2)
When
RL=“H”,
.
’ Output discharge
period
!
Sampling
data output period
!
Sampling
data output period
CSl =“L”, and CS2=“H”
S240
(Internal samplrng signals);
OS1 to OS240
Sampling data
output period
- ’ Output discharge
period
LHI 684F
(3)
When
RL=“H”,
13
CSl =“H”, and CS2=“L”
CK
SP
DIS
s240
(Internal sampltng slgnatsj /
OS1 to OS240
Sampling data
output period
(4)
When
RL=“H”,
’ Output discharge
period
CSl=“L”,
! -
Sampling data output period
and CS2=“L”
DIS
(Internal discharge signal) ;
Sl
s2
si39
s240
(Internal sampling slgnaa) i
OS1 to OS240
Sampling data
output period
’ Output discharge
period
’
Sampling
data output period
14
LH 1684F
When
RL=“L”,
CSl=“H”,
and CS;Z=“H”
DIS
Sl
(Internal sampling slgnais) ;
OS1 to OS240
Sampling data
output period
(6)
When
RL=“L”,
’ Output discharge
period
CSl=“L”,
!
Sampling data output period
!
Sampling data output period
and CS2=“H”
Sl
(Internal sampling slgnaw i
OS1 to OS240
Sampling data
output period
’ Output discharge
period
(7)
When RL=“L”,
CSl =“H”, and CS2=“L”
CK
SP
Sh
Sl
(Internal sampling srgnals) j
OS1 to OS240
Sampling data
output period
(8)
When RL=“L”,
iiternal
’ Output discharge
period
CSl =“L”,
!
Sampling
data output period
’
Sampling
data output period
and CS2=“L”
sampling signals) i
OS1 to OS240
Sampling data
output period
’ Output discharge
period
SHARP
16
LH 1684F
6.5 Timing chart for 3-point
(1)
When
RL=“H”,
CSl=“H”,
simultaneous
sampling operation
and CS2=“H”
S238 to S240
(Internal sampling srgnals)
OS1 to 240
d
Sampling data
output period
(2)
When
FiL=“H”,
CSl=“L”,
’ Output discharge ’
period
Sampling data output period
and CS2=“H”
CK
SP
S238 to S240
(Internal sampling signals)
OS1 to 240
Sampling data
output period
.‘4
’ Output discharge ’
period
Sampling data output period
SHARP
17
LH 1684F
(3)
When
RL=“H”,
CSl=“H”,
and CS2=“L”
CK
S4 to S6
1 j
5135 to S237
S238 to 5240
(Internal sampling slgnars)
OS1 to 240
u
Sampling data
output period
(4)
When
RL=“H”,
CSl=“L”,
-I
’ Output discharge !
period
Sampling data output period
and CS2=“L”
CK
SP
DIS
(Internal discharge signal)
Sl to 53
S4 to S6
S235 to S237
S238 to 5240
(Internal samplrng srgnay
OS1 to 240
.‘I
Sampling data
output period
’ Output discharge r
period
Sampling data output period
SHARP
LH1684F
(5)
When
FiL=“L”,
CSl=“H”,
and CS2=“H”
CK
SP
DIS
S240 to S238
S237 to 5235
S6 to S4
,
s3 to Sl
(Internal sampling signals)
/
OS1 to 240
-I-
Sampling data
output period
(6)
When
RL=“L”,
CSl=“L”,
Output discharge !
period
Sampling data output period
and CS2=“H”
DIS
(Internal discharge signal)
5237 to S235
S&OS4
s3 to Sl
(Internal sampling signals)
OS1 to 240
Sampling data
output period
’ Output discharge !
period
Sampling data output period
I
SHARP
19
LHI 684F
(7)
When
RL=“L”,
CSl =“H”, and CS2=“L”
CK
SP
DIS
s3 to Sl
(Internal sampilng slgnats)
OS1 to 240
1
Sampling data
output period
(8)
When
RL=“L”,
’ Output discharge !
period
Sampling data output period
CSl =“L”, and CS2=“L”
DIS
(Internal discharge signal)
OS1 to 240
Sampling data
output period
’ Output discharge ’
period
Sampling data output period
20
LH1684F
6.6
Precautions
(1)
Setting of external voltage of Vbl and Vb2 pins
The LHl684Fdoes not have the biasvoltage setting circuit forthe output operational amplifiers
and the output buffers. Therefore it is necessary to input the suitable voltage to Vbl pin and
Vb2 pin.
Set the voltage value to an optimum value in the range of Vcc to GND as shown in the diagram
below, fully evaluating the current consumption, picture quality, etc.
(Example of biascircuit)
t----r>
Vbl, Vb2
Set the resistance to Rl +R2=50 kfI
(2) Setting of Input pins
Since 6 pins of SP, CK, CTR, MODE, Vbl , and Vb2 of the input pins are not pulled up or
pulled down in the LSI, never use these 6 pins in the “OPEN” condition.
Since VA, VB, and VC pins are for inputting video signals, necessary video signals must be
input always.
Except VA, VB, VC, Vbl , Vb2, SP, CK, CTR, and MODE, all other input pins are pulled up or
pulled down in the LSI. However,because of preventing malfunction due to noise, etc., avoid
using the “OPEN” condition whenever possible, and set to “H” level or “L”level.
(3) Input video signals
Input video signalsare target for analog signals (continuous signals).
The input band of video signals is applicable up to the maximumof 10 MHz.
(4) Bypass capacitor
lfthe noise of alogicsystem is superposed on analog circuits such as the sample and hold
circuits, analog characteristics (such as output voltage deviation and dynamic range,etc.) may
deteriorate. Forthis reason, insert bypass capacits or of about 1 pF between VCC and GND.
Fully evaluate and determine the value of bypass capacits orwith actually mounted on the
LCD panel.
L
SHARI=
I H1684F
Absolute
7.
Maximum
21
Ratings
1
I
Parameter
I
I
/ Symbol
Condition
i
Rating
Supply voltage
/
Ta=+25 “c /
-0.3to+7.0
Input voltage
/
vcc
:
Ta=+25 “c j -0.3toVcc+0.3
VINCC
j Storage temperature /
Unit /
Tstg /
V
/
v
I
I
/
1 -45to+125
j
“c
/
; Unit /
Note:Standard voltage is GND (0 V).
8.
Recommended
I
1
Operating
Conditions
Parameter
i Symbol ’
I
Supply voltage
/
I
Input voltage
j
vcc
Topr
Rating
:
1
VINCC
/ Operating temperature i
Condition
!
j
/
+4.5to+5.5
i
u
0 to ucc
:
v
-3Oto+85
:
“c
j
I
/
Note:Standard voltage is GND (0 V).
9.
Electrical
Characteristics
9.1
DC characteristics
Parameter
/
Input “L” voltage
1
VIL
)
Input “H” voltage
j
‘/IH
/
Input “L” current
/
I
1111 1
llL.2 /
1
lH1
Input “H” current
!
I
1
/ Measuring /
!Symboli condition /
j
Dynamic range
j
/
I
III-I2 )
UPP
/
vIN=ov
viN=vCC
MIN
/
TYP
j
I 0.3vcc
U / Pins1,2,and3’
i
v
/
j
I
j
I
/
!
~
j
1
/vcc-0.5
i1
Unit 1 Applicable pin !
MAX
0
i
/ 0.7vcc;
vcc
1.0
j
I
/ PA / Pinsl,and3
1 50.0
,b:“,
PA j
1
ILL
1
/
I
Pins 2
Pinspil,(sa3nd2
j
I
/
! Output voltage deviation 1 VOD / (Condition 1);
Current consumption
I
) ICC 1(Condition 2)j
0.5
j
50.0
j
6.0
u
/’
VA,VB,VC
j mV ( OS1 toOS240
j mA 1
vcc
Unless otherwise specified, GND=O V, Ubl =Vb2=2.0 U, Ta=-30 to +85 “C.
[Applicable pins]
(Pin 1) Applicable to CK, CTR, SP, and MODE pins.
(Pin 2) Applicable to RL, CSl , CS2, SAM, TST, and TSTl to 4 pins.
(Pin 3) Applicable toTST5 pin.
[Measuring condition]
(Condition 1) SP signal : Cycle tSP= 63.5 ps, “H’ period width twHP = 5.0 JLS
CTR signal : Cycle tCTR = 127.0 ps, ‘H” period width tWHCT = 63.5 ps
Change from “H” to “L” and vice versa during “H” period of SP signal.
CK signal : Frequency fCK = 10.0 MHz
Pin to be set to 2.0 V : Vbl , Vb2
Pin to be set to GND : TST5
UA=VB=UC=0.5 U to Ucc-0.5 U
Connect all other pins to Vcc.
Difference between the output voltage mean value of all OS output pins in the chip
and the output voltage of each OS output pin.
Ta=25 @
!
I
/
LHl684F
22
(Condition 2) SP signal : Cycle tS? = 63.5 us, “H” period width tWHP = 5.0 ps
CTR signal : Cycle ~CTR = 127.0 us, “H” period width tWHcT = 63.5 us
Change from “H” to “L” and vice versa during “H” period of SP signal.
CK signal :
Frequency fCK = 10.0 MHz
Pin to be set to 2.0 V : Vbl , Vb2
Pin to be set to GND : TST5
Connect all other pins to Vcc.
9.2
AC characteristics
_~
! Measuring
I
/ Symbol’
condition
Parameter
Clock frequency
fCK
“H” level clock width
tWHC
j
Clock fall time
/
j
/
90.0
1
SAM=“H”
I 40.0
!
SAM=“L”
i
j SAM=“H”
I
j
I
/
I
/
I
!
j SAM=“H”
1
I
/
j SAM=“L”
/
/
j
/ 30.0
i
:
trC
SAM=“H”
90.0
SAM=“L”
trc
/
I
Dabsetuptime
/
tsu
Data holdtime
j
tH
; 30.0
!
Pulse setup time
I
tsup
0.5
/
0.5
5.0
/
I
/
Pulse holdtime
j
“H”level pulse width
/
Pulse alteration time
!
Output transfer delay time ,/
tHP
tWHP
I
tdl
tm
; Gondition)l
/
tr
Output fall time
/
tf
Unless otherwise
;
trfP
Output risetime
TYP
1
tWLC
1
I
/
!
/
,
/ MAX 1 Unit / Applicable pin
j 40.0
i
I
,
Clock rise time
MIN
,
CK
j SAM=“L’
“L” level clock width
:
/
)
I
I
I
1
j
:
t
I
specified, GND=O V, Vbl =Vb2=2.0
j ns
I
, ns
/
/ ns
I
/ ns
j
/ 10.0
/ ns
: 35.0
j ns
/
10.0
/ ns
j 35.0
I
j ns
I
/
/
j ns
j
CK, SP
j
ns
/
SP, CTR
/
i 1.0
1 0.7
/ P
/psj
) pS
/ ps
1 2.0
j
I
1
/
SP
CTR
SP
ps _I OS1 toos240
j
1.5
/
3.0
/ ps
j OS1 toos240
(
1.0
/
2.0
1 ps
/
V, Ta=-30 to +85”C.
[Measuring condition]
(Condition)
SP signal :
Cycle tsP = 63.5 ps, “H” period width tWHP = 5.0 ps
CTR signal : Cycle tCTR = 127.0 ps, “H” period width twHCT = 63.5 ps
Change from “H” to “L” and vice versa during “H” period of S P signal.
CK signal :
Frequency fcK = 10.0 MHz
Pin to be set to 2.0 V : Vbl , Vb2
Pin to be set to GND : TST5
Connect all other pins to Vcc.
Capacity of output load CL=~ 5OpF
~
’
j
:
,
LH 1684F
9.3
Timing
23
diagram
trC,
tWHC
>-4
tic
tWLC
F
CK
tWHP
CTR
I
tdl
OS1 to
OS240
SHARP
LHI 684F
10.
Example
of System
Configuration
“aA
r
:
;R
+g
b’ 4
I
I
)
t-i
m
osao0%-S0S238-
LrR
SP
ac
“al
LL
$
(D
i&E
fj
VA
VB
vc
SAM
TST
TSTl to 1
TST5
;
:
i
i
OS3 OS2 OS1 -
4 vcc
MODE
o(
SP
Controller
z
24
25
LH1684F
11. Example
of Typical
Characteristics
Parameter
/
/
Basic gate propagation
I
delay time
I
Conditions
GND=O V,Vcc=+5.0
*
Ta=+25 @
1 MIN 1 TYP I MAX / Unit
V,
’
I
I’Oi
In=
LH1684F
12. P.4CKXGE
AND
PACKING
26
SPECIFICATION
1. Package Outline Specification
Refer to drawing No. SPN4701-00
2. Markings
The meanings of the device code printed on each tape carrier package are as follows.
(1) Date code
(example)
: ---5 3 8 D 0
a) b) c) d)
a) denotes the last figure of Arino Domini
(of production)
b) denotes the week (of production)
c) denotes factory code (of production)
d) denotes the number of times of alteration
3. Packing Specifications
3-2 Packing Form
* Specification
of label
a) Tape carrier package(TCP) is wound on a reel
with separator and the ends of them are fixed
with adhesive tape.
b) A label indicating
production name, lot no.
TYPE
Production
name
and quantity is stuck on one side of the reel.
Lot
No:
c) The reel and silica gel is put in a laminated
aluminium
bag. Nitrogen
gas is enclosed in
QUANTITY
Quantity
the bag and the bag is sealed. The same
label(b) is affixed to the bag. The bag is put
LQT(DATE)
Shipping date
in a carton and the same label(b) is affixed
to one side of the inner carton.
d) 5 inner cartons are put in an outer carton and the same
label(b) is affixed to one side of the outer carton.
3-3 Other
(1) The length of the TCP is typically 40 m per reel, but this may change in
accordance with the inventory quantity.
(2) Faulty devices is conpletely punched out at the part of the device.
(3) The maximum
number of continuous faulty devices is 9.
I
4
ISSUE
DATE
AUG
ISSUE
NUMBER
H8801
S/C NUMBER
28.1996
APPROVE
CHECK
DESIGN
(NO-W
SHARP
27
LH1684F
4. Cautions concerning handling.
Althrough the strength of the device has been verified in accodance with the test
method shown below, do not subject the resin parts or the slit terminals to any
excessive bending or pressure.
Indicate as moment M.
M=FXL (N-m)
M=1.47X 10e3 N*m MAX.
(for both + B and - 0)
5. Cautions concerning stora,oe.
- When storing the product, it is recommended that it be left in its shipping package.
After the seal of the packin,0 bag has been broken, store the products in a nitrogen
atmosphere.
* Strage conditions
Straoe state
Straoe conditions
humidity : 80% RH or less.
than 60 davs) Temperature: 5 to 30°C; _____._-_-....____-_-..------------.-.
..Unopened(less
.. . . . . . ..-.-..-.-..---...---.-..‘.....----.---..-.----..-.--.--......-.
After seal of broken
Room temperature, dry nitrogen atomosphere.
* Don’t store in a location exposed to corrosive gas or excessive dust.
- Don’t store in a location exposed to direct sunlight or subject to sharp changes in
temperature.
* Don’t store the product such that it subjected to an excessive load weight, such as
by stacking.
* Deterioration of the plating may occor after long-term storage, so special‘ care
is required.
It is recommended that the products be inspected before use.
6. Other cautions.
- Immediately after opening the moisture-proof packing, the mesurement will shrink
slightly. In oder to return the mesurements to those shown in the drawing, it is
nessesary to store the product for at least 48 hours at a temperature of 20’ to 25°C
and humidity of 50 to 60%.
SliARf=
LH1684F
7. External appearance inspection
ion of the rsternal aopearance of the packare
Item
Insoection standards
I. Exposure of the inner lea
and device holes
. Faulty if.the chip or inner leads are completely
exposed.
. Faulty if the device holes are not completely
filled with resin. ’
*Faulty if there are air bubbles extending as far as
the suaface of the chip.
*Faulty if there are air bubbles at the inner leads.
2. Air bubbles
28
e shown below.
Remarks
1
t
Faulty
3. Seal resin area
-Faulty if the area of the seal resin area exceeds
the specifications.
Jpperside: 16.5 X 5.2 mmMAX
Jnderside: 16.5 X5.2 mmMAX
&. Seal resin thickness
*Faulty if the thickness of the device exceeds the
specifications.
5. Adherance of resin or
foreign matter except
the seal resin area.
‘Faulty if there is anything adhering to the tin
plating.
‘Faulty if any resin or forein matter adhered to the
copper pattern is wider than the width of the
pattern. (If the forein matter is easily moved, it is
not a cause for concern.)
Faulty if there are any cracks in the chip.
Faulty if there is any chipping in the underside of
the chip that is lager than one-half the thickness
of the chip.
Faulty if adherance of the resin to the underside
of the chip that causes the thickness of the device
exceed the specifications.
Faulty if there are any scratches exposing the
sustrate (chip, pattern. or inner leads) at the seal
resin.
Faulty if there are any scratches extending as far
as the copper foil at the sorder resists.
Faulty if there are any cracks or chipping at the
perforations.
FdUky
if the pattern overhanging the slits is
markedly deformed
Upperside:0.30 mmMAX
Underside:0.75 mmMAX
Total thickness: 1.20 mmMAX
i. Undrside of the chip
‘. Scratches, cracks and
chipping in the tape carrie
L Pattern deformation
9. Discoloration
Faulty if the tin plating is markedly discolored.
Faulty if the cover coating is markedly
discolored.
0. Markings
Faulty if the markings are illegible.
1. Missing parts of output
leads
Faulty if the width of the output lead is reduced
to less than one-half of the standard.
Faulty
if copper foil remnants reduce the clearanc
between the output leads to less than two-thirds o
the standards.
12. Other
if there is any warping, twisting. bending,
etc.. of the tape that would impair use.
Faulty if there are no indication holes at the noneffective indication holes.
FdUlty
Faulty
T/ZMAX
f
Creased
n
Faulty
SHARI=
SPECIFICATION
LOTCDATE)
OF
B
C
.TERIAL
ANTI-STATIC
TREATED
0127
36
PLASTIC
29
LABEL
SHIPPNIG
REEL
A d405,
‘IZE
LH 1684F
DATE
INNER
SIZE
CARTON
L
420
w
4-20
H
MATERIAL
CARDBOARD
DATE
UNIT
APROVE
50
AUG.
31.
1995
T1TLE
mm
CHECK
DESIGN
REEL
AND INNER
OF TCP PACKING
DRAWINGNo.
ASSEMBLY
/q,
KPN
ENGNEERING
j&...??k
SHARP
CORPORATION
CARTON
023
DEPT.
SliARP
LH1684F
30
I
I
LAM1 NATED
PACKING
VIEW
BAG
OF
SHARP
LH1684F
31
OUTER
FL
LABEL
IC
GROUP
SHARP
CORI ‘ORATION
RAWING
NO
CARTON
32
LH1684F
I
NOTES:
ANTI-STATIC
TREATED
[24.5&E.
**.O(GOOD
DEVICE
HOLE)
I,.
0.6CSL)
909(SL)
WINDING
PATTERNS
PLASTIC
I DE
L)l
I
22. aksL)
VII
1. REEL
1,
909(SL)
I
0. S(SL)
I
YSEPARETOR
.
2. RESIN
AREA
OF FRONT
AND
BACK
SURFACE
IS 16. 5X5.
2mmhAX).
3. E. L. MEANS
ASSUMED
EXCISING
LINE.
4.SL
MEANS
DIMENSION
OF PUNCHlNG
HOLE
AND
ITS
TOLERANCE
IS
k0. 05mm.
5. SR MEANS
DIMENSION
OF SOLDER
RESIST
AND
ITS
TOLERANCE
IS CO. 3mm.
6. POTTING
RESIN
IS
SL5.
0.75MAX.
CROSS
SECTION
OF
OUTPUT
LEADS
tj
m
: r:
R
(DR
*
d d ,- _*----.-\
I
\
I
\
:
\
El
- -_e*
!EL
,Ii
I
OUT
0. 4 to.
02
0. 6 to.
02
LINE
DRAWING
OF