DATA SHEET MOS INTEGRATED CIRCUIT µPD17P207 4-BIT SINGLE-CHIP MICROCONTROLLER WITH LCD CONTROLLER/DRIVER AND A/D CONVERTER FOR INFRARED REMOTE CONTROL TRANSMITTER DESCRIPTION µPD17P207 is a variation of µPD17207 and is equipped with a one-time PROM instead of an internal mask ROM. µPD17P207 is suitable for evaluating program when developing a µPD17201A and 17207 systems because program can be written by the user. When reading this document, also refer to the µPD17201A, 17207 documents. FEATURES • Internal one-time PROM: 4096 × 16 bits • 17K architecture: • Supply voltage: General-purpose register format • Pin-compatible with µ PD17201A, 17207 2.5 to 5.5 V (at fX = 4 MHz, TA = –20 to +75°C) 2.4 to 5.5 V (at fX = 4 MHz, TA = –20 to +60°C) except PROM programming functiom 2.0 to 5.5 V (at fXT = 32.768 kHz, TA = –20 to +75°C) ORDERING INFORMATION Part Number Package µPD17P207GF-001-3B9 80-pin plastic QFP (14 × 20 mm) µPD17P207GF-002-3B9 80-pin plastic QFP (14 × 20 mm) µPD17P207GF-003-3B9 80-pin plastic QFP (14 × 20 mm) The features of each product is shown in the following table: When using µPD17P207-001, be sure to connect the resonator to the main clock oscllator circuit and subclock oscillator circuit. Item Pull-up resistor of RESET pin Main clock oscillator circuit Subclock oscillator circuit µPD17P207-001 Provided µPD17P207-002 Not provided Provided Not provided µPD17P207-003 µPD17201A, 17207 Not provided Provided On request (mask option) µPD17P207 is different from µPD17201A, 17207 in some of the electrical characteristics, such as supply voltage, the operating ambient temperature, and supply current. Therefore, use µPD17P207 only for the system evaluation. The information in this document is subject to change without notice. Document No. U11777EJ3V0DS00 (3rd edition) Previous No. IC-2707A Date Published November 1996 P Printed in Japan The mark shows major revised points. © 1993 µPD17P207 PIN CONFIGURATION (TOP VIEW) RESET VREG WDOUT XTIN XTOUT VLCD0 VLCDC VLCD1 VLCD2 CAPH CAPL COM 0 COM 1 LCD35/COM 2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 1 LCD31 2 63 XIN LCD30 3 62 VDD LCD29 4 61 REM LCD28 5 60 P1A2/SI LCD27 6 59 P1A1/SO LCD26 7 58 P1A0/SCK LCD25 8 57 P0D3 LCD24 9 56 P0D2 LCD23 10 55 P0D1/TMOUT 54 P0DO/LED LCD22 11 LCD21 12 LCD20 13 LCD19 14 µ PD17P207GF-3B9 LCD32 XOUT 53 P0C3 52 P0C2 51 P0C1 50 P0C0 45 P0A3 21 44 P0A2 LCD11 22 43 P0A1 LCD10 23 42 P0A0 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 INT LCD8 GNDADC 20 LCD12 ADC 3 LCD13 ADC 2 P0B0 ADC 1 46 ADC 0 19 VADC P0B1 LCD14 LCD0 47 GND 18 LCD1 P0B2 LCD15 LCD2 P0B3 48 LCD3 49 17 LCD4 16 LCD16 LCD5 LCD17 LCD6 15 LCD7 LCD18 LCD9 2 LCD34/COM 3 LCD33 (1) Ordinary operation mode µPD17P207 (L) (L) (OPEN) (OPEN) (2) PROM programming mode 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 1 63 CLK 3 62 VDD 4 61 (OPEN) 5 60 6 59 7 58 8 57 µ PD17P207GF-3B9 9 10 11 (L) 56 55 54 53 D7 52 D6 51 D5 50 D4 49 MD 3 17 48 MD 2 18 47 MD 1 19 46 MD 0 20 45 D3 21 44 D2 22 43 D1 23 42 D0 12 (OPEN) (OPEN) 2 13 14 15 16 VPP GNDADC (L) GND (OPEN) VDD (OPEN) 41 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Caution: Those enclosed in parentheses indicate the processing of the pins not used in PROM programming mode. L : Ground these pins through a resistor (470 Ω). Open : Do not connect anything to these pins. 3 µPD17P207 Pin Name ADC0-ADC3 : A/D converter input CAPH, CAPL : Booster capacitor connection CLK : PROM clock input COM0-COM3 : LCD common signal output D0-D7 : PROM data I/O GND, GNDADC : Ground 4 INT : External interrupt request signal input LCD0-LCD35 : LCD segment signal output LED : Remote controller transfer display output MD0-MD3 : PROM mode selection input P0A0-P0A3 : I/O port P0B0-P0B3 : I/O port P0C0-P0C3 : I/O port P0D0-P0D3 : I/O port REM : Remote controller transfer output RESET : Reset signal input SCK : Serial clock I/O SI : Serial data input SO : Serial data output TMOUT : Timer output VADC : A/D converter power supply VDD : Power supply VLCD0-VLCD2 : LCD drive voltage output VLCDC : LCD drive reference voltage adjustment VPP : PROM writing power supply VREG : Voltage regulator output WDOUT : Overrun detection output XIN, XOUT : Main clock oscillator circuit XTIN, XTOUT : Subclock oscillator circuit µPD17P207 BLOCK DIAGRAM VREG Power Supply Circuit P1A0 SCK P1A1 /SO P1A P1A2 /SI RF Serial Interface RAM 336 × 4 bits LCD P0A P0B0 (MD0) P0B1 (MD1) P0B2 (MD2) P0B3 (MD3) P0B LCD0 LCD1 LCD2 LCD3 LCD4 Controller LCD33 COM3/LCD34 COM2/LCD35 COM1 COM0 SYSTEM REG. P0A0 (D0) P0A1 (D1) P0A2 (D2) P0A3 (D3) VDD CAPH CAPL VLCD0 VLCD1 VLCD2 VLCDC GMD ALU Interrupt Controller INT (Vpp ) Instruction Decoder P0C0 (D4) P0C1 (D5) P0C2 (D6) P0C3 (D7) P0C One Time PROM VADC 4096 × 16 bits ADC0 A/D Converter P0D0/LED P0D1/TMOUT P0D2 P0D3 ADC2 ADC3 P0D GNDADC Program Counter RESET Stack 5 × 12 bits REM ADC1 WDOUT Carrier Generator CPU Clock Clock Stop X IN (CLK) Main clock Timer/ Counter X OUT Watch Timer Divider CPU Clock XT IN Subclock XT OUT Remark Inside the parenthesis indicates pin names in the PROM programming mode. 5 µPD17P207 CONTENTS 1. 2. PIN FUNCTIONS ................................................................................................................................. 7 1.1 ORDINARY OPERATION MODE .............................................................................................................. 7 1.2 PROM PROGRAMMING MODE ................................................................................................................ 9 1.3 EQUIVALENT CIRCUITS OF PINS ......................................................................................................... 10 1.4 PROCESSING OF UNUSED PINS .......................................................................................................... 11 1.5 NOTES ON USING RESET AND INT PINS (ONLY IN ORDINARY OPERATION MODE) ................... 12 ONE-TIME PROM (PROGRAM MEMORY) WRITING, READING, AND VERIFICATION ............... 13 2.1 OPERATION MODE FOR WRITING, READING, AND VERIFICATION OF PROGRAM MEMORY ..... 13 2.2 PROGRAM MEMORY WRITE PROCEDURE ......................................................................................... 14 2.3 PROGRAM MEMORY READ PROCEDURE ........................................................................................... 15 3. DEFFERENCES BETWEEN µPD17P207 AND µPD17201A/17207 ................................................. 16 4. ELECTRICAL CHARACTERISTICS ................................................................................................. 17 5. PACKAGE DRAWINGS ..................................................................................................................... 25 6. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 26 APPENDIX A. MICROCONTROLLER FAMILY FOR HIGH-FUNCTION REMOTE CONTROLLER WITH LCD ........................................................................................................................ 27 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................ 28 6 µPD17P207 1. PIN FUNCTIONS 1.1 ORDINARY OPERATION MODE Pin No. Symbol 76 77 78 79 80 1 | 32 34 COM0 COM1 LCD35/COM2 LCD34/COM3 LCD33 LCD32 | LCD1 LCD0 33 GND 35 VADC 36 | 39 ADC0 | ADC3 40 GNDADC 41 INT 42 | 45 P0A0 | P0A3 46 | 49 50 | 53 Output Type On Reset CMOS, push-pull – Device ground – – Positive power supply of the A/D converter (VADC should be equal to VDD.) – – Analog inputs of the A/D converter (8-bit resolution) – – Ground of the A/D converter – – External interrupt request signal (Input). The interrupt request is generated at the rising edge of this signal. – Input 4-bit I/O port (enabling setting of inputs or outputs in 4-bit units) (Grouped I/O). Each of these pins has a pull-up resistor. CMOS, push-pull Input P0B0 | P0B3 4-bit I/O port (enabling setting of inputs or outputs in 4-bit units) (Grouped I/O). N-channel, open-drain Input P0C0 | P0C3 4-bit I/O port (enabling setting of inputs or outputs in 4-bit units) (Grouped I/O). N-channel, open-drain Input 54 P0D0/LED 55 P0D1/TMOUT 56 P0D2 57 P0D3 Function Common/segment signal outputs of the LCD driver. These common and segment signal outputs are selected by LCDMD3 to LCDMD0 of the register file. • COM0 to COM3 · Common signal outputs of the LCD driver • LCD35 to LCD0 · Segment signal outputs of the LCD driver Port 0D/LED output or 8-bit timer output. P0D0 and LED outputs are switched by NRZEN of the register file. P0D1 and 8-bit timer outputs are switched by TMOE of the register file. • P0D0 to P0D3 · 4-bit I/O port · Enabling setting of inputs or outputs of each bit (Bitwise I/O) • LED · Outputs NRZ signal in synchronization with infrared remote controller signal (REM) · Outputs high level while remote controller carrier is output from REM pin • TMOUT · Output of the 8-bit timer CMOS, push-pull Input (to be cont’d) 7 µPD17P207 (cont’d) Pin No. Symbol Function Port 1A or serial interface. Port 1A and serial interface are switched by SIOEN of the register file. • P1A0 to P1A2 · 3-bit I/O port · Enabling setting of inputs or outputs of 3 bits (Grouped I/O) • SCK, SO, SI · SCK: Serial clock I/O · SO: Serial data output · SI: Serial data input 58 P1A0/SCK 59 P1A1/SO 60 P1A2/SI 61 REM 62 VDD Positive power supply. 63 XIN These pins are connected to a 4-MHz ceramic or crystal 64 XOUT 65 RESET 66 VREG 67 WDOUT 68 XTIN 69 XTOUT for subclock oscillation. 71 VLCDC Input to regulate the reference voltage to drive LCD. 70 VLCD0 Reference voltage outputs to drive LCD. 72 VLCD1 • VLCD0: Reference voltage output 73 VLCD2 • VLCD1: Doubler output (Two times the reference voltage) Signal output to an infrared remote controller. Active-high output Output Type CMOS, push-pull CMOS, push-pull – Output of the voltage regulator for the subclock oscillation circuit. Connect external 0.1-µF capacitor to this pin. Output for detection of a program overrun. Outputs low level when the watchdog timer overflows or the stack overflows/underflows. Use this pin after connecting to the RESET pin. Input Low-level output – (Oscillation stops.) resonator for main clock oscillation. System reset input System is reset when low level is input to this pin. While this pin is low, oscillation of main clock is stopped. Only µPD17P207-001 has internal pull-up resistor. On Reset – Input – – N-channel, open drain Highimpedance – (Oscillates.) – – – – – – These pins are connected to a 32.768-kHz crystal oscillator • VLCD2: Tripler output (Three times the reference voltage) 8 74 CAPH These pins are connected to a capacitor to boost the 75 CAPL LCD drive voltage. µPD17P207 1.2 PROM PROGRAMMING MODE Pin No. Symbol 33 GND 35 VDD 40 GNDADC 41 Output Type On Reset Ground – – Positive power supply – – Ground for A/D converter Performs PROM programming with GNDADC = GND. – – VPP Positive power supply for PROM programming. Applies 12.5V as the program voltage when writing, reading, and verifying the program memory. – – 42 to 45 50 to 53 D0 to D3 D4 to D7 8-bit data I/O for PROM programming. 46 to 49 MD0 to MD3 Select operation mode for PROM programming. – Input 62 VDD Positive power supply – – 63 CLK Address update clock input – Input Remark Function CMOS, push-pull Input Pins other than the above are not used in the PROM programming mode. For the processing of unused pins, refer to (2) PROM programming mode in PIN CONFIGURATION. 9 µPD17P207 1.3 EQUIVALENT CIRCUITS OF PINS The followings are equivalent circuits (partially simplified) of the respective pins of the µPD17P207. (1) P0A (4) V DD data Output latch P-ch N-ch output disable P0D, P1A V DD V DD Output latch data N-ch output disable Selector Selector Input buffer (2) data P-ch Input buffer P0B (5) RESET V DD Output latch Pull-up resistor Note N-ch output disable Input buffer Schmitt trigger input with hysteresis characteristics Input buffer Note Only µPD17P207-001 has the internal pull-up resistor. (3) data P0C (6) Output latch N-ch output disable Input buffer Schmitt trigger input with hysteresis characteristics Selector Input buffer 10 INT µPD17P207 1.4 PROCESSING OF UNUSED PINS In ordinay operation mode, process unused pins as follows: Table 1-1. Processing of Unused Pins (a) Port pins Recommended Processing of Unused Pins Pin Name Internally Input Mode Output Mode P0A (Connect pull-up resistor.) Open P0C – Directly connect to GND. P0D, P1A – Connect each pin to VDD or GND via resistorNote. P0A (CMOS port) Outputs high level P0D, P1A (CMOS port) P0B, P0C (N-ch open-drain port) Note Externally Open – Outputs low level When externally pulling a pin up (connecting the pin to VDD via resistor) and down (connecting the pin to GND via resistor), give adequate consideration to the drive capability and current consumption of the port. To pull a pin up or down at a high resistance, make sure that no noise is superimposed on the pin. (b) Pins other than port pins Pn Name I/O Mode Recommended Processing of Unused Pin ADC0-ADC3 Input Directly connect to GND CAPH, CAPL Output Open COM0, COM1, COM2/LCD35, COM3/LCD34 Output Open Input Directly connect to GND LCD0-LCD33 Output Open REM Output Open VADC – INT Note VLCD0-VLCD2 Output VLCDC – Directly connect to VDD Open Directly connect to VDD or VLCD0 WDOUT Output Directly connect to GND XIN, XTIN Input Directly connect to GND XOUT – Directly connect to VDD XTOUT – Directly connect to VREG Note The INT pin is also used as a test mode setting pin. Directly connect this pin to GND when it is not used. Cautions 1. It is recommended that the input/output mode and output level of a pin be fixed by repeatedly setting in each loop of the program. 2. When the LCD controller/driver is not used, stop the voltage regulator by using the display mode register. 11 µPD17P207 1.5 NOTES ON USING RESET AND INT PINS (ONLY IN ORDINARY OPERATION MODE) In addition to the functions shown in 1. PIN FUNCTIONS, the RESET and INT pins also have a function to set a test mode (for IC testing) in which the internal operations of the µPD17P207are tested. When a voltage higher than VDD is applied to either of these pins, the test mode is set. This means that, even during ordinary operation, the µPD17P207 may be set in the test mode if a noise exceeding VDD is applied. For example, if the wiring length of the RESET or INT pin is too long, noise superimposed on the wiring line of the pin may cause the above problem. Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. • Connect diode with low VF between VDD and RESET/INT pin • Connect capacitor between VDD and RESET/INT pin V DD Diode with low V F V DD RESET, INT 12 V DD V DD RESET, INT µPD17P207 2. ONE-TIME PROM (PROGRAM MEMORY) WRITING, READING, AND VERIFICATION µPD17P207 sets the PROM mode when PROM writing, reading or verification as shown in Table 2-1. In PROM mode, no address input pin is used. Instead, the address is updated by the clock for input from the CLK pin. Table 2-1. Pins Used for Program Memory Writing, Reading, or Verification Pin Name 2.1 Function VPP Applies program voltage (12.5 V). CLK Inputs address update clock. MD0-MD3 Selects operation mode. D0-D7 Inputs and outputs 8-bit data. VDD Applies supply voltage (6 V). OPERATION MODE FOR WRITING, READING, AND VERIFICATION OF PROGRAM MEMORY If +6 V is applied to the VDD and +12.5 V to the VPP pin after µPD17P207 has been placed in the reset status for a fixed time (VDD = 5V, RESET = Low level), µPD17P207 enters program memory write, read, or verify mode. The MD0 to MD3 pins are used to set the operation modes listed in Table 2-2. Leave the pins not used for program memory writing, reading, or verification open or ground through pull-down resistors (470 Ω). (Refer to (2) PROM programming mode in PIN CONFIGURATION.) Table 2-2. Operating Mode for Program Memory Writing, Reading or Verification Operating Mode Specification Operating Mode VPP +12.5 V Remark VDD +6 V MD0 MD1 MD2 MD3 H L H L Program memory address 0 clear mode L H H H Write mode L L H H Read/verify mode H x H H Program inhibit mode x: L or H 13 µPD17P207 2.2 PROGRAM MEMORY WRITE PROCEDURE The program memory write procedure is as follows. High-speed program memory write is possible. (1) Ground the unused pins through pull-down resistors. The CLK pin must be low. (2) Supply 5 V to the VDD pin. The VPP pin must be low. (3) After waiting for 10 µs, supply 5 V to the VPP pin. (4) Operate the MD0 to MD3 pins to set program memory address 0 clear mode. (5) Supply 6 V to the VDD pin and 12.5 V to the VPP pin. (6) Set program inhibit mode. (7) Write data in 1-millisecond write mode. (8) Set program inhibit mode. (9) Set verify mode. If data has been written connectly, proceed to step (10). If data has not yet been written, repeat steps (7) to (9). (10) Write additional data for (the number of times data was written (X) in steps (7) to (9)) times 1 milliseconds. (11) Set program inhibit mode. (12) Supply a pulse to the CLK pin four times to update the program memory address by 1. (13) Repeat steps (7) to (12) to the last address. (14) Set program memory address 0 clear mode. (15) Change the voltages of VDD and VPP pins to 5 V. (16) Turn off the power supply. Steps (2) to (12) are illustrated below. X-time repetition Reset Write Additional data write Verify Address increment VPP VPP VDD GND VDD VDD+1 VDD GND CLK D0-D7 MD0 MD1 MD2 MD3 14 Hi-z Data input Hi-z Data output Hi-z Data input Hi-z µPD17P207 2.3 PROGRAM MEMORY READ PROCEDURE (1) Ground the unused pins through pull-down resistors. The CLK pin must be low. (2) Supply 5 V to the VDD pin. The VPP pin must be low. (3) After waiting for 10 µs, supply 5 V to the VPP pin. (4) Operate the MD0 to MD3 pins to set program memory address 0 clear mode. (5) Supply 6 V to the VDD pin and 12.5 V to the VPP pin. (6) Set program inhibit mode. (7) Set verify mode. Data of each address is sequentially output each time a clock pulse is input to the CLK pin four times. (8) Set program inhibit mode. (9) Set program memory address 0 clear mode. (10) Change the voltages of VDD and VPP pins to 5 V. (11) Turn off the power supply. Steps (2) to (9) are illustrated below. Reset VPP VPP VDD VDD GND VDD+1 VDD GND 1 cycle CLK D0-D7 Hi-z Data output Data output Hi-z MD0 MD1 “L” MD2 MD3 15 µPD17P207 3. DIFFERENCES BETWEEN µPD17P207 AND µPD17201A/17207 The µPD17P207 has a PROM to which the user can write a program in place of the internal mask ROM (program memory) of the µPD17201A and 17207. Therefore, the µPD17P207 is identical to µPD17201A and 17207 except for the program memory and mask option. However, some of the electrical characteristics, such as supply current or VLCDC voltage of the µPD17P207, are different from that of the µPD17201A and 17207. The following table lists the differences between the µPD17P207 and µPD17201A/17207. For the details of the CPU and hardware of the µPD17201A and 17207, refer to their Data Sheets. Item Product Name µPD17P207 -001 Program Memory µPD17201A µPD17207 Mask ROM 0000H-0FFFH 0000H-0BFFH 0000H-0FFFH 4096 × 16 bits 3072 × 16 bits 4096 × 16 bits Not provided Provided Provided Not provided Any (mask option) Subclock Oscillator Circuit Not provided VPP pin, PROM Programming Pin Provided Not provided VDD = 2.5 to 5.5 V (at fX = 4 MHz, TA = –20 to +75°C) VDD = 2.4 to 5.5 V (at fX = 4 MHz, TA = –20 to +60°C) VDD = 2.2 to 5.5 V (at fX = 4 MHz) Supply Voltage (TA = –20 to +75°C) Package 16 µPD17P207 -003 One-Time PROM Pull-Up Resistor of RESET Pin Main Clock Oscillator Circuit µPD17P207 -002 Provided 80-pin plastic QFP (14 × 20 mm) µPD17P207 4. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Parameter Symbol Conditions Rating Unit Supply Voltage VDD –0.3 to +7.0 V Analog Supply Voltage VADC –0.3 to +7.0 V Input Voltage VI –0.3 to VDD+0.3 V Output Voltage VO –0.3 to VDD+0.3 V Peak value –30 mA rms value –20 mA One pin (except REM) Peak value –7.5 mA –5 mA All pins (except REM) Peak value –22.5 mA rms value –15 mA Peak value 7.5 mA 5 mA 22.5 mA 15 mA REM pin High-Level Output Current IOH rms value One pin Low-Level Output Current rms value IOL All pins (except REM) Peak value rms value Operating Ambient Temperature TA –20 to +75 °C Storage Temperature Tstg –40 to +125 °C Note rms value = Peak value × √Duty Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product. CAPACITANCE (TA = 25°C, VDD = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit CIN1 INT and RESET pins 10 pF CIN2 Other than INT and RESET pins 10 pF Input Capacitance RECOMMENDED OPERATING RANGES (TA = –20 to + 75°C) Parameter Symbol MIN. TYP. MAX. Unit System clock fX = 4 MHz 2.5 3.0 5.5 V fX = 4 MHz, TA = –20 to + 60°C 2.4 3.0 5.5 V VDD2 System clock fX = 8 MHz 4.5 5.0 5.5 V VDD3 System clock fXT = 32.768 kHz 2.0 3.0 5.5 V 1.0 4.0 8.0 MHz VDD1 Supply Voltage Main Clock Oscillation Frequency fX Subclock Oscillation Frequency fXT Conditions 32.768 kHz 17 µPD17P207 MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –20 to +75°C, VDD = 2.5 to 5.5 V) Resonator Recommended Constants X IN Item Conditions Oscillation Note 1 frequency (fX) X OUT MIN. TYP. MAX. Unit 1.0 4 8.0 MHz 4 ms 8.0 MHz 10 ms 30 ms Note 3 Ceramic Resonator C1 C2 X IN C1 From when VDD reaches the minimum oscillation voltage Oscillation frequency (fX) Note 1 X OUT Note 3 Crystal Resonator Note 2 Oscillation stabilization time C2 Note 2 Oscillation stabilization time 1.0 4 VDD = 4.5 to 5.5V Notes 1. The oscillation frequency is indicated only to express the oscillator characteristics. Refer to the AC characteristics for instruction execution time. 2. The oscillation stabilization time is the time required for stabilizing the oscillation after VDD is applied or the STOP mode is released. 3. The recommended resonators are shown in the table described later. SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS Resonator Recommended Constants X IN X OUT Item Oscillation frequency (fXT) Conditions MIN. TYP. MAX. 32.768 Unit kHz Crystal Resonator Oscillation stabilization time Caution 5 10 s When using the main system clock and the subsystem clock generators, in order to avoid wiring capacitance effects, the following notations must be read and observed for wiring the portion inside the dotted line in the table: • Wiring length must be minimized. • Do not cross with other signal lines. Do not wire close to a large current line. • Capacitors used in the oscillators must always be grounded to GND potential level. Never ground the grounding pattern having a large current flow. • Do not take the signal directly out of the oscillator. In order to reduce the power consumption, the subsystem clock oscillator employs a low amplification factor circuit. Because of this, the subsystem clock oscillator is more sensitive to noise than the main system clock oscillator. Therefore, when using the subsystem clock, wiring must be carefully planned. 18 µPD17P207 RECOMMENDED RESONATORS Main System Clock : Ceramic Resonator External Capacitance (pF) Manufacturer Oscillation Voltage Range (V) Part Name Remarks C1 C2 MIN. MAX. CSA3.58MG 30 30 2.0 6.0 CSA4.00MG 30 30 2.0 6.0 CSA4.19MG 30 30 2.0 6.0 CST3.58MGW Not required Not required 2.0 6.0 CST4.00MGW Not required Not required 2.0 6.0 CST4.19MGW Not required Not required 2.0 6.0 KBR3.58MS 33 33 2.0 6.0 KBR4.0MS 33 33 2.0 6.0 KBR4.19MS 33 33 2.0 6.0 TOKO CRHF4.00 18 18 2.0 6.0 DAISHINKU PRS0400BCSAN 39 33 2.0 6.0 MURATA Mfg. KYOCERA Built-in capacitor Main System Clock : Crystal Resonator Manufacturer KINSEKI Frequency (MHz) 4.0 Holder HC-49U-S External Capacitance (pF) Oscillation Voltage Range (V) C1 C2 MIN. MAX. 22 22 2.0 6.0 Remarks 19 µPD17P207 DC CHARACTERISTICS (TA = –20 to +75°C, VDD = VADC = 3 V) Parameter Symbol Test Condition MIN. TYP. MAX. Unit VIH1 RESET and INT pins 2.4 3 V VIH2 Other than RESET and INT pins 2.1 3 V VIL1 RESET and INT pins 0 0.6 V VIL2 Other than RESET and INT pins 0 0.9 V ILIH1 XTIN, XTOUT, XIN, and XOUT pins 20 µA ILIH2 Other than XTIN, XTOUT, XIN, and XOUT pins 3 µA ILIL1 XTIN, XTOUT, XIN, and XOUT pins –20 µA ILIL2 Other than XTIN, XTOUT, XIN, and XOUT pins –3 µA IOH1 REM pin VOH = 1.8 V –7 –15 mA IOH2 Note 1 VOH = 2.7 V –0.3 –0.7 mA IOL Note 2 VOL = 0.3 V 0.5 0.9 mA RP0A P0A0 to P0A3 pins 100 200 350 kΩ RRES RESET pins (µPD17P207-001 only) 24 47 94 kΩ ±2 LSB High-Level Input Voltage Low-Level Input Voltage High-Level Input Leakage Current Low-Level Input Leakage Current High-Level Output Current Low-Level Output Current Built-In Pull-Up Resistor A/D Absolute Precision A/D Resolution A/D Converter Current Consumption 8 IADC Comparator Error In comparator mode IDD1 IDD2 Supply Current X installed (fX = 4.19 MHz) XT not installed IDD3 IDD4 Note 3 IDD5 X not installed or STOP mode XT installed (fXT = 32.768 kHz) RUN mode Bits 60 120 µA 10 20 mV 1.6 2.2 mA 1.8 mA HALT mode STOP mode 3.0 10.0 µA RUN mode 400 600 µA HALT mode 20 40 µA Notes 1. P0A0 to P0A3, P0D0 to P0D3, and P1A0 to P1A2 pins 2. P0A0 to P0A3, P0B0 to P0B3, P0C0 to P0C3, P0D0 to P0D3, P1A0 to P1A2, WDOUT, and REM pins 3. The specifications of the main STOP mode (sub-mounting) are the same as the sub-HALT mode (with the main clock oscillation stopped). LCD CHARACTERISTICS (TA = –20 to +75°C, VDD = 3 V) Parameter 20 Symbol Test Condition MIN. TYP. MAX. Unit 0.65 0.8 V 1.8 V VLCDC Output Voltage VLCDC TA = 25°C, R1 = R2 = 1 MΩ 0.5 LCD Reference Output Voltage VLCD0 External variable resistance (0 to 2.2 MΩ) 0.8 Doubler Output Voltage VLCD1 C1 to C4 = 0.47 µF 1.9 2.0 VLCD0 Tripler Output Voltage VLCD2 C1 to C4 = 0.47 µF 2.85 3.0 VLCD0 LCD Common Output Current ICOM Output voltage deviation = 0.2 V 30 µA LCD Segment Output Current ILCD Output voltage deviation = 0.2 V 5 µA µPD17P207 AC CHARACTERISTICS (TA = –20 to +75°C, VDD = 2.0 to 5.5 V) Parameter Symbol Condition MIN. TYP. MAX. Data input 2.0 µs Data output 10 µs Data input 5 µs Data output 13 µs Data input 1.0 µs tKH, Data output 5.0 µs tKL Data input 2.5 µs Data output 6.5 µs VDD = 5 V±10 % SCK Input Cycle Time tKCY VDD = 5 V±10 % SCK Input High- and Low-Level Widths Unit SI Setup Time (Vs. SCK↑) tSIK 100 ns SI Hold Time (Vs. SCK↑) tKSI 100 ns SCK↓→to SO Output Delay Time tKSO INT High-and Low-Level Width tIOH, tIOL 50 µs RESET Low-Level Width tRSL 50 µs P0A Low-Level Width tRLSL 10 µs CL = 100 pF 4.5 At standby release µs SERIAL TRANSFER TIMING 3-line Serial I/O Mode: t KCY t KL t KH SCK t SIK SI t KSI Input data t KSO SO Output data 21 µPD17P207 DC PROGRAMMING CHARACTERISTICS (TA = 25°C, VDD = 6.0 ±0.25V, VPP = 12.5 ±0.3V) Parameter High-Level Input Voltage Low-Level Input Voltage Symbol MAX. Unit VIH1 Other than CLK Conditions 0.7 VDD VDD V VIH2 CLK V DD –0.5 VDD V VIL1 Other than CLK 0 0.3 VDD V 0 0.4 V 10 µA VIL2 CLK Input Leakage Current ILI VIN = VIL or V IH High-Level Output Voltage VOH IOH = –1 mA Low-Level Output Voltage VOL IOL = 1.6 mA VDD Supply Current IDD VPP Supply Current IPP MD0 = V IL, MD1 = V IH Cautions 1. VPP must not exceed +13.5 V, including the overshoot. 2. Apply VDD before VPP and disconnect it after VPP. 22 MIN. TYP. V DD –1.0 V 0.4 V 30 mA 30 mA µPD17P207 AC PROGRAMMING CHARACTERISTICS (TA = 25°C, VDD = 6.0 ±0.25V, VPP = 12.5 ±0.3V) Parameter Address Setup Time Note 2 Symbol Note 1 (vs.MD0↓) MD1 Setup Time (vs. MD0↓) Conditions MIN. TYP. MAX. Unit tAS tAS 2 µs tM1S tOES 2 µs µs Data Setup Time (vs. MD 0↓) tDS tDS 2 Address Hold Time Note 2 (vs.MD0↑) tAH tAH 2 µs Data Hold Time (vs. MD0↑) tDH tDH 2 µs MD0 ↑→ Data Output Float Delay Time tDF tDF 0 µs µs V PP Setup Time (vs. MD3↑) tVPS tVPS 2 V DD Setup Time (vs. MD 3↑) tVDS tVCS 2 Initial Program Pulse Width tPW tPW 0.95 Additional Program Pulse Width tOPW tOPW 0.95 2 MD0 Setup Time (vs. MD1↑) tMOS tCES MD0 ↓→ Data Output Delay Time tDV tDV MD1 Hold Time (vs. MD0↑) tM1H tOEH MD1 Recovery Time (vs. MD0↓) tM1R tOR 130 1.0 tM1H + t M1R ≥ 50 µs 1.05 ms 21.0 ms µs 1 MD0 = MD 1 = VIL µs µs 2 µs 2 µs µs µs tPCR – 10 tXH,tXL – 0.125 CLK Input Frequency fX – Initial Mode Set Time tI – 2 µs µs Program Counter Reset Time CLK Input High-/Low- Level Width 4 MHz MD3 Setup Time (vs. MD1↑) tM3S – 2 MD3 Hold Time (vs. MD1↓) tM3H – 2 µs MD3 Setup Time (vs. MD0↓) tM3SR – 2 µs tDAD tACC Address Note 2 → Data Output Delay Time Address Note 2 → Data Output Hold Time tHAD tOH MD3 Hold Time (vs. MD0↑) tM3HR – MD3 ↓→ Data Output Float Delay Time tDFR – Reset Setup Time tRES – When data is read from 0 program memory 2 2 µs 130 µs µs 2 10 µs µs Notes 1. These symbols are the corresponding µPD27C256A (maintenance product) symbols. 2. The internal address is incremented by 1 at the third falling edge of CLK (with four clocks constituting as one cycle). The internal address is not connected to any pin. 23 µPD17P207 PROGRAM MEMORY WRITE TIMING t RES VPP VDD t VPS VPP VDD GND VDD+1 VDD GND t VDS t XH CLK D0 to D7 Hi-z Hi-z Data input t DS t OH tI Hi-z Data output t DV t DF t XL Data input t DH t AH t DS Hi-z Data input t AS MD0 tMOS t M1R t PW t OPW MD1 t PCR t M1S t M1H MD2 t M3H t M3S MD3 PROGRAM MEMORY READ TIMING t RES t VPS VPP VPP VDD GND VDD VDD+1 VDD GND t VDS t XH CLK t XL Hi-z D0 to D7 MD0 MD1 “L” t PCR MD2 t M3SR MD3 24 Data output t DV tI t HAD t DAD Hi-z Data output t M3HR t DFR Hi-z µPD17P207 5. PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14 20) A B 64 65 41 40 detail of lead end C D S Q R 25 24 80 1 F J G H I M P K M N NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. L ITEM MILLIMETERS INCHES A 23.2±0.2 0.913 +0.009 –0.008 B 20.0±0.2 0.787 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 17.2±0.2 0.677±0.008 F 1.0 0.039 G 1.8 0.031 H 0.35±0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P.) K 1.6±0.2 0.063±0.008 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.125±0.075 0.005±0.003 R 5°±5° 5°±5° S 3.0 MAX. 0.119 MAX. S80GF-80-3B9-3 25 µPD17P207 6. RECOMMENDED SOLDERING CONDITIONS When mounting the µPD17P207 by soldering, soldering should be performed under the following recommended contitions. For details on recommended soldering conditions, refer to the information document “Semconductor Device Mounting Technology Manual” (C10535E). For other soldering methods, please cousult with NEC sales personnel. Table 6-1. Conditions for Surface Mounting µPD17P207GF-001-3B9 : 80-pin plastic QFP ( 14 × 20 mm) µPD17P207GF-002-3B9 : 80-pin plastic QFP ( 14 × 20 mm) µPD17P207GF-003-3B9 : 80-pin plastic QFP ( 14 × 20 mm) Soldering Method Infrared Reflow Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (210°C min.), Number of times: 2 max., Number of days: 7Note (after that, prebaking is necessary at 125 °C for 20 hours) <Precaution> Products other than those supplied in thermal-resistant tray (magazine, taping, and non-thermal-resistant tray) cannot be baked in their packs. Package peak temperature: 215°C Time: 40 seconds max. (200°C min.), Number of times: 2 max., Number of days: 7Note (after that, prebaking is necessary at 125 °C for 20 hours) <Precaution> Products other than those supplied in thermal-resistant tray (magazine, taping, and non-thermal-resistant tray) cannot be baked in their packs. VPS Wave Soldering Soldering bath temperature: 260 °C max., Time: 10 seconds max., Number of times: 1 Preheating temperature: 120 °C max. (package surface temperature) Number of days: 7Note (after that, prebaking is necessary at 125 °C for 20 hours) Partial Heating Pin temperature: 300°C max., Time: 3 seconds max. (per device) Note IR35-207-2 VP15-207-2 WS 60-207-1 Number of days after unpacking the dry pack. Storage conditions are 25°C and 65 %RH max. Caution Do not use different soldering methods together (however, pin partial heating can be performed with other soldering methods). 26 Recommended Conditions Reference Code µPD17P207 APPENDIX A. MICROCONTROLLER FAMILY FOR HIGH-FUNCTION REMOTE CONTROLLER WITH LCD Item Product Name ROM Capacity µPD17201A µPD17207 µPD17P207 3072 × 16 bits (Mask ROM) 4096 × 16 bits (Mask ROM) 4096 × 16 bits (One-Time PROM) 336 × 4 bits RAM Capacity LCD Controller/Driver Infrared Remote Controller Carrier Generator 136 segments max. LED output is high-active. Number of I/O Ports 19 External Interrupt (INT) 1 Timer 2 channels 8-bit timer : 1 Watch timer : 1 Watchdog Timer Internal (WDOUT output) Serial Interface 1 channel Stack 5 levels (3 levels for multiplexed interrupt) Instruction Execution Time Supply Voltage (TA = –20 to +75°C) Main System Clock Subsystem Clock Main System Clock Subsystem Clock Standby Function Pakcage Note 4 µs (4 MHz: with ceramic or crystal oscillator) 488 µs (32.768 kHz: with crystal osciallator) 2.5 to 5.5 V 2.2 to 5.5 V 2.4 to 5.5 V Note 2.0 to 5.5 V STOP, HALT 80-pin plastic QFP TA = –20 to + 60°C 27 µPD17P207 APPENDIX B. DEVELOPMENT TOOLS To develop the programs for the µPD17P207, the following development tools are available: Hardware Name In-Circuit Emulator IE-17K IE-17K-ET EMU-17K Note 1 Note 2 Remarks IE-17K, IE-17K-ET, and EMU-17K are the in-circuit emulators used in common with the 17K series microcomputer. IE-17K and IE-17K-ET are connected to a PC-9800 series or IBM PC/ATTM as the host machine with RS-232C. EMU-17K is inserted into the expansion slot of a PC-9800 series. By using these in-circuit emulators with a system evaluation board corresponding to the microcomputer, the emulators can emulate the microcomputer. A higher level debugging environment can be provided by using man-machine interface SIMPLEHOSTTM. EMU-17K also has a function by which you can check the contents of data memory realtime. SE Board (SE-17207) This is an SE board for µPD17201A, 17207, and 17P207. It can be used alone to evaluate a system or in combination with an in-circuit emulator for debugging. Emulation Probe (EP-17201GF) EP-17201GF is an emulation probe for µPD17201A, 17207, and 17P207. When used with EV-9200G-80, it connects an SE board to the target system. Conversion Socket (EV-9200G-80 Note 3) EV-9200G-80 is a conversion socket for 80-pin QFP (14 × 20 mm) and is used to connect EP-17201GF to the target system. PROM Programmer (AF-9703 Note 4, AF-9704 Note 4, AF-9705 Note 4, AF-9706 Note 4) AF-9703, AF-9704, AF-9705, and AF-9706 are PROM programmers corresponding to µPD17P207. By connecting program adapter AF-9808A to this PROM programmer, µPD17P207 can be programmed. Program Adapter (AF-9808 Note 4) AF-9808A is an adapter that is used to program µPD17P207, and is used in combination with AF-9703, AF-9704, AF-9705, or AF-9706. Notes 1. Low-cost model: External power supply type 2. This is a product from IC Corp. For details, consult IC Corp. 3. Two EV-9200G-80s are supplied with the EP-17201GF. Five EV-9200G-80s are optionally available as a set. 4. These are products from Ando Electric. For details, consult Ando Electric. 28 µPD17P207 Software Name 17K Series Assembler (AS17K) Device File AS17201 AS17207 Host Machine Outline AS17K is an assembler that can be used in common with the 17K series products. When developing the program of the µPD17P207, AS17K is used in combination with a device file (AS17201 or AS17207). AS17201 is a device file for µPD17201A. AS17207 is a device file for µPD17207. These are used in combination with an assembler for the 17K series (AS17K). PC-9800 series IBM PC/AT PC-9800 series IBM PC/AT Support Software (SIMPLEHOST) SIMPLEHOST is a software package that enables manmachine interface on the TM Windows when a program is developed by using an in-circuit emulator and a personal computer. PC-9800 series Supply Order Code 5" 2HD µS5A10AS17K 3.5" 2HD µS5A13AS17K 5" 2HC µS7B10AS17K 3.5" 2HC µS7B13AS17K 5" 2HD µS5A10AS17201 µS5A10AS17207 3.5" 2HD µS5A13AS17201 µS5A13AS17207 5" 2HC µS7B10AS17201 µS7B10AS17207 3.5" 2HC µS7B13AS17201 µS7B13AS17207 5" 2HD µS5A10IE17K 3.5" 2HD µS5A13IE17K 5" 2HC µS7B10IE17K 3.5" 2HC µS7B13IE17K MS-DOSTM PC DOSTM MS-DOS PC DOS MS-DOS Windows IBM PC/AT Remark OS Media PC DOS The corresponding OS versions are as follows: OS Version MS-DOS Ver. 3.30 to Ver. 5.00A Note PC DOS Ver. 3.1 to Ver. 5.0 Windows Ver. 3.0 to Ver. 3.1 Note Note Ver. 5.00/5.00A of MS-DOS and Ver. 5.0 of PC DOS have a task swap function, but this function cannot be used with this software. 29 µPD17P207 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 30 µPD17P207 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 31 µPD17P207 [MEMO] SIMPLEHOST is a trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5