SITRONIX ST7576

ST
Sitronix
ST7576
66 x 102 Dot Matrix LCD Controller/Driver
1. INTRODUCTION
The ST7576 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 102 segments
and 65 common with 1 ICON driver circuits. This chip is connected directly to a microprocessor, accepts 3-line or 4-line
serial peripheral interface (SPI), I2C interface or 8-bit parallel interface, display data can stores in an on-chip display
data RAM of 66 x 102 bits. It performs display data RAM read/write operation with no external operating clock to
minimize power consumption. In addition, because it contains power supply circuits to drive liquid crystal, it is possible
to make a display system with the fewest components.
2. FEATURES
Single-chip LCD controller & driver
-
Generation of intermediate LCD bias voltages
Driver Output Circuits
-
Oscillator requires no external components
102 segment / 65 common+1 ICON common (1/66 duty)
(external clock also possible)
102 segment / 16 common+1 ICON common (1/17 duty)
-
Voltage converter X4; X5
(1/17 duty is under partial screen mode)
-
Voltage follower
On-chip Display Data Ram
-
On-chip electronic contrast control function (255
-
Capacity: 66X102=6,732 bits
steps)
Microprocessor Interface
-
-
External RESB (reset) pin
8-bit parallel bi-directional interface with
Logic supply voltage range
6800-series or 8080-series
-
VDD1 -VSS : 1.8 to 3.3V
4-line SPI (serial peripheral interface) available
-
VDD2 -VSS : 2.4 to 3.3V
(only write operation)
-
Display supply voltage range (V0)
3-line SPI (serial peripheral interface) available
2
I C (Inter-Integrated Circuit) Interface
On-chip Low Power Analog Circuit
-
-
Application Vop range: 4V-9.5V
-
Programmable Max V0: 10.5V
Temperature range: -30 to +85 degree
Generation of LCD supply voltage
ST7576
6800 , 8080 ,
4-Line , 3-Line interface
(without I2C interface)
ST7576i
I2C
Ver 1.0
interface
1/54
2007/01/29
ST7576
3. ST7576 Pad Arrangement
Chip Size: 5570 um ×770 um
Bump Height: 15 um
Chip Thickness: 480 um
Bump Pitch: (minimum)
PAD Number
Unit: um
Pitch
PAD Number
Pitch
1~27, 130~156, 157~163, 243~250:
37.20
212~213
46.65
28~129:
33.00
213~216,218~221
33.30
27~28
62.90
216~217,217~218
38.80
129~130
60.69
221~222
46.30
163~164
329.57
228~229
66.40
164~207, 208~211,222~228,229~235,236~242
59.30
235~236
62.45
207~208
131.83
242~243
79.90
211~212
71.30
* Refer to “Pad Center Coordinates” section for ITO layout.
Fig 1
Ver 1.0
2/54
2007/01/29
ST7576
Pad Center Coordinates
66 Duty (TMY=0)
PAD NO. PIN Name
Fig 2
Ver 1.0
3/54
X
Y
1
COM[59]
2695.50
293.00
2
COM[58]
2658.30
293.00
3
COM[57]
2621.10
293.00
4
COM[56]
2583.90
293.00
5
COM[55]
2546.70
293.00
6
COM[54]
2509.50
293.00
7
COM[53]
2472.30
293.00
8
COM[52]
2435.10
293.00
9
COM[51]
2397.90
293.00
10
COM[50]
2360.70
293.00
11
COM[49]
2323.50
293.00
12
COM[48]
2286.30
293.00
13
COM[47]
2249.10
293.00
14
COM[46]
2211.90
293.00
15
COM[45]
2174.70
293.00
16
COM[44]
2137.50
293.00
17
COM[43]
2100.30
293.00
18
COM[42]
2063.10
293.00
19
COM[41]
2025.90
293.00
20
COM[40]
1988.70
293.00
21
COM[39]
1951.50
293.00
22
COM[38]
1914.30
293.00
23
COM[37]
1877.10
293.00
24
COM[36]
1839.90
293.00
25
COM[35]
1802.70
293.00
26
COM[34]
1765.50
293.00
27
COM[33]
1728.30
293.00
28
SEG[0]
1665.39
282.75
29
SEG[1]
1632.39
282.75
30
SEG[2]
1599.39
282.75
2007/01/29
ST7576
PAD NO.
PIN Name
X
Y
X
Y
31
SEG[3]
1566.39
282.75
61
SEG[33]
576.39
282.75
32
SEG[4]
1533.39
282.75
62
SEG[34]
543.39
282.75
33
SEG[5]
1500.39
282.75
63
SEG[35]
510.39
282.75
34
SEG[6]
1467.39
282.75
64
SEG[36]
477.39
282.75
35
SEG[7]
1434.39
282.75
65
SEG[37]
444.39
282.75
36
SEG[8]
1401.39
282.75
66
SEG[38]
411.39
282.75
37
SEG[9]
1368.39
282.75
67
SEG[39]
378.39
282.75
38
SEG[10]
1335.39
282.75
68
SEG[40]
345.39
282.75
39
SEG[11]
1302.39
282.75
69
SEG[41]
312.39
282.75
40
SEG[12]
1269.39
282.75
70
SEG[42]
279.39
282.75
41
SEG[13]
1236.39
282.75
71
SEG[43]
246.39
282.75
42
SEG[14]
1203.39
282.75
72
SEG[44]
213.39
282.75
43
SEG[15]
1170.39
282.75
73
SEG[45]
180.39
282.75
44
SEG[16]
1137.39
282.75
74
SEG[46]
147.39
282.75
45
SEG[17]
1104.39
282.75
75
SEG[47]
114.39
282.75
46
SEG[18]
1071.39
282.75
76
SEG[48]
81.39
282.75
47
SEG[19]
1038.39
282.75
77
SEG[49]
48.39
282.75
48
SEG[20]
1005.39
282.75
78
SEG[50]
15.39
282.75
49
SEG[21]
972.39
282.75
79
SEG[51]
-17.60
282.75
50
SEG[22]
939.39
282.75
80
SEG[52]
-50.60
282.75
51
SEG[23]
906.39
282.75
81
SEG[53]
-83.60
282.75
52
SEG[24]
873.39
282.75
82
SEG[54]
-116.60
282.75
53
SEG[25]
840.39
282.75
83
SEG[55]
-149.60
282.75
54
SEG[26]
807.39
282.75
84
SEG[56]
-182.60
282.75
55
SEG[27]
774.39
282.75
85
SEG[57]
-215.60
282.75
56
SEG[28]
741.39
282.75
86
SEG[58]
-248.60
282.75
57
SEG[29]
708.39
282.75
87
SEG[59]
-281.60
282.75
58
SEG[30]
675.39
282.75
88
SEG[60]
-314.60
282.75
59
SEG[31]
642.39
282.75
89
SEG[61]
-347.60
282.75
60
SEG[32]
609.39
282.75
90
SEG[62]
-380.60
282.75
Ver 1.0
PAD NO. PIN Name
4/54
2007/01/29
ST7576
PAD NO. PIN Name
X
Y
PAD NO. PIN Name
X
Y
91
SEG[63]
-413.60
282.75
121
SEG[93]
-1403.60
282.75
92
SEG[64]
-446.60
282.75
122
SEG[94]
-1436.60
282.75
93
SEG[65]
-479.60
282.75
123
SEG[95]
-1469.60
282.75
94
SEG[66]
-512.60
282.75
124
SEG[96]
-1502.60
282.75
95
SEG[67]
-545.60
282.75
125
SEG[97]
-1535.60
282.75
96
SEG[68]
-578.60
282.75
126
SEG[98]
-1568.60
282.75
97
SEG[69]
-611.60
282.75
127
SEG[99]
-1601.60
282.75
98
SEG[70]
-644.60
282.75
128
SEG[100]
-1634.60
282.75
99
SEG[71]
-677.60
282.75
129
SEG[101]
-1667.60
282.75
100
SEG[72]
-710.60
282.75
130
COMS1
-1728.30
293.00
101
SEG[73]
-743.60
282.75
131
COM[0]
-1765.50
293.00
102
SEG[74]
-776.60
282.75
132
COM[1]
-1802.70
293.00
103
SEG[75]
-809.60
282.75
133
COM[2]
-1839.90
293.00
104
SEG[76]
-842.60
282.75
134
COM[3]
-1877.10
293.00
105
SEG[77]
-875.60
282.75
135
COM[4]
-1914.30
293.00
106
SEG[78]
-908.60
282.75
136
COM[5]
-1951.50
293.00
107
SEG[79]
-941.60
282.75
137
COM[6]
-1988.70
293.00
108
SEG[80]
-974.60
282.75
138
COM[7]
-2025.90
293.00
109
SEG[81]
-1007.60
282.75
139
COM[8]
-2063.10
293.00
110
SEG[82]
-1040.60
282.75
140
COM[9]
-2100.30
293.00
111
SEG[83]
-1073.60
282.75
141
COM[10]
-2137.50
293.00
112
SEG[84]
-1106.60
282.75
142
COM[11]
-2174.70
293.00
113
SEG[85]
-1139.60
282.75
143
COM[12]
-2211.90
293.00
114
SEG[86]
-1172.60
282.75
144
COM[13]
-2249.10
293.00
115
SEG[87]
-1205.60
282.75
145
COM[14]
-2286.30
293.00
116
SEG[88]
-1238.60
282.75
146
COM[15]
-2323.50
293.00
117
SEG[89]
-1271.60
282.75
147
COM[16]
-2360.70
293.00
118
SEG[90]
-1304.60
282.75
148
COM[17]
-2397.90
293.00
119
SEG[91]
-1337.60
282.75
149
COM[18]
-2435.10
293.00
120
SEG[92]
-1370.60
282.75
150
COM[19]
-2472.30
293.00
Ver 1.0
5/54
2007/01/29
ST7576
PAD NO. PIN Name
X
Y
PAD NO. PIN Name
X
Y
151
COM[20]
-2509.50
293.00
181
VDD1
-1134.54
-311.50
152
COM[21]
-2546.70
293.00
182
VDD1
-1075.23
-311.50
153
COM[22]
-2583.90
293.00
183
VDD1
-1015.92
-311.50
154
COM[23]
-2621.10
293.00
184
VDD1
-956.62
-311.50
155
COM[24]
-2658.30
293.00
185
VDD2
-897.32
-311.50
156
COM[25]
-2695.50
293.00
186
VDD2
-838.01
-311.50
157
COM[32]
-2695.50
-293.00
187
VDD2
-778.70
-311.50
158
COM[31]
-2658.30
-293.00
188
VDD2
-719.40
-311.50
159
COM[30]
-2621.10
-293.00
189
RESB
-660.09
-311.50
160
COM[29]
-2583.90
-293.00
190
CSB
-600.79
-311.50
161
COM[28]
-2546.70
-293.00
191
RWR
-541.48
-311.50
162
COM[27]
-2509.50
-293.00
192
ERD
-482.18
-311.50
163
COM[26]
-2472.30
-293.00
193
A0
-422.88
-311.50
164
VDX2O
-2142.72
-311.50
194
VDD1
-363.57
-311.50
165
VDX2O
-2083.42
-311.50
195
D7
-304.27
-311.50
166
VDX2O
-2024.11
-311.50
196
D6
-244.96
-311.50
167
VSS2
-1964.81
-311.50
197
D5
-185.66
-311.50
168
T11
-1905.50
-311.50
198
D4
-126.35
-311.50
169
T12
-1846.19
-311.50
199
D3
-67.05
-311.50
170
BR
-1786.89
-311.50
200
D2
-7.74
-311.50
171
CP
-1727.58
-311.50
201
D1
51.56
-311.50
172
TMX
-1668.28
-311.50
202
D0
110.87
-311.50
173
TMY
-1608.97
-311.50
203
OSC
170.17
-311.50
174
PS2
-1549.67
-311.50
204
VSS2
229.47
-311.50
175
PS1
-1490.36
-311.50
205
VSS2
288.78
-311.50
176
PS0
-1431.06
-311.50
206
VSS2
348.09
-311.50
177
VMO
-1371.75
-311.50
207
VSS2
407.39
-311.50
178
VMO
-1312.45
-311.50
208
VSS1
539.23
-311.50
179
VMO
-1253.14
-311.50
209
VSS1
598.53
-311.50
180
VSS2
-1193.84
-311.50
210
VSS1
657.84
-311.50
Ver 1.0
6/54
2007/01/29
ST7576
PAD NO. PIN Name
X
Y
PAD NO. PIN Name
X
Y
211
VSS1
717.15
-311.50
241
XV0I
2295.89
-311.50
212
VRS
788.45
-311.50
242
XV0S
2355.20
-311.50
213
T1
835.10
-307.75
243
COMS2
2435.10
-293.00
214
T2
868.40
-307.75
244
COM[60]
2472.30
-293.00
215
T3
901.70
-307.75
245
COM[61]
2509.50
-293.00
216
T4
935.00
-307.75
246
COM[62]
2546.70
-293.00
217
T0
973.80
-307.75
247
COM[63]
2583.90
-293.00
218
T5
1012.60
-307.75
248
COM[64]
2621.10
-293.00
219
T6
1045.90
-307.75
249
Reserved
2658.30
-293.00
220
T7
1079.20
-307.75
250
Reserved
2695.50
-293.00
221
T8
1112.50
-307.75
222
VGO
1158.81
-311.50
223
VGO
1218.11
-311.50
224
VGI
1277.42
-311.50
225
VGI
1336.72
-311.50
226
VGI
1396.03
-311.50
227
VGI
1455.33
-311.50
228
VGS
1514.64
-311.50
229
V0O
1581.08
-309.75
230
V0O
1640.38
-309.75
231
V0I
1699.69
-309.75
232
V0I
1759.00
-309.75
233
V0I
1818.30
-309.75
234
V0I
1877.60
-311.50
235
V0S
1936.91
-311.50
236
XV0O
1999.36
-311.50
237
XV0O
2058.67
-311.50
238
XV0I
2117.98
-311.50
239
XV0I
2177.28
-311.50
240
XV0I
2236.58
-311.50
Ver 1.0
7/54
2007/01/29
ST7576
66 Duty (TMY=1)
PAD NO. PIN Name
X
Y
PAD NO. PIN Name
X
Y
1
COM[5]
2695.50
293.00
31
SEG[3]
1566.39
282.75
2
COM[6]
2658.30
293.00
32
SEG[4]
1533.39
282.75
3
COM[7]
2621.10
293.00
33
SEG[5]
1500.39
282.75
4
COM[8]
2583.90
293.00
34
SEG[6]
1467.39
282.75
5
COM[9]
2546.70
293.00
35
SEG[7]
1434.39
282.75
6
COM[10]
2509.50
293.00
36
SEG[8]
1401.39
282.75
7
COM[11]
2472.30
293.00
37
SEG[9]
1368.39
282.75
8
COM[12]
2435.10
293.00
38
SEG[10]
1335.39
282.75
9
COM[13]
2397.90
293.00
39
SEG[11]
1302.39
282.75
10
COM[14]
2360.70
293.00
40
SEG[12]
1269.39
282.75
11
COM[15]
2323.50
293.00
41
SEG[13]
1236.39
282.75
12
COM[16]
2286.30
293.00
42
SEG[14]
1203.39
282.75
13
COM[17]
2249.10
293.00
43
SEG[15]
1170.39
282.75
14
COM[18]
2211.90
293.00
44
SEG[16]
1137.39
282.75
15
COM[19]
2174.70
293.00
45
SEG[17]
1104.39
282.75
16
COM[20]
2137.50
293.00
46
SEG[18]
1071.39
282.75
17
COM[21]
2100.30
293.00
47
SEG[19]
1038.39
282.75
18
COM[22]
2063.10
293.00
48
SEG[20]
1005.39
282.75
19
COM[23]
2025.90
293.00
49
SEG[21]
972.39
282.75
20
COM[24]
1988.70
293.00
50
SEG[22]
939.39
282.75
21
COM[25]
1951.50
293.00
51
SEG[23]
906.39
282.75
22
COM[26]
1914.30
293.00
52
SEG[24]
873.39
282.75
23
COM[27]
1877.10
293.00
53
SEG[25]
840.39
282.75
24
COM[28]
1839.90
293.00
54
SEG[26]
807.39
282.75
25
COM[29]
1802.70
293.00
55
SEG[27]
774.39
282.75
26
COM[30]
1765.50
293.00
56
SEG[28]
741.39
282.75
27
COM[31]
1728.30
293.00
57
SEG[29]
708.39
282.75
28
SEG[0]
1665.39
282.75
58
SEG[30]
675.39
282.75
29
SEG[1]
1632.39
282.75
59
SEG[31]
642.39
282.75
30
SEG[2]
1599.39
282.75
60
SEG[32]
609.39
282.75
Ver 1.0
8/54
2007/01/29
ST7576
PAD NO. PIN Name
X
Y
PAD NO. PIN Name
X
Y
61
SEG[33]
576.39
282.75
91
SEG[63]
-413.60
282.75
62
SEG[34]
543.39
282.75
92
SEG[64]
-446.60
282.75
63
SEG[35]
510.39
282.75
93
SEG[65]
-479.60
282.75
64
SEG[36]
477.39
282.75
94
SEG[66]
-512.60
282.75
65
SEG[37]
444.39
282.75
95
SEG[67]
-545.60
282.75
66
SEG[38]
411.39
282.75
96
SEG[68]
-578.60
282.75
67
SEG[39]
378.39
282.75
97
SEG[69]
-611.60
282.75
68
SEG[40]
345.39
282.75
98
SEG[70]
-644.60
282.75
69
SEG[41]
312.39
282.75
99
SEG[71]
-677.60
282.75
70
SEG[42]
279.39
282.75
100
SEG[72]
-710.60
282.75
71
SEG[43]
246.39
282.75
101
SEG[73]
-743.60
282.75
72
SEG[44]
213.39
282.75
102
SEG[74]
-776.60
282.75
73
SEG[45]
180.39
282.75
103
SEG[75]
-809.60
282.75
74
SEG[46]
147.39
282.75
104
SEG[76]
-842.60
282.75
75
SEG[47]
114.39
282.75
105
SEG[77]
-875.60
282.75
76
SEG[48]
81.39
282.75
106
SEG[78]
-908.60
282.75
77
SEG[49]
48.39
282.75
107
SEG[79]
-941.60
282.75
78
SEG[50]
15.39
282.75
108
SEG[80]
-974.60
282.75
79
SEG[51]
-17.60
282.75
109
SEG[81]
-1007.60
282.75
80
SEG[52]
-50.60
282.75
110
SEG[82]
-1040.60
282.75
81
SEG[53]
-83.60
282.75
111
SEG[83]
-1073.60
282.75
82
SEG[54]
-116.60
282.75
112
SEG[84]
-1106.60
282.75
83
SEG[55]
-149.60
282.75
113
SEG[85]
-1139.60
282.75
84
SEG[56]
-182.60
282.75
114
SEG[86]
-1172.60
282.75
85
SEG[57]
-215.60
282.75
115
SEG[87]
-1205.60
282.75
86
SEG[58]
-248.60
282.75
116
SEG[88]
-1238.60
282.75
87
SEG[59]
-281.60
282.75
117
SEG[89]
-1271.60
282.75
88
SEG[60]
-314.60
282.75
118
SEG[90]
-1304.60
282.75
89
SEG[61]
-347.60
282.75
119
SEG[91]
-1337.60
282.75
90
SEG[62]
-380.60
282.75
120
SEG[92]
-1370.60
282.75
Ver 1.0
9/54
2007/01/29
ST7576
PAD NO. PIN Name
X
Y
PAD NO. PIN Name
X
Y
121
SEG[93]
-1403.60
282.75
151
COM[44]
-2509.50
293.00
122
SEG[94]
-1436.60
282.75
152
COM[43]
-2546.70
293.00
123
SEG[95]
-1469.60
282.75
153
COM[42]
-2583.90
293.00
124
SEG[96]
-1502.60
282.75
154
COM[41]
-2621.10
293.00
125
SEG[97]
-1535.60
282.75
155
COM[40]
-2658.30
293.00
126
SEG[98]
-1568.60
282.75
156
COM[39]
-2695.50
293.00
127
SEG[99]
-1601.60
282.75
157
COM[32]
-2695.50
-293.00
128
SEG[100]
-1634.60
282.75
158
COM[33]
-2658.30
-293.00
129
SEG[101]
-1667.60
282.75
159
COM[34]
-2621.10
-293.00
130
COMS1
-1728.30
293.00
160
COM[35]
-2583.90
-293.00
131
COM[64]
-1765.50
293.00
161
COM[36]
-2546.70
-293.00
132
COM[63]
-1802.70
293.00
162
COM[37]
-2509.50
-293.00
133
COM[62]
-1839.90
293.00
163
COM[38]
-2472.30
-293.00
134
COM[61]
-1877.10
293.00
164
VDX2O
-2142.72
-311.50
135
COM[60]
-1914.30
293.00
165
VDX2O
-2083.42
-311.50
136
COM[59]
-1951.50
293.00
166
VDX2O
-2024.11
-311.50
137
COM[58]
-1988.70
293.00
167
VSS2
-1964.81
-311.50
138
COM[57]
-2025.90
293.00
168
T11
-1905.50
-311.50
139
COM[56]
-2063.10
293.00
169
T12
-1846.19
-311.50
140
COM[55]
-2100.30
293.00
170
BR
-1786.89
-311.50
141
COM[54]
-2137.50
293.00
171
CP
-1727.58
-311.50
142
COM[53]
-2174.70
293.00
172
TMX
-1668.28
-311.50
143
COM[52]
-2211.90
293.00
173
TMY
-1608.97
-311.50
144
COM[51]
-2249.10
293.00
174
PS2
-1549.67
-311.50
145
COM[50]
-2286.30
293.00
175
PS1
-1490.36
-311.50
146
COM[49]
-2323.50
293.00
176
PS0
-1431.06
-311.50
147
COM[48]
-2360.70
293.00
177
VMO
-1371.75
-311.50
148
COM[47]
-2397.90
293.00
178
VMO
-1312.45
-311.50
149
COM[46]
-2435.10
293.00
179
VMO
-1253.14
-311.50
150
COM[45]
-2472.30
293.00
180
VSS2
-1193.84
-311.50
Ver 1.0
10/54
2007/01/29
ST7576
PAD NO. PIN Name
X
Y
PAD NO. PIN Name
X
Y
181
VDD1
-1134.54
-311.50
211
VSS1
717.15
-311.50
182
VDD1
-1075.23
-311.50
212
VRS
788.45
-311.50
183
VDD1
-1015.92
-311.50
213
T1
835.10
-307.75
184
VDD1
-956.62
-311.50
214
T2
868.40
-307.75
185
VDD2
-897.32
-311.50
215
T3
901.70
-307.75
186
VDD2
-838.01
-311.50
216
T4
935.00
-307.75
187
VDD2
-778.70
-311.50
217
T0
973.80
-307.75
188
VDD2
-719.40
-311.50
218
T5
1012.60
-307.75
189
RESB
-660.09
-311.50
219
T6
1045.90
-307.75
190
CSB
-600.79
-311.50
220
T7
1079.20
-307.75
191
RWR
-541.48
-311.50
221
T8
1112.50
-307.75
192
ERD
-482.18
-311.50
222
VGO
1158.81
-311.50
193
A0
-422.88
-311.50
223
VGO
1218.11
-311.50
194
VDD1
-363.57
-311.50
224
VGI
1277.42
-311.50
195
D7
-304.27
-311.50
225
VGI
1336.72
-311.50
196
D6
-244.96
-311.50
226
VGI
1396.03
-311.50
197
D5
-185.66
-311.50
227
VGI
1455.33
-311.50
198
D4
-126.35
-311.50
228
VGS
1514.64
-311.50
199
D3
-67.05
-311.50
229
V0O
1581.08
-309.75
200
D2
-7.74
-311.50
230
V0O
1640.38
-309.75
201
D1
51.56
-311.50
231
V0I
1699.69
-309.75
202
D0
110.87
-311.50
232
V0I
1759.00
-309.75
203
OSC
170.17
-311.50
233
V0I
1818.30
-309.75
204
VSS2
229.47
-311.50
234
V0I
1877.60
-311.50
205
VSS2
288.78
-311.50
235
V0S
1936.91
-311.50
206
VSS2
348.09
-311.50
236
XV0O
1999.36
-311.50
207
VSS2
407.39
-311.50
237
XV0O
2058.67
-311.50
208
VSS1
539.23
-311.50
238
XV0I
2117.98
-311.50
209
VSS1
598.53
-311.50
239
XV0I
2177.28
-311.50
210
VSS1
657.84
-311.50
240
XV0I
2236.58
-311.50
Ver 1.0
11/54
2007/01/29
ST7576
PAD NO. PIN Name
X
Y
241
XV0I
2295.89
-311.50
242
XV0S
2355.20
-311.50
243
COMS2
2435.10
-293.00
244
COM[4]
2472.30
-293.00
245
COM[3]
2509.50
-293.00
246
COM[2]
2546.70
-293.00
247
COM[1]
2583.90
-293.00
248
COM[0]
2621.10
-293.00
249
Reserved
2658.30
-293.00
250
Reserved
2695.50
-293.00
Ver 1.0
12/54
2007/01/29
ST7576
4. BLOCK DIAGRAM
1 COM59
27 COM33
250 RESERVATION
249 RESERVATION
244 COM60
243 COMS
242 XV0S
238~241 XV0I
236~237 XV0O
235 V0S
231~234 V0I
229~230 V0O
228 VGS
224~227 VGI
222~223 VGO
221 T8
220 T7
219 T6
218 T5
217 T0
216 T4
215 T3
214 T2
213 T1
212 VRS
208~211 VSS1
204~207 VSS2
203 OSC
202 D0
201 D1
200 D2
199 D3
198 D4
197 D5
196 D6
195 D7
194 VDD1
193 A0
192 RD
191 WR
190 CSB
189 RESB
185~188 VDD2
181~184 VDD1
180 VSS2
179 VMO
178 VMO
177 VMO
176 PS0
175 PS1
174 PS2
173 TMY
172 TMX
171 CP
170 BR
169 T12
168 T11
167 VSS2
164~166 VDX2
163 COM26
157 COM32
18
XV0
Vss
V0
D0
D1
D2
D3
D4
D5
D6
D7
17
15
A0
/RD
/WR
CSB
RESB
VG
14
13
12
11
10
VDD
16
7 8 9
28 SEG0
129 SEG101
130 COMS
131 COM0
156 COM25
2 3 4 5 6
2007/01/29
13/54
Ver 1.0
1
SYSTEMSIDE
......
......
..........................................
.............................................
.............................................
ITOSIDE
FPCSIDE
C=1.0uF
Fig 3 Block diagram
ST7576
5. PINNING DESCRIPTIONS
Pin Name
I/O
Description
No. of Pins
Lcd driver outputs
LCD segment driver outputs
This display data and the M signal control the output voltage of segment
driver.
Segment drover output voltage
Display data
Frame
Normal display Reverse display
SEG0 to SEG101
O
COM0 to COM64
O
COMS
O
H
H
VG
VSS
H
L
VSS
VG
L
H
VSS
VG
L
L
VG
VSS
102
Power save mode
VSS
VSS
LCD column driver outputs
This internal scanning data and M signal control the output voltage of
common driver.
Common drover output voltage
Display data
Frame
Normal display Reverse display
H
H
XV0
H
L
V0
L
H
VM
L
L
VM
Power save mode
VSS
65
Common output for the icons
The output signals of two pins are same. When not used, this pin should
be left open.
2
MICROPROCESSOR INTERFACE
PS[2:0]
I
CSB
I
RESB
I
A0
I
Ver 1.0
Microprocessor interface select input pin
PS2 PS1 PS0
State
" L " " L " " L " 4 Pin-SPI MPU interface
" H " " L " " L " 3 Pin-SPI MPU interface
" L " " H " " L " 8080-series parallel MPU interface
" H " " H " " L " 6800-series parallel MPU interface
"H"
"H"
" H " I2C interface
3
Chip select input pins
Data/instruction I/O is enabled only when CSB is "L". When chip select
is non-active, DB0 to DB7 is high impedance.
There is no CSB pin in I2C interface, so this pin can fix to ” H”
Reset input pin
When RESB is "L", initialization is executed.
It determines whether the data bits are data or a command.
A0="H“: Indicates that D0 to D7 are display data.
A0="L“: Indicates that D0 to D7 are control data.
There is no A0 pin in three line or I2C interface, so this pin can fix to ” H”
14/54
1
1
1
2007/01/29
ST7576
Read/Write execution control pin (PS[0:1]=[L:H])
RWR
PS2
MPU type
/WR(R/W)
H
6800-series
R/W
I
L
8080-series
/WR
Description
Read/Write control input pin
R/W="H“: read
R/W="L”: write
Write enable clock input pin
The data on D0 to D7 are latched
at the rising edge of the /WR
signal
1
When in the serial interface must fix to ”H”
Read/Write execution control pin (PS[0:1]=[L:H])
PS2
ERD
I
MPU Type
/RD (E)
H
6800-series
E
L
8080-series
/RD
Description
Read/Write control input pin
R/W="H“: When E is "H", D0 to D7
are in an output status.
R/W="L“: The data on D0 to D7 are
latched at the falling edge of the E
signal.
Read enable clock input pin
When /RD is "L", D0 to D7 are in an
output status.
1
When in the serial interface must fix to ” H”
When using 8-bit parallel interface : 6800 . 8080
8-bit bi-directional data bus that is connected to the standard 8-bit
microprocessor data bus.
When chip select is not active, D0 to D7 is high impedance.
When using serial interface: 4-LINE.3-LINE
D7: serial input clock (SCLK) ; D6: serial input data (SDA)
D5: command/data selection (A0) ; D4: chip select pin(CSB)
D3,D2.D1.D0: must fix to ” H”
When using 3-line A0 must fix to “H”
D7(SCLK)
D6(SDA)
D5(A0)
D4(CSB)
D3 to D0
I/O
D7 to D6 (SA)
D5 to D4(X)
D3 to D2 (SDA_OUT)
D1 (SDA_IN)
D0 (SCLK)
Ver 1.0
When using I2C interface
D7: serial clock input (SCLK)
D6: serial input data (SDA_IN)
D3, D2: (SDA_OUT) serial data acknowledge for the I2C interface. By
connecting SDA_OUT to SDA_IN externally, the SDA line becomes fully
2
I C interface compatible. Having the acknowledge output separated
from the serial data line is advantageous in chip on glass (COG)
applications. In COG application where the track resistance from the
SDA_OUT pad to the system SDA line can be significant, a potential
divider is generated by the bus pull-up resistor and the ITO track
resistance. It is possible the during the acknowledge cycle the ST7576
will not be able to create a valid logic 0 level. By splitting the SDA_IN
input from the SDA_OUT output the device could be used in a mode
that ignores the acknowledge bit. In COG applications where the
acknowledge cycle is required, it is necessary to minimize the track
resistance from the SDA_OUT pad to the system SDA line to guarantee
a valid low level.
D6, D3,D2 must be connected together (SDA)
D4, D5: must fix to ” H”
D0, D1: Is slave address (SA0,SA1), must fix to “H” or “L”
Chip select input pins “CSB” not used must fix to “H”
15/54
8
2007/01/29
ST7576
LCD DRIVER SUPPLY
OSC
I
When the on-chip oscillator is used, this input must be connected
to VDD1. An external clock signal, if used, is connected to this input. If
the oscillator and external clock are both inhibited by connecting the
OSC pin to VSS the display is not clocked and may be left in a DC state.
To avoid this, the chip should always be put into Power Down Mode
before stopping the clock.
1
Power Supply Pins
VSS1
Power
Digital ground: must be connected with VSS2
4
VSS2
Power
Analog ground: must be connected with VSS1
6
VDX2
Power
Testing mode power.
Must be floating.
3
VDD1
Power
Digital Supply voltage:1.8V~3.3V
The 2 supply rails VDD1 and VDD2 could be connected together.
Digital Option pin must connect to VDD1 to pull high
5
VDD2
Power
Analog Supply voltage:1.8V~3.3V
The 2 supply rails VDD1 and VDD2 could be connected together.
4
XV0
Power
Negative LCD driver supply voltage
XV0O, XV0I & XV0S should be separated in ITO layout.
XV0O, XV0I & XV0S should be connected together in FPC layout.
7
V0
Power
Positive LCD driver supply voltage
V0 ≥ VG ≥ VM ≥ VSS ≥ XV0
V0O, V0I & V0S should be separated in ITO layout.
V0O, V0I & V0S should be connected together in FPC layout.
7
VG
Power
LCD driving voltage for segments
VGO, VGI & VGS should be separated in ITO layout.
VGO, VGI & VGS should be connected together in FPC layout.
7
VMO
Power
VM output. LCD driving voltage for commons.
3
VRS
Power
Monitor Voltage Regulator level, must be left open.
1
Ver 1.0
16/54
2007/01/29
ST7576
Configuration Pins
CP
I
Set Booster stages. (“L”=4X; “H”=5X)
CP pin set the default value of booster stages after reset , and booster
stage can be changed by software instruction
1
BR
I
Set LCD bias ratio. (“L”=1/7; “H”=1/9)
BR pin set the default value of bias ratio after reset , and bias ratio can
be changed by software instruction
1
TMX
I
Mirror X: SEG bi-direction selection
TMX connect to VSS : normal direction (SEG0àSEG101)
1
TMX connect to VDD : reverse direction (SEG101àSEG0)
TMY
I
Mirror Y: COM bi-direction selection
TMY connect to VSS (TMY=0): normal direction
TMY connect to VDD (TMY=1): reverse direction
1
See Pad Center Coordinates at page 3~10.
Test Pin
T0~T8
T
Do NOT use. Reserved for testing.
Must be floating
9
T11
T
Do NOT use. Reserved for testing.
Must be pull high
1
T12
T
Do NOT use. Reserved for testing.
Must be pull low
1
ST7576 I/O PIN ITO Resister Limitation
PIN Name
ITO Resister
PS[2:0], OSC, CP, BR, T11, T12
No Limitation
T0~T8, VRS, VDX2, TMX, TMY
Floating
VDD1, VDD2, VSS
<100Ω
V0(V0I, V0O, V0S), VG(VGI, VGO, VGS), XV0(XV0I, XV0O, XV0S), VM
<500Ω
A0, /WR, /RD, CSB, D7…D0
<1KΩ
RESB
RESB<10KΩ
Ver 1.0
17/54
2007/01/29
ST7576
6. FUNCTIONS DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
There is CSB pin for chip selection. The ST7576 can interface with an MPU when CSB is "L". When CSB is “H”, these pins
are set to any other combination, A0, /RD(E), and /WR(R/W) inputs are disabled and D0 to D7 are to be high impedance.
And, in case of serial interface, the internal shift register and the counter are reset.
Parallel / Serial Interface
ST7576 has five types of interface with an MPU, which are three serial and two parallel interfaces. This parallel or serial
interface is determined by PS [0:2] pin as shown in table 1.
Table 1. Parallel/Serial Interface Mode
PS2
"L"
"H"
"L"
"H"
"H"
PS1
"L"
"L"
"H"
"H"
"H"
PS0
"L"
"L"
"L"
"L"
"H"
State
4 Pin-SPI MPU interface
3 Pin-SPI MPU interface
8080-series parallel MPU interface
6800-series parallel MPU interface
I2C interface
Parallel Interface
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS2 as shown in table 2.
The type of data transfer is determined by signals at A0, /RD (E) and /WR(R/W) as shown in table 3.
PS2
H
L
PS1
H
H
Table 2. Microprocessor Selection for Parallel Interface
PS0 CSB
A0
/RD (E) /WR (R/W)
D0 to D7
MPU bus
L
CSB
A0
E
R/W
D0 to D7 6800-series
L
CSB
A0
/RD
/WR
D0 to D7 8080-series
Table 3. Parallel Data Transfer
6800-series
8080-series
Description
E
R/W
/RD
/WR
A0
(/RD)
(/WR)
(E)
(R/W)
H
H
H
L
H
Display data read out
H
H
L
H
L
Display data write
L
H
H
L
H
Register status read
L
H
L
H
L
Writes to internal register (instruction)
NOTE: When /RD (E) pin is always pulled high for 6800-series interface, it can be used CSB for enable signal. In this case,
interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at A0, /WR(R/W)
as in case of 6800-series mode.
Common
Serial Interface
Serial Mode
4-line SPI interface
PS2
L
PS1
L
PS0
L
CSB
CSB
3-line SPI interface
H
L
L
CSB
I2C interface
H
H
H
Not Used
Fix to “H”
Ver 1.0
18/54
A0
Used
Not Used
Fix to “H”
Not Used
Fix to “H”
2007/01/29
ST7576
PS2= “L”, PS1= “L”, PS0= “L”: 4-line SPI interface
When the ST7576 is active (CSB=”L”), serial data (D6) and serial clock (D7) inputs are enabled. When CSB is “High”, the
internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication is controlled by the register
selection pin (A0). The signals transferred on data bus will be display data when A0 is high and will be instruction when A0
is low. The read feature is not supported in this mode. Serial data on SDA (D6) is latched at the rising edge of serial clock
on SCLK (D7). After the eighth serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM column
address pointer will be increased by one automatically after each byte of DDRAM access.
1 COM59
. .. .. . .. .. .. . .. .. .. . .. .. . .. .. .. . .. .. .. . .. .
249 RESE RVATION
. . .. ..
250 R ESERVA TIO N
244 COM60
243 COMS
242 XV0S
235 V0S
231~234 V0I
238~241 XV0I
236~237 XV0O
229~230 V0O
228 VGS
8
9
10
VG
V0
XV0
C
224~227 VGI
222~223 VGO
221 T8
220 T7
219 T6
218 T5
217 T0
216 T4
215 T3
214 T2
213 T1
212 VRS
208~211 VSS1
202 X
203 OSC
Vss
204~207 VSS2
201 X
CSB
200 X
A0
199 X
SDA
198 CSB(D4)
SCLK
197 A0(D5)
19 5 SCLK( D7)
196 SDA(D6)
194 VDD1
7
193 X
6
192 RD
5
191 WR
4
190 X
3
189 RE SB
2
RESB
185~188 VDD2
1
27 COM33
28 SE G0
129 SEG101
. .. . .. .. .. . .. .. . .. .. .. . .. .. . .. .. .. . .. .. .. . .. .
VDD
S I D E
181~184 VDD1
180 V SS2
179 VMO
178 VMO
177 VMO
176 PS0
175 PS1
174 PS2
173 TMY
172 TMX
S ID E
171 CP
F P C
S Y S T E M
170 BR
S ID E
169 T12
I T O
168 T11
167 V SS2
164~166 VDX2
163 COM26
157 COM32
.. . .. .
130 COMS
131 COM0
156 COM25
. . .. .. .. . .. .. .. . .. .. . .. .. .. . .. .. .. . .. .. . .. .. .
= 1 . 0 u F
Fig 4 4-line SPI Timing
PS2= “L”, PS1= “L”, PS0= “H”: 3-line SPI interface
When ST7576 is active (CSB=”L”), SDA-out, SDA-in and SCL inputs are enabled. When ST7576 is not active (CSB=”H”),
the internal 8-bit shift register and the 3-bit counter are reset. The A0 pin is not available in this mode. Before issuing serial
data, an A0 bit is required to indicate the access is data or instruction. The read feature is not supported in this mode
except ID code read feature. Serial data on SDA (D6) is latched at the rising edge of serial clock on SCLK (D7). After the
eighth serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM column address pointer will be
increased by one automatically after each byte of DDRAM access.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 CO M59
27 CO M33
28 S EG 0
129 S EG 101
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
249 RE SE RVAT ION
. . . . . .
2 50 RES ERV ATI ON
243 CO MS
244 C OM60
242 XV0 S
235 V0S
231~ 234 V0I
238~241 X V0I
236~237 XV0O
229 ~230 V0O
221 T8
228 V G S
224~227 V G I
220 T7
222~223 V G O
219 T6
218 T5
217 T0
216 T4
215 T3
214 T2
213 T1
212 V RS
208~211 V SS 1
202 X
203 O SC
204~207 V SS 2
201 X
200 X
199 X
1 98 CS B(D 4)
197 X
193 X
195 S CLK( D7)
1 96 SD A(D 6)
192 R D
194 V DD 1
191 WR
190 X
189 R ESB
185~188 V DD 2
179 VMO
181~184 V DD 1
178 VMO
177 VMO
180 V SS 2
176 PS 0
175 PS1
171 C P
E
I D
E
5
6
7
C
=
1
. 0
u
8
9
V0
4
XV0
3
VG
V DD
2
Vss
1
C SB
E
SD A
I D
SC LK
S
R ESB
M
174 PS2
S
E
173 TMY
C
T
170 BR
P
S
I D
172 TMX
Y
S
169 T12
F
S
O
168 T11
I T
167 V SS 2
163 CO M26
164~166 V DX 2
157 CO M32
. . . . . .
13 0 CO MS
131 CO M0
156 CO M25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F
Fig 5 3-line SPI Timing
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ST7576
PS2= “H”, PS1= “H”, PS0= “H”: I2C Interface
The I2C interface receives and executes the commands sent via the I2C Interface. It also receives RAM data and sends it to
the RAM.
The I2C Interface is for bi-directional, two-line communication between different ICs or modules. The two lines are a Serial
Data line (SDA) and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data
transfer may be initiated only when the bus is not busy.
BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of
the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated
in Fig.6.
START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock
is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined
as the STOP condition (P). The START and STOP conditions are illustrated in Fig.7.
SYSTEM CONFIGURATION
The system configuration is illustrated in Fig.8.
- Transmitter: the device, which sends the data to the bus
- Receiver: the device, which receives the data from the bus
- Master: the device, which initiates a transfer, generates clock signals and terminates a transfer
- Slave: the device addressed by a master
- Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message
- Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed
to do so and the message is not corrupted
- Synchronization: procedure to synchronize the clock signals of two or more devices.
ACKNOWLEDGE
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the
transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that
acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master
receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a
STOP condition. Acknowledgement on the I2C Interface is illustrated in Fig.9.
1 COM59
250 RES ERVATION
243 COMS
244 COM60
9
......
249 RESERVA TIO N
235 V0S
V0
XV0
VG
8
242 X V0S
238~241 XV0I
236~237 X V0O
231~234 V0I
229~230 V0O
221 T8
7
. .. . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . .. . . . . . .
228 V GS
220 T7
224~227 VGI
219 T6
222~223 V GO
218 T5
217 T0
216 T4
215 T3
V ss
214 T2
213 T1
203 OSC
20 2 SA0 (D0 )
201 SA1(D1)
212 VRS
208~211 VS S1
200 SDA _O UT(D 2)
204~207 VS S2
SDA
199 SDA _O UT(D 3)
SCLK
198 X
197 X
193 X
196 SDA_IN(D6)
VDD
192 RD
19 5 SCLK(D7 )
6
191 WR
4
194 VDD1
3
190 X
2
189 RESB
1
27 COM33
28 SEG0
129 SE G101
. .. . . . . . . .. . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. .
RESB
185~188 V DD2
181~184 V DD1
176 PS 0
180 VSS2
175 PS1
179 VMO
178 VMO
177 VMO
171 CP
174 PS2
S ID E
170 BR
S ID E
173 TMY
F P C
S Y S T E M
169 T12
S ID E
172 TMX
IT O
168 T11
167 VSS2
163 COM26
164~166 VDX2
157 COM32
......
130 COMS
131 COM0
156 COM25
. . . . . . . .. . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . .
C = 1 .0 u F
Fig 6 Bit transfer
Fig 7 Definition of START and STOP conditions
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ST7576
Fig 8 System configuration
Fig 9 Acknowledgement on the I2C Interface
I2C Interface protocol
The ST7576 supports command, data write addressed slaves on the bus.
Before any data is transmitted on the I2C Interface, the device, which should respond, is addressed first. Four 7-bit slave
addresses (0111100,0111101, 0111110 and 0111111) are reserved for the ST7576. The least significant bit of the slave
address is set by connecting the input SA0 and SA1 to either logic 0 or logic 1 (VDD1).
The I2C Interface protocol is illustrated in Fig.10.
The sequence is initiated with a START condition (S) from the I2C Interface master, which is followed by the slave address.
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C Interface transfer. After
acknowledgement, one or more command words follow which define the status of the addressed slaves.
A command word consists of a control byte, which defines Co and A0, and a data byte.
The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a
cleared Co bit, only data bytes will follow. The state of the A0 bit defines whether the data byte is interpreted as a command
or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte,
depending on the A0 bit setting; either a series of display data bytes or command data bytes may follow. If the A0 bit is set
to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer
is automatically updated and the data is directed to the intended ST7576 device. If the A0 bit of the last control byte is set to
logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received
commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the bus
master issues a STOP condition (P). If no acknowledge is generated by the master after a byte, the driver stops
transferring data to the master.
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Co
0
1
Co
Co
R/W
ST7576
Fig 10 I2C Interface protocol
Last control byte to be sent. Only a stream of data bytes is allowed to follow.
This stream may only be terminated by s STOP or RE-START condition.
Another control byte will follow the data byte unless a STOP or RE-START condition is received.
Data Transfer
The ST7576 uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU
to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in Fig. 11. And when reading
data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU
reads this stored data from bus holder for the next data read cycle as shown in Fig. 12. This means that a dummy read
cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the
data of the specified address cannot be output with the read display data instruction right after the address sets, but can be
output at the second read of data.
MPU signal
A0
/WR
D0 to D7
N
D(N)
D(N+1) D(N+2)
D(N+3)
N
D(N)
D(N+1)
D(N+2)
D(N+3)
N
N+1
N+2
N+3
Internal signals
/WR
BUS HOLDER
COLUMN ADDRESS
Fig 11 Write Timing
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ST7576
MPU signal
A0
/W R
/RD
Dummy
N
D0 to D7
D(N)
D(N+1)
Internal signals
/WR
/RD
BUS HOLDER
COLUMN ADDRESS
N
N
D(N)
D(N+1)
D(N+2)
D(N)
D(N+1)
D(N+2)
Fig 12 Read Timing
DISPLAY DATA RAM (DDRAM)
The ST7576 contains a 66X102 bit static RAM that stores the display data. The display data RAM store the dot data for the
LCD. It has a 66(8 pageX8 bit +1 pageX1 bit +1 pageX1 bit) X 102 . There is a direct correspondence between X-address
and column output number. It is 66-row by 102-column addressable array. Each pixel can be selected when the page and
column addresses are specified. The 65 rows are divided into 8 pages of 8 lines (0~63 COM) and 8th page with single line
(D0)(64COM) and 9th page with a single line (D0)(COMS (ICOM). Data is read from or written to the 8 lines of each page
directly through D0 to D7. The display data of D0 to D7 from the microprocessor correspond to the LCD common lines. The
microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently,
data can be written into RAM at the same time as data is being displayed without causing the LCD flicker.
Page Address Circuit
This circuit is for providing a Page Address to Display Data RAM. It incorporates 4-bit Page Address register changed by
only the “Set Page” instruction. Page Address 9 is a special RAM area for the icons and display data D0 is only valid.
Line Address Circuit
This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line
Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of
on-chip RAM as shown in Fig. 10. It incorporates 7-bit Line Address register changed by only the initial display line
instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line
counter which is increased by CL signal and generates the line address for transferring the 102-bit RAM data to the display
data latch circuit. When icon is selected by setting icon page address, display data of icons are not scrolled because the
MPU cannot access Line Address of icons.
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ST7576
Column Address Circuit
Column Address Circuit has an 8-bit preset counter that provides Column Address to the Display Data RAM as shown in
figure16. The display data RAM column address is specified by the Column Address Set command. The specified column
address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed
continuously.
ADDRESSING
Data is downloaded in bytes into the RAM matrix of ST7576. The display RAM has a matrix of 66 by 102 bits. The address
pointer addresses the columns. The address ranges are: X 0 to 101 (1100101),Y 0 to 9 (1001) .Addresses outside these
ranges are not allowed.In vertical addressing mode (V=1) the Y address increments after each byte. After the last Y
address (Y = 8), Y wraps around to 0 and X increments to address the next column.In horizontal addressing mode (V=0)
the X address increments after each byte. After the last X address(X = 101) X wraps around to 0 and Y increments to
address the next row.After the very last address (X = 101, Y = 8) the address pointers wrap around to address (X = 0, Y =0)
D0
D7
LSB
MSB
LSB
1 bit
Xaddress
0
10
1
0
1
2
3
4
5
6
7
8
9
Fig13 RAM format
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Yaddress
Data structure
ST7576
Data structure
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
0
1
2
3
4
5
18
19
20
21
22
23
24
25
26
0
6
7
8
9
917
X-address
101
0 1 2
102103104
204205206
306307308
408409410
510511512
612613614
714715716
816817818
0
917
X-address
0
1
2
3
4
5
6
7
8
9
Y-address
Fig14 Sequence of writing data bytes into RAM with vertical addressing (V=1)
101
Fig15 Sequence of writing data bytes into RAM with horizontal addressing (V=0)
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ST7576
Page Address Dat
D3 D2 D1 D0 a
MX
Column
address
D0
64
0
5F
S6
1
60
S5
D0
61
S4
Regardless of the display
start line address,
1/65duty => 64th line,
LCD
Out
62
S3
65
63
S2
00
64
S1
COM64
S101
65
S0
COM Output
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
Page
8
D0
63
0
01
0
S100
0
62
1
Page
7
02
1
S99
1
61
1
03
0
Page
6
S98
0
60
1
04
1
S97
0
Page
5
5F
1
05
0
S96
1
5E
0
Page
4
06
0
S95
0
5D
1
07
0
Page
3
08
1
S94
1
S93
0
08
0
Page
2
07
0
5D
1
S8
0
06
0
Page
1
5E
1
S7
0
05
0
04
0
When the common
output is normal
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page
0
03
0
02
0
01
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
00
0
Line
Address
Fig.16 Display Data RAM Map (66 COM)
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ST7576
Partial Display on LCD
The ST7576 realizes the Partial Display function on LCD with low-duty driving for saving power consumption and showing
the various display duty. To show the various display duty on LCD, LCD driving duty and bias are programmable via the
instruction. And, built-in power supply circuits are controlled by the instruction for adjusting the LCD driving voltages.
Fig 17 Reference Example for Partial Display
Fig 18 Partial Display (Partial Display Duty=17, initial COM0=0)
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ST7576
-COM0
-COM1
-COM2
-COM3
-COM4
-COM5
-COM6
-COM7
-COM8
-COM9
-COM10
-COM11
-COM12
-COM13
-COM14
-COM15
-COM16
-COM17
-COM18
-COM19
-COM20
-COM21
-COM22
-COM23
Fig 19 Moving Display (Partial Display Duty=17, Initial COM0=8)
Liquid Crystal Driver Power Circuit
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power
consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage
follower circuits. They are controlled by power control instruction.
External Power Components
Fig 20 Power Circuit
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ST7576
7. RESET CIRCUIT
Setting RESB to “L” or Reset instruction can initialize internal function.
When RESB becomes “L”, following procedure is occurred.
Page address: 0
Column address: 0
Display control: Display blank
COM Scan Direction MY: 0
SEG Select Direction MX: 0
DO=0
Oscillator: OFF
Power down mode (PD = 1)
normal instruction set (H[1:0] = 00)
Display blank (E = D = 0)
Address counter X [6:0] = 0, Y [3:0] = 0
Bias system: depend on Hardware (BR) setting
Booster stage: depend on Hardware (CP) setting
V0 is equal to 0; the HV generator is switched off (VOP [6:0] = 0)
After power-on, RAM data are undefined
While RESB is “L” or reset instruction is executed, no instruction except read status can be accepted. Reset
status appears at D0. After D0 becomes ”L”, any instruction can be accepted. RESB must be connected to the
reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESB is
essential before used.
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ST7576
8. INSTRUCTION TABLE
INSTRUCTION
A0
WR
(R/W)
COMMAND BYTE
DESCRIPTION
D7
D6
D5
D4
D3
D2
D1
D0
H=0 or 1
NOP
0
0
0
0
0
0
0
0
0
0
No operation
Function set
0
0
0
0
1
0
0
PD
V
H
Power-down; entry mode;
Partial screen mode 0
0
0
0
1
0
1
X
X
PS
Partial screen enable
Display part
0
0
0
0
1
1
1
DP2
DP1
DP0
Set display part for partial
screen mode
Write data
1
0
D7
D6
D5
D4
D3
D2
D1
D0
A0
WR
(R/W)
D0
INSTRUCTION
Write data to RAM
COMMAND BYTE
DESCRIPTION
D7
D6
D5
D4
D3
D2
D1
H=0
Set VLCD range
Display control
Set Y address of
RAM
Set X address of
RAM
H=1
Reserved
Reserved
Bias system
Reserved
Set VOP
Ver 1.0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
D
0
E
0
0
0
1
0
0
Y3
Y2
Y1
Y0
0
0
1
X6
X5
X4
X3
X2
X1
X0
Sets Y address of RAM
0≦Y≦9
Sets X address of RAM
0≦X≦101
0
0
0
0
0
0
0
0
0
X
Do not use
0
0
0
0
0
0
0
0
1
X
Do not use
0
0
0
0
0
1
0
BS2
BS1
BS0
0
0
0
1
X
X
X
X
X
X
0
0
1
VOP6
VOP5
VOP4
VOP3
VOP2
VOP1
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PRS VLCD range L/H select
Sets display configuration
Sets bias system (BSx)
Do not use(reserved for test)
VOP0 Write VOP to register
2007/01/29
ST7576
9. INSTRUCTION DESCRIPTION
Function Set
A0
0
Flag
PD
H
D7
0
WR(R/W)
0
D6
0
D5
1
D4
0
D3
0
D2
PD
D1
V
D0
H
Description
PD=0:chip is active
PD=1:chip is in power down mode
All LCD outputs at VSS (display off), bias generator and V0 generator off, VOUT can be
disconnected, oscillator off (external clock possible), RAM contents not cleared; RAM data
can be written.
H are used to select different instruction block
Follow the instruction table
Partial screen mode
A0
0
Flag
PS
D7
0
WR(R/W)
0
D5
1
D4
0
D3
1
D2
X
D1
X
D0
PS
D3
1
D2
DP2
D1
DP1
D0
DP0
Description
Full display mode or partial screen mode selection
PS=0: Full display mode with MUX 1:66
PS=1: Partial screen mode with MUX 1:17
Display part
A0
WR(R/W)
0
0
D7
0
Flag
DP2 DP1 DP0
Ver 1.0
D6
0
D6
0
D5
1
Status
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
D4
1
Description
Display common
DDRAM position
Start from common 0
Start from page 0
Start from common 8
Start from page 1
Start from common 16
Start from page 2
Start from common 24
Start from page 3
Start from common 32
Start from page 4
Start from common 40
Start from page 5
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ST7576
Read data
8-bit data of Display Data from the RAM location specified by the column address and page address can be read to the
microprocessor.
D7
D6
D5
D4
D3
D2
D1
D0
A0
WR(R/W)
1
1
Read data
Write data
8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and
page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data
to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written.
A0
1
D5
D4
D3
Write data
D2
D1
D0
D5
0
D4
1
D3
0
D2
0
D1
0
D0
PRS
D5
0
D4
0
D3
1
D2
D
D1
0
D0
E
Y [3:0] defines the Y address vector address of the display RAM.
A0
WR(R/W)
D7
D6
D5
D4
D3
0
0
0
1
0
0
Y3
D2
Y2
D1
Y1
D0
Y0
WR(R/W)
D7
D6
0
H=”0”
Set VOP range
VOP range L/H select
A0
WR(R/W)
D7
D6
0
0
0
0
PRS=0: VOP programming range LOW
PRS=1: VOP programming range HIGH
Display Control
This bits D and E selects the display mode.
A0
0
Flag
D,E
WR(R/W)
0
D7
0
D6
0
Description
D E The bits D and E select the display mode.
0 0 Display blank
1 0 Normal display
0 1 All display segments on
1 1 Inverse video mode
Set Y address of RAM
Y3
0
0
0
0
0
0
0
0
1
1
Y2
0
0
0
0
1
1
1
1
0
0
Ver 1.0
Y1
0
0
1
1
0
0
1
1
0
0
Y0
0
1
0
1
0
1
0
1
0
1
CONTENT
Page0 (display RAM)
Page1 (display RAM)
Page2 (display RAM)
Page3 (display RAM)
Page4 (display RAM)
Page5 (display RAM)
Page6 (display RAM)
Page7 (display RAM)
Page8 (display RAM)
Page9 (display RAM)
ALLOWED X-RANGE
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
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ST7576
Set X address of RAM
The X address points to the columns. The range of X is 0…101.
D7
D6
D5
D4
A0
WR(R/W)
0
0
1
X6
X5
X4
X6
0
0
0
0
:
1
1
1
1
X5
0
0
0
0
:
1
1
1
1
X4
0
0
0
0
:
0
0
0
0
X3
0
0
0
0
:
0
0
0
0
X2
0
0
0
0
:
0
0
1
1
X1
0
0
1
1
:
1
1
0
0
D3
X3
X0
0
1
0
1
:
0
1
0
1
D2
X2
D1
X1
D0
X0
Column address
0
1
2
3
:
98
99
100
101
H=”1”
System Bias
Select LCD bias ratio of the voltage required for driving the LCD.
A0
WR(R/W)
D7
D6
D5
D4
D3
0
0
0
0
0
1
0
BS2
BS1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
LCD bias voltage
Symbol
V0
V3
V4
VGND
XV0
BS0
0
1
0
1
0
1
0
1
Bias
11
10
9
8
7
6
5
4
D2
BS2
D1
BS1
D0
BS0
D1
VOP1
D0
VOP0
Recommend Duty
1:100
1:81
1:65/1:68
1:49
1/40:1/36
1/24
1:18/1:16
1:10/1:9/1:8
Bias voltage for 1/9 bias
V0
2/9 X V0
2/9 X V0
VSS
-V0
Set VO value
A0
WR(R/W)
D7
D6
D5
0
0
1
VOP6
VOP5
The operation voltage VLCD can be set by software.
D4
VOP4
D3
VOP3
VOP=( a + VOPוb )
Ver 1.0
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D2
VOP2
(1)
2007/01/29
ST7576
The maximum voltage that can be generated is depending on the VDD1 voltage and the display load current. Two
overlapping VLCD ranges are selectable via the command “Booster control”. For the LOW (PRS=0) range a=a1 and for
the HIGH (PRS=1) range a=a2 with steps equal to “b” in both ranges. Note that the charge pump is turned off if VOP
[6;0] and the bit PRS are all set to zero
* The Vop must be operated in the range of 4V to 9.5V for the normal or partial display mode application, so that
customer have some range(<4V; >9.5V) to adjust contrast by themselves.
Table 4 Typical values for parameter for the HV-Generator programming
SYMBOL
VALUE
UNIT
a1
2.94(PRS=0)
V
a2
6.75(PRS=1)
V
b
0.03
V
Charge pump off
VL2
00
b
a2
a1+b
01
02
03
04
05
06 ..... 7D 7E
7F
00
01
02
03
LOW(PRS=0)
04
05
06 ..... 7D 7E
7F
HIGH(PRS=1)
VOP [6:0](programmed) {00 hex… 7F hex}
Fig21 VOP programming of ST7576
Ver 1.0
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10. COMMAND DESCRIPTION
Referential Instruction Setup Flow: Initializing with the built-in Power Supply Circuits
User System Setup by External Pins
Start of Initialization
Power ON(VDD-VSS) Keeping the /RESB
Pin="L"
Waiting for Stabilizing the Power
Release the reset state. (/RESB pin="H")
Waiting reset circuit stablized(>1ms)
Function set PD=0 ,V=0 , H=1
SET Bias system
SET V0
Function set PD=0 , V=0 , H=0
Set VLCD Range(PRS)
Display control D=1 E=0 (Normal)
Set X , Y address
End of Initialization
Fig 22 Initializing with the Built-in Power Supply Circuits
Ver 1.0
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11. LIMITING VALUES
In accordance with the Absolute Maximum Rating System; see notes 1 and 2.
Parameter
Symbol
Conditions
Unit
Power Supply Voltage
VDD1
-0.3 ~ 3.6
V
Power supply voltage
VDD2
-0.3 ~ 3.6
V
LCD Power supply voltage
V0
-0.3~15
V
LCD Power supply voltage
XV0-VG
-15~0.3
V
LCD Power driving voltage
VG, VM
-0.3 ~ VDD2
V
Operating temperature
TOPR
–30 to +85
°C
Storage temperature
TSTR
–65 to +150
°C
Fig 23
Notes
1. Stresses above those listed under Limiting Values may cause permanent damage to the device.
2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to
VSS unless otherwise noted.
3. Insure that the voltage levels of VG, VM, VSS, and XV0 are always such that
V0 ≧VDD2≧ VG > VM > VSS ≧ XV0
Ver 1.0
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12. HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS devices”).
13. DC CHARACTERISTICS
VDD1 = 1.8V to 3.3V; VSS = 0V; Tamb = -30℃ to +85℃; unless otherwise specified.
Item
Symbol Condition
Operating Voltage (1)
VDD1
Operating Voltage (2)
VDD2
High-level Input Voltage
Rating
Units
Applicable
Pin
Min.
Typ. Max.
1.8
—
3.3
V
VDD1
2.4
—
3.3
V
VDD2
VIHC
0.7 x VDD1
—
VDD1
V
Low-level Input Voltage
VILC
VSS
—
0.3 x VDD1
V
High-level Output Voltage
VOHC
IOUT=1mA; VDD1=1.8V
0.8 x VDD1
—
VDD1
V
Low-level Output Voltage
VOLC
IOUT=1mA; VDD1=1.8V
VSS
—
0.2 x VDD1
V
Input leakage current
ILI
–1.0
—
1.0
μA
Output leakage current
ILO
–3.0
—
3.0
μA
—
0.7
—
(Relative to VSS)
Vop= 9.0 V
Liquid Crystal Driver ON
Resistance
RON
Ta = 25°C
ΔV=0.9V
VG = 2.0 V
ΔV=0.2V
Frame frequency
Internal Power
Item
Positive power for
common driver
Negative power for
common driver
FR
FR default (1,0,0)
Symbol
Condition
V0
XV0
KΩ
—
0.7
—
71
75
79
Rating
COMn
SEGn
Hz
Units Applicable Pin
Min.
Typ.
Max.
(V0-XV0)
3
—
12
V
V0
(XV0-V0)
-3
—
-12
V
XV0
*Recommand: LCD Vop range is 4V-9.5V
Ver 1.0
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ST7576
Dynamic consumption current: During Display, with Internal Power Supply ON, current consumed by whole IC (bare die).
Test pattern
Symbol
ISS
(static)
Power Down
(dynamic,
4-SPI)
Ver 1.0
Typ.
Max.
—
110
150
uA
—
0.7
10
uA
Notes
Booster X5
V0 – VSS = 9.0 V
Bias=1/9
ISS
Ta = 25°C
VDD = 3.0 V,
Display Pattern
SNOW
Units
Min.
VDD = 3.0 V,
Display Pattern
SNOW
Rating
Condition
Booster X5
ISS
V0 – VSS = 9.0 V
—
uA
Bias=1/9
Data write frequency: 1M Hz
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ST7576
14. TIMING CHARACTERISTICS
System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
(VDD = 3.3V , Ta =-30~85°C)
Item
Address hold time
Address setup time
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
Signal
A0
WR
WR
RD
WRITE Data setup time
WRITE Data hold time
READ access time
READ Output disable time
Ver 1.0
D0 to D7
Symbol
Condition
Rating
Min.
Max.
tAH8
10
—
tAW8
80
—
tCYC8
350
—
tCCLW
70
—
tCCHW
50
—
tCCLR
120
—
tCCHR
50
tDS8
60
—
tDH8
10
—
tACC8
CL = 100 pF
—
70
tOH8
CL = 100 pF
10
50
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Units
ns
2007/01/29
ST7576
(VDD = 2.8V , Ta =-30~85°C)
Item
Address hold time
Address setup time
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
Signal
A0
WR
WR
RD
WRITE Data setup time
WRITE Address hold time
READ access time
D0 to D7
READ Output disable time
Symbol
Condition
Rating
Min.
Max.
tAH8
15
—
tAW8
120
—
tCYC8
450
—
tCCLW
120
—
tCCHW
100
—
tCCLR
120
—
tCCHR
100
—
tDS8
90
—
tDH8
15
—
tACC8
CL = 100 pF
—
140
tOH8
CL = 100 pF
10
100
Units
ns
(VDD = 1.8V , Ta =-30~85°C)
Item
Address hold time
Address setup time
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
Signal
A0
WR
WR
RD
WRITE Data setup time
WRITE Address hold time
READ access time
READ Output disable time
D0 to D7
Symbol
Condition
Rating
Min.
Max.
tAH8
30
—
tAW8
150
—
tCYC8
550
—
tCCLW
170
—
tCCHW
150
—
tCCLR
170
—
tCCHR
150
tDS8
120
—
tDH8
30
—
tACC8
CL = 100 pF
—
240
tOH8
CL = 100 pF
10
200
Units
ns
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.
*2 All timing is specified using 20% and 80% of VDD1 as the reference.
*3 tCCLW and tCCLR are specified as the overlap between CSB being “L” and WR and RD being at the “L” level.
Ver 1.0
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ST7576
System Bus Read/Write Characteristics 1 (For the 6800 Series MPU)
(VDD = 3.3V , Ta =-30~85°C)
Item
Signal
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WR
RD
WRITE Data setup time
WRITE Data hold time
READ access time
READ Output disable time
Ver 1.0
D0 to D7
Symbol
Condition
Rating
Min.
Max.
tAH6
10
—
tAW6
80
—
tCYC6
240
—
tEWLW
70
—
tEWHW
50
—
tEWLR
70
—
tEWHR
130
tDS6
60
—
tDH6
10
—
tACC6
CL = 100 pF
—
70
tOH6
CL = 100 pF
10
50
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Units
ns
2007/01/29
ST7576
(VDD = 2.8V , Ta =-30~85°C)
Item
Signal
Address hold time
A0
Address setup time
System cycle time
Enable L pulse width (WRITE)
WR
Enable H pulse width (WRITE)
Enable L pulse width (READ)
RD
Enable H pulse width (READ)
WRITE Data setup time
WRITE Address hold time
READ access time
D0 to D7
READ Output disable time
Symbol
Rating
Condition
Min.
Max.
tAH6
15
—
tAW6
100
—
tCYC6
340
—
tEWLW
120
—
tEWHW
100
—
tEWLR
120
—
tEWHR
100
—
tDS6
120
—
tDH6
15
—
tACC6
CL = 100 pF
—
140
tOH6
CL = 100 pF
10
100
Units
ns
(VDD = 1.8V , Ta =-30~85°C)
Item
Signal
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WR
RD
WRITE Data setup time
WRITE Data hold time
READ access time
READ Output disable time
D0 to D7
Symbol
Condition
Rating
Min.
Max.
tAH6
30
—
tAW6
150
—
tCYC6
440
—
tEWLW
170
—
tEWHW
150
—
tEWLR
170
—
tEWHR
150
—
tDS6
180
—
tDH6
30
—
tACC6
CL = 100 pF
—
240
tOH6
CL = 100 pF
10
200
Units
ns
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified.
*2 All timing is specified using 20% and 80% of VDD1 as the reference.
*3 tEWLW and tEWLR are specified as the overlap between CSB being “L” and E.
Ver 1.0
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ST7576
SERIAL INTERFACE(4-Line Interface)
(VDD = 3.3V , Ta =-30~85°C)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
A0
SI
Data hold time
CS-SCL time
CSB
CS-SCL time
Symbol
Condition
Rating
Min.
Max.
tSCYC
120
—
tSHW
60
—
tSLW
60
—
tSAS
20
—
tSAH
90
—
tSDS
20
—
tSDH
10
—
tCSS
20
—
tCSH
120
—
Units
ns
(VDD = 2.8V , Ta =-30~85°C)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
CS-SCL time
Ver 1.0
A0
SI
CSB
Symbol
Condition
Rating
Min.
Max.
tSCYC
200
—
tSHW
100
—
tSLW
100
—
tSAS
30
—
tSAH
120
—
tSDS
30
—
tSDH
20
—
tCSS
30
—
tCSH
150
—
43/54
Units
ns
2007/01/29
ST7576
(VDD=1.8V,Ta=-30~85℃)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
CS-SCL time
A0
SI
CSB
Symbol
Condition
Rating
Min.
Max.
tSCYC
280
—
tSHW
140
—
tSLW
140
—
tSAS
50
—
tSAH
150
—
tSDS
50
—
tSDH
50
—
tCSS
40
—
tCSH
180
—
Units
ns
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD1 as the standard.
Ver 1.0
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ST7576
SERIAL INTERFACE (3-Line Interface)
First bit
Last bit
(VDD=3.3V,Ta=-30~85℃)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Data setup time
SI
Data hold time
CS-SCL time
CSB
CS-SCL time
Symbol
Condition
Rating
Min.
Max.
tSCYC
120
—
tSHW
60
—
tSLW
60
—
tSDS
20
—
tSDH
10
—
tCSS
20
—
tCSH
130
—
Units
ns
(VDD=2.8V,Ta=-30~85℃)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Data setup time
Data hold time
CS-SCL time
CS-SCL time
Ver 1.0
SI
CSB
Symbol
Condition
Rating
Min.
Max.
tSCYC
180
—
tSHW
90
—
tSLW
90
—
tSDS
30
—
tSDH
20
—
tCSS
30
—
tCSH
160
—
45/54
Units
ns
2007/01/29
ST7576
(VDD=1.8V,Ta=-30~85℃)
Item
Signal
Serial Clock Period
SCL
SCL “H” pulse width
SCL “L” pulse width
Data setup time
SI
Data hold time
CS-SCL time
CSB
CS-SCL time
Symbol
Rating
Condition
Min.
Max.
tSCYC
240
—
tSHW
120
—
tSLW
120
—
tSDS
60
—
tSDH
50
—
tCSS
40
—
tCSH
190
—
Units
ns
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD1 as the standard.
SERIAL INTERFACE(I2C Interface)
(VDD=3.3V,Ta=-30~85℃)
Item
Signal Symbol
Rating
Condition
Min.
Max.
Units
SCL clock frequency
SCL
FSCLK
-
400
KHz
SCL clock low period
SCL
TLOW
1.3
-
us
SCL clock high period
SCL
THIGH
0.6
-
us
Data set-up time
SI
TSU;Data
100
-
ns
Data hold time
SI
THD;Data
0
0.9
us
SCL,SDA rise time
SCL
TR
20+0.1Cb 300
ns
SCL,SDA fall time
SCL
TF
20+0.1Cb 300
ns
Cb
-
400
pF
Capacitive load represented by each bus line
Setup time for a repeated START condition
SI
TSU;SUA
0.6
-
us
Start condition hold time
SI
THD;STA
0.6
-
us
Setup time for STOP condition
TSU;STO
0.6
-
us
Tolerable spike width on bus
TSW
-
50
ns
BUS free time between a STOP and START condition SCL
TBUF
1.3
Ver 1.0
46/54
us
2007/01/29
ST7576
15. RESET TIMING
tRW
/RES
tR
Internal
status
During reset
Reset complete
(VDD = 3.3V , Ta = –30 to 85°C )
Item
Signal
Reset time
Reset “L” pulse width
RESB
Symbol
Condition
Rating
Units
Min.
Typ.
Max.
tR
—
—
1.5
us
tRW
1.5
—
—
us
(VDD = 2.8V , Ta = –30 to 85°C )
Item
Signal
Reset time
Reset “L” pulse width
RESB
Symbol
Condition
Rating
Units
Min.
Typ.
Max.
tR
—
—
2.0
us
tRW
2.0
—
—
us
(VDD = 1.8V , Ta = –30 to 85°C )
Item
Signal
Reset time
Reset “L” pulse width
Ver 1.0
RESB
Symbol
Condition
Rating
Units
Min.
Typ.
Max.
tR
—
—
3.0
us
tRW
3.0
—
—
us
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ST7576
APPLICATION NOTE
250 RESERVATIO N
XV0
V0
18
17
Vss
VG
15
16
14
13
12
11
10
D0
D1
D2
D3
D4
D5
D6
D7
VDD
A0
/RD
/WR
CSB
RESB
C=1.0uF
249 RESERVATIO N
244 COM60
243 COMS
FPC SIDE
1 COM59
27 COM33
28 SEG0
129 SEG101
242 XV0S
238~241 XV0I
236~237 XV0O
235 V0S
231~234 V0I
229~230 V0O
228 VGS
224~227 VGI
222~223 VGO
221 T8
220 T7
219 T6
218 T5
217 T0
216 T4
215 T3
214 T2
213 T1
212 VRS
208~211 VSS1
204~207 VSS2
203 OSC
202 D0
201 D1
200 D2
199 D3
198 D4
197 D5
196 D6
195 D7
194 VDD1
193 A0
192 RD
191 WR
190 CSB
189 RESB
185~188 VDD2
181~184 VDD1
180 VSS2
179 VMO
178 VMO
177 VMO
176 PS0
175 PS1
174 PS2
173 TMY
172 TMX
171 CP
170 BR
169 T12
168 T11
167 VSS2
164~166 VDX2
163 COM26
157 COM32
2007/01/29
48/54
Ver 1.0
2 3 4 5 6
7 8 9
1
SYSTEM SIDE
130 COMS
131 COM0
156 COM25
ITO SIDE
......
......
..........................................
.............................................
.............................................
ST7576
1 COM59
27 COM33
28 SEG0
129 SEG101
130 COMS
131 COM0
156 COM25
ITO SIDE
FPC SIDE
17
18
V0
XV0
Vss
VG
15
16
14
13
12
11
10
D0
D1
D2
D3
D4
D5
D6
D7
VDD
A0
/RD
/WR
CSB
RESB
C=1.0uF
250 RESERVATIO N
249 RESERVATIO N
244 COM60
243 COMS
242 XV0S
238~241 XV0I
236~237 XV0O
235 V0S
231~234 V0I
229~230 V0O
228 VGS
224~227 VGI
222~223 VGO
221 T8
220 T7
219 T6
218 T5
217 T0
216 T4
215 T3
214 T2
213 T1
212 VRS
208~211 VSS1
204~207 VSS2
203 OSC
202 D0
201 D1
200 D2
199 D3
198 D4
197 D5
196 D6
195 D7
194 VDD1
193 A0
192 RD
191 WR
190 CSB
189 RESB
185~188 VDD2
181~184 VDD1
180 VSS2
179 VMO
178 VMO
177 VMO
176 PS0
175 PS1
174 PS2
173 TMY
172 TMX
171 CP
170 BR
169 T12
168 T11
167 VSS2
164~166 VDX2
163 COM26
157 COM32
2007/01/29
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Ver 1.0
2 3 4 5 6
7 8 9
1
SYSTEM SIDE
......
......
..........................................
.............................................
.............................................
ST7576
1 COM59
249 RESERVATIO N
250 RESERVATIO N
244 COM60
243 COMS
10
XV0
Vss
V0
CSB
A0
SDA
SCLK
9
RESB
VG
VDD
8
7
27 COM33
202 X
242 XV0S
238~241 XV0I
236~237 XV0O
235 V0S
231~234 V0I
229~230 V0O
228 VGS
224~227 VGI
222~223 VGO
221 T8
220 T7
219 T6
218 T5
217 T0
216 T4
215 T3
214 T2
213 T1
212 VRS
208~211 VSS1
204~207 VSS2
203 OSC
195 SCLK(D7)
201 X
200 X
199 X
198 CSB(D4)
197 A0(D5)
196 SDA(D6)
194 VDD1
193 X
192 RD
191 WR
190 X
189 RESB
185~188 VDD2
181~184 VDD1
180 VSS2
179 VMO
178 VMO
177 VMO
176 PS0
175 PS1
174 PS2
173 TMY
172 TMX
171 CP
170 BR
169 T12
168 T11
167 VSS2
164~166 VDX2
163 COM26
157 COM32
3 4 5 6
28 SEG0
129 SEG101
130 COMS
131 COM0
156 COM25
2
2007/01/29
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Ver 1.0
1
SYSTEM SIDE
......
......
..........................................
.............................................
.............................................
ITO SIDE
FPC SIDE
C=1.0uF
ST7576
1 COM59
27 COM33
28 SEG0
129 SEG101
130 COMS
131 COM0
156 COM25
249 RESERVATIO N
250 RESERVATIO N
244 COM60
243 COMS
202 X
242 XV0S
238~241 XV0I
236~237 XV0O
235 V0S
231~234 V0I
229~230 V0O
228 VGS
224~227 VGI
222~223 VGO
221 T8
220 T7
219 T6
218 T5
217 T0
216 T4
215 T3
214 T2
213 T1
212 VRS
208~211 VSS1
204~207 VSS2
203 OSC
195 SCLK(D7)
201 X
200 X
199 X
198 CSB(D4)
197 X
196 SDA(D6)
194 VDD1
193 X
192 RD
191 WR
190 X
189 RESB
185~188 VDD2
181~184 VDD1
180 VSS2
179 VMO
178 VMO
177 VMO
176 PS0
175 PS1
174 PS2
173 TMY
172 TMX
171 CP
170 BR
169 T12
168 T11
167 VSS2
164~166 VDX2
163 COM26
157 COM32
SDA
SCLK
CSB
Vss
XV0
RESB
V0
VDD
VG
6
2007/01/29
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Ver 1.0
5
9
3 4
8
2
7
1
SYSTEM SIDE
......
......
..........................................
.............................................
.............................................
ITO SIDE
FPC SIDE
C=1.0uF
ST7576
1 COM59
27 COM33
28 SEG0
129 SEG101
130 COMS
131 COM0
156 COM25
249 RESERVATIO N
250 RESERVATIO N
244 COM60
243 COMS
202 SA0(D0)
242 XV0S
238~241 XV0I
236~237 XV0O
235 V0S
231~234 V0I
229~230 V0O
228 VGS
224~227 VGI
222~223 VGO
221 T8
220 T7
219 T6
218 T5
217 T0
216 T4
215 T3
214 T2
213 T1
212 VRS
208~211 VSS1
204~207 VSS2
203 OSC
201 SA1(D1)
200 SDA_OUT(D2)
198 X
197 X
199 SDA_OUT(D3)
195 SCLK(D7)
196 SDA_IN(D6)
194 VDD1
193 X
192 RD
191 WR
190 X
189 RESB
185~188 VDD2
181~184 VDD1
180 VSS2
179 VMO
178 VMO
177 VMO
176 PS0
175 PS1
174 PS2
173 TMY
172 TMX
171 CP
170 BR
169 T12
168 T11
167 VSS2
164~166 VDX2
163 COM26
157 COM32
Vss
XV0
SDA
SCLK
V0
RESB
VG
VDD
2007/01/29
52/54
Ver 1.0
6
9
3 4
8
2
7
1
SYSTEM SIDE
......
......
..........................................
.............................................
.............................................
ITO SIDE
FPC SIDE
C=1.0uF
ST7576
Reference to ITO Layout
XV0I
XV0O
VGS
VGI
VGO
VDD1
VDD2
XV0S
V0O
V0I
V0S
VSS1
VSS2
Ver 1.0
53/54
2007/01/29
ST7576
ST7576 Serial Specification Revision History
Version
Date
Description
1 All layer change
0.6a
2006/05/10
2 Fig arrange
3 Add reference to ITO layout
4 Test pin size is reduced
0.6b
2006/05/24 P11
0.6c
2006/06/01 To remove the capacitor between V0 and XV0
0.6d
2006/06/19 Modify function set
P1 : Voltage converter ; display supply voltage range
P16: VSS1, VSS2
0.7a
2006/08/14 P17: Mode0, Mode1=>T11,T12
P34 : limit Vop application range
P36-P47: take off TBD
Remove external V0
0.7b
2006/10/05
0.7c
2006/12/15 Modify P3
Modify P37 DC characteristic
Modify display supply voltage range at P1
Modify VDX2O pin description at P16
1.0
2007/01/25
Modify TEN to X in instruction table at P30
Modify V0, XV0 limit value to 15V at P36
Modify Max value of internal of DC characteristic at P37
Ver 1.0
54/54
2007/01/29