UTC-IC 75323L-S20-T

UNISONIC TECHNOLOGIES CO., LTD
75323
LINEAR INTEGRATED CIRCUIT
MULTIPLE RS-232 DRIVERS
AND RECEIVERS
„
DESCRIPTION
The UTC 75323 provides a rugged, low-cost effectiveness
performance due to the circuits consisting of bipolar ones,
incorporating five drivers and three receivers. It is characterized
with less required external components, board spaces and an easy
interface between UART and serial-port connector for a single chip.
Working at temperatures from 0℃ to 70℃ is one of its features.
„
FEATURES
* Single chip with easy interface between UART and serial-port
connector
* Data rates : 20 kb/s.
* Complement to the UTC 75232.
„
ORDERING INFORMATION
Ordering Number
Lead Free
Halogen Free
75323L-S20-R
75323G-S20-R
75323L-S20-T
75323G-S20-T
75323L-D20-T
75323G-D20-T
www.unisonic.com.tw
Copyright © 2012 Unisonic Technologies Co., Ltd
Package
Packing
SOP-20
SOP-20
DIP-20
Tape Reel
Tube
Tube
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QW-R113-007,B
75323
„
„
LINEAR INTEGRATED CIRCUIT
PIN CONFIGURATION
VCC
1
20
VDD
1DA
2
19
1DY
2DA
3
18
2DY
2DA
4
17
3DY
1RY
5
16
1RA
2RY
6
15
2RA
4DA
7
14
4DY
3RY
8
13
3RA
5DA
9
12
5DY
GND
10
11
VSS
PIN DESCRIPTION
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIN NAME
VCC
1DA
2DA
3DA
1RY
2RY
4DA
3RY
5DA
GND
VSS
5DY
3RA
4DY
2RA
1RA
3DY
2DY
1DY
VDD
DESCRIPTION
Supply Voltage of receiver
Input of driver 1
Input of driver 2
Input of driver 3
Output of receiver 1
Output of receiver 2
Input of driver 4
Output of receiver 3
Input of driver 5
Ground
Negative Supply Voltage of driver
Output of driver 5
Input of receiver 3
Output of driver 4
Input of receiver 2
Input of receiver 1
Output of driver 3
Output of driver 2
Output of driver 1
Positive Supply Voltage of driver
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LINEAR INTEGRATED CIRCUIT
LOGIC SYMBOL
Note: This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
„
LOGIC DIAGRAM ( POSITIVE LOGIC )
„
BLOCK DIAGRAM
The circuit for each driver
VDD
11.6kΩ
9.4kΩ
Input DA
75.8Ω
320Ω
Output DY
254.5Ω
4.2kΩ
GND
0
10.4kΩ
3.3kΩ
68.5Ω
VSS
Resistor values shown are nominal.
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LINEAR INTEGRATED CIRCUIT
BLOCK DIAGRAM(Cont.)
The circuit for each receiver
VCC
5kΩ
9kΩ
1.66kΩ
Output RY
Input RA
3.8kΩ
2kΩ
10kΩ
GND
0
Resistor values shown are nominal
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LINEAR INTEGRATED CIRCUIT
ABSOLUTE MAXIMUM RATING (TA=25℃, unless otherwise specified)
PARAMETER
Supply Voltage (Note 2)
Supply Voltage (Note 2)
Supply Voltage (Note 2)
RATINGS
UNIT
10
V
15
V
-15
V
Driver
-15 ~ 7
V
Input Voltage
VI
Receiver
-30 ~ 30
Output Voltage (Driver)
Vo
-15 ~ 15
V
Low-level Output Current (Receiver)
IOL
20
mA
Storage temperature
TSTG
-65 ~ 150
°C
Note: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
2. All voltages are with respect to the network ground terminal.
„
SYMBOL
VCC
VDD
VSS
THERMAL DATA
PARAMETER
Junction to Ambient
„
SYMBOL
SOP-20
DIP-20
θJA
UNIT
°С/W
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
High-Level Input Voltage
Low-Level Input Voltage
Driver
Driver
Driver
High-Level Output Current
Receiver
Driver
High-Level Output Current
Receiver
Operating Free-Air Temperature
„
RATINGS
97
67
SYMBOL
VDD
VSS
VCC
VIH
VIL
MIN
7.5
-7.5
4.5
1.9
TYP
9
-9
5
IOH
IOL
TA
0
MAX
13.5
-13.5
5.5
UNIT
V
V
V
0.8
-6
-0.5
6
16
70
mA
mA
℃
SUPPLY CURRENTS OVER OPERATING FREE-AIR TEMPERATURE RANGE
PARAMETER
Supply Current From VDD
Supply Current From VSS
Supply Current From VCC
SYMBOL
IDD
ISS
ICC
TEST CONDITIONS
VDD=9V, VSS=-9V
All inputs at 1.9V, No load
VDD=12V, VSS=-12V
VDD=9V, VSS=-9V
All inputs at 0.8V, No load
VDD=12V, VSS=-12V
VDD=9V, VSS=-9V
All inputs at 1.9V, No load
VDD=12V, VSS=-12V
VDD=9V, VSS=-9V
All inputs at 0.8V, No load
VDD=12V, VSS=-12V
VCC=5V, All inputs at 5V, No load
UNISONIC TECHNOLOGIES CO., LTD
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MIN
MAX
25
32
7.5
9.5
-25
-32
-5.3
-5.3
20
UNIT
mA
mA
mA
mA
mA
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LINEAR INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS OVER OPERATING FREE-AIR TEMPERATURE
RANGE (VDD=9V, VSS=-9V, VCC=5V , unless otherwise specified)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP MAX UNIT
High-Level Output Voltage
VOH
VIL=0.8V, RL=3kΩ (Fig. 1)
6
7.5
V
Low-Level Output Voltage(see Note 1)
VOL
VIH=1.9V, RL=3kΩ (Fig. 1)
-7.5
-6
V
High-Level Input Current
IIH
VI=5V (Fig. 2)
10
μA
Low-Level Input Current
IIL
VI=0 (Fig. 2)
-1.6
mA
High-Level Short-Circuit Output Current
IOS(H) VIL=0.8V,Vo=0 (Fig. 1, Note 2) -4.5
-9
-19.5 mA
Low-Level Short-Circuit Output Current
IOS(L) VIH=2V, Vo=0 (Fig. 1)
4.5
9
19
mA
Output Resistance (Note 3)
rO
VCC=VDD=VSS=0, Vo=-2V ~ 2V 300
Ω
Note: 1. The algebraic convention, where the more positive(less negative) limit is designated as maximum, is used in
this data sheet for logic levels only, e. g.,if-10V is maximum, the typical value is a more negative voltage.
2. Output short-circuit conditions must maintain the total power dissipation below absolute maximum ratings.
3. Test conditions are those specified by TIA/EIA-232-F and as listed above.
„
SWITCHING CHARACTERISTICS (TA=25℃, VDD=12V, VSS=-12V, VCC=5V±10%)
PARAMETER
Propagation Delay Time, Low- to
High-Level Output
Propagation Delay Time, High-to
Low-Level Output
SYMBOL
tPLH
tPHL
TEST CONDITIONS
RL=3kΩ ~ 7kΩ, CL=15pF
(Fig. 3)
MIN
TYP
MAX
315
500
75
175
UNIT
ns
RL=3kΩ~7kΩ, CL=15pF(Fig. 3)
60
100
ns
tTLH
RL=3kΩ ~ 7kΩ, CL=2500pF
1.7
2.5
μs
(Fig. 3, Note 1)
RL=3kΩ~7kΩ, CL=15pF(Fig. 3)
40
75
ns
Transition Time, High-to Low-Level Output
tTHL
RL=3kΩ ~ 7kΩ, CL=2500pF
1.5
2.5
μs
(Fig. 3, Note 2)
Note: 1. Measured between-3-V and 3-V points of the output waveform (TIA/EIA-232-F conditions), all unused
inputs are tied either high or low.
2. Measured between 3-V and -3-V points of the output waveform (TIA/EIA-232-F conditions), all unused
inputs are tied either high or low
tTLH Transition Time, Low-to High-Level
Output
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LINEAR INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
CONDITIONS (unless otherwise specified)
PARAMETER
SYMBOL
Positive-Going Input Threshold Voltage
VIT+
Negative-Going Input Threshold Voltage
Input Hysteresis Voltage(VIT+ - VIT-)
VITVHYS
TEST CONDITIONS
TA=25℃
Fig.5
TA=0℃ ~ 70℃
Fig. 5
VIH=0.75V
Inputs open
Low-Level Output Voltage
VOL
IOL=10mA, VI=3V
VI=25V
High-Level Input Current
IIH
VI=3V
VI=-25V
Low-Level Input Current
IIL
VI=-3V
Short-Circuit Output Current
IOS
Fig. 4
Note: All typical values are at TA=25℃, VCC=5V, VDD=9V, VSS=-9V
High-Level Output Voltage
„
VOH
IOH=-0.5mA
MIN
1.75
1.55
0.75
0.5
2.6
2.6
TYP
1.9
0.97
MAX
2.3
2.3
1.25
4
5
0.2
0.45
8.3
3.6
0.43
-3.6
-0.43
-8.3
-3.4
-12
UNIT
V
V
V
mA
mA
mA
mA
mA
SWITCHING CHARACTERISTICS (TA=25℃, VCC=5V, VDD=12V, VSS= -12V)
PARAMETER
Propagation Delay Time, Low-to High-Level Output
Propagation Delay Time, High- to Low-Level Output
Transition Time, Low-to High-Level Output
Transition time, High- to Low-Level Output
UNISONIC TECHNOLOGIES CO., LTD
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SYMBOL TEST CONDITIONS MIN
tPLH
tPHL
CL=50pF, RL=5kΩ
Fig. 6
tTLH
tTHL
TYP
107
42
175
16
MAX UNIT
500
ns
150
ns
525
ns
60
ns
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LINEAR INTEGRATED CIRCUIT
PARAMETER MEASUREMENT INFORMATION
IOS(L)
VDD
Vcc
VDD or GND
-IOS(H)
VSS or GND
VI
VO
RL=3kΩ
VSS
Fig. 1 Driver Test Circuit for VOH, VOL, IOS(H), IOS(L)
Fig. 2 Driver Test Circuit for IIH and IIL
Fig.3 Driver Test Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics(tW=25μs,PRR=20kHz,ZO=50Ω,tR=tF<50ns)
VDD
VCC
-IOS
VSS
Fig.4 Receiver Test Circuit for Ios
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LINEAR INTEGRATED CIRCUIT
PARAMETER MEASUREMENT INFORMATION(Cont.)
VDD
VCC
-IOH
VIT, VIN
VOH
VOL
IOL
VSS
Fig. 5 Receiver Test Circuit for VIT ,VOH, and VOL
Fig. 6 Receive Propagation and Transition Times
Notes: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics(tW=25μs,PRR=20kHz,ZO=50Ω,tR=tF<50ns)
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LINEAR INTEGRATED CIRCUIT
APPLICATION INFORMATION
Diodes placed in series with the VDD and VSS leads protect the UTC 75323 in the fault condition in which the
device output are shorted to VDD or VSS, and the Power supplies are at low and provide low-impedance paths to
ground (see Figure7)
VDD
VDD
Output
UTC ±15V
UTC
75323
75323
VSS
VSS
Fig. 7 Power-Supply Protection to Meet Power-Off Fault Condition of TIA/EIA-232-F
-12V
TL16C450
ACE
RI
DTR
TIA/EIA-232-F
DB9S
CONNECTOR
10 GND
9
5DA
8
3RY
7
4DA
6
2RY
5
1RY
4
3DA
3
2DA
2
1DA
1
Vcc
43
37
40
CTS
13
SO
36
RTS
11
SI
41
DSR
42
DCD
VSS
UTC
75323
5DY
3RA
4DY
2RA
1RA
3DY
2DY
11
12
13
14
15
16
17
18
19
1DY
20
VDD
5
RI
DTR
CTS
TX
RTS
RX
DSR
9
C5*
C4*
6
C3*
DCD C2*
12V
C1*
1
5V
Fig. 8 Typical Connection
*See Figure Slew Rate vs. Load Capacitance to select the correct values for the loading capacitors (C1, C2, C3, C4
and C5), which may be required to meet the RS-232 maximum slew-rate requirement of 30V/us. The value of the
loading capacitors resrequired depends upon the line length and desired slew rate, but is typically 330pF.
Note C: To use the receivers only, VDD and Vss both must be powered or tied to ground.
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TYPICAL CHARACTERISTICS
„
Output Voltage , Vo (V)
Shourt-Circuit Output Current, IOS (mA)
DRIVER SECTION
Slew Rate vs. Load Capacitance
Slew Rate, SR (V/μs)
1000
100
10
1
VDD=9V
VSS=-9V
RL=3kΩ
TA=25°C
1
10
100
1000
10000
Load Capacitance, CL (pF)
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TYPICAL CHARACTERISTICS(Cont.)
„
Input Threshold Voltage, VIT (V)
Input Threshold Voltage, VIT (V)
RECEIVER SECTION
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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