1021BV33 WCFS1016V1C 64K x 16 Static RAM Features • 3.3V operation (3.0V–3.6V) • High speed — tAA = 12 ns • CMOS for optimum speed/power • Automatic power-down when deselected • Independent control of upper and lower bits • Available in 400-mil SOJ through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Functional Description Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The WCFS1016V1C is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 The WCFS1016V1C is available in 400-mil-wide SOJ packages. Logic Block Diagram Pin Configurations SOJ Top View 64K x 16 RAM Array 512 X 2048 SENSE AMPS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC I/O1 – I/O8 I/O9 – I/O16 A8 A9 A10 A11 A12 A13 A14 A15 COLUMN DECODER BHE WE CE OE BLE 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC Selection Guide WCFS1016V1C-12 Maximum Access Time (ns) 12 Maximum Operating Current (mA) 150 Maximum CMOS Standby Current (mA) 5 Revised April 19, 2002 WCFS1016V1C Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[1] ......................................–0.5V to VCC+0.5V Range Commercial Ambient Temperature[2] VCC 0°C to +70°C 3.3V ± 10% DC Input Voltage[1]...................................–0.5V to VCC+0.5V Electrical Characteristics Over the Operating Range Test Conditions Parameter Description WCFS1016V1C 12ns Min. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage[1] IIX Input Load Current IOZ Max. Unit 2.4 V 0.4 V 2.2 VCC+ 0.3V V –0.3 0.8 V GND < VI < VCC –1 +1 µA Output Leakage Current GND < VI < VCC, Output Disabled –1 +1 µA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 150 mA ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX 40 mA ISB2 Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f=0 5 mA Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz Max. Unit 6 pF 8 pF Note: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “instant on” case temperature. 3. Tested initially and after any design or process changes that may affect these parameters. Page 2 of 9 WCFS1016V1C AC Test Loads and Waveforms R 317 Ω R 317 Ω 3.3V 3.3V OUTPUT 90% OUTPUT 30 pF R2 351Ω INCLUDING JIG AND SCOPE (a) R2 351Ω 5 pF INCLUDING JIG AND SCOPE 167 OUTPUT Equivalent to: THÉVENIN EQUIVALENT ALL INPUT PULSES 3.0V GND Rise Time: 1 V/ns (b) 10% 90% 10% Fall Time: 1 V/ns 1.73V 30 pF Page 3 of 9 WCFS1016V1C Switching Characteristics[4] Over the Operating Range WCFS1016V1C 12ns Parameter Description Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid 12 tOHA Data Hold from Address Change tACE CE LOW to Data Valid 12 ns tDOE OE LOW to Data Valid 6 ns tLZOE OE LOW to Low Z 3 0 OE HIGH to High Z tLZCE CE LOW to Low Z[6] ns CE HIGH to High tPU CE LOW to Power-Up tPD CE HIGH to Power-Down tDBE Byte Enable to Data Valid tLZBE Byte Enable to Low Z tHZBE 6 3 ns ns Z[5, 6] tHZCE ns ns [5, 6] tHZOE WRITE ns 12 6 0 ns ns 12 ns 6 ns 0 ns Byte Disable to High Z 6 ns CYCLE[7] tWC Write Cycle Time 12 ns tSCE CE LOW to Write End 9 ns tAW Address Set-Up to Write End 8 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 8 ns tSD Data Set-Up to Write End 6 ns tHD Data Hold from Write End 0 ns tLZWE WE HIGH to Low Z[6] 3 ns Z[5, 6] tHZWE WE LOW to High tBW Byte Enable to End of Write 6 8 ns ns Data Retention Characteristics Over the Operating Range Parameter Description Conditions[8] VDR VCC for Data Retention tCDR[9] tR[10] Chip Deselect to Data Retention Time VCC = VDR = 2.0V, CE > VCC – 0.3V, Operation Recovery Time VIN > VCC – 0.3V or VIN < 0.3V Min. Max. Unit 2.0 V 0 ns tRC ns Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. No input may exceed VCC + 0.5V. 9. Tested initially and after any design or process changes that may affect these parameters. 10. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds. Page 4 of 9 WCFS1016V1C Data Retention Waveform DATA RETENTION MODE 3.0V VCC VDR > 2V 3.0V tR tCDR CE Switching Waveforms Read Cycle No. 1 [11, 12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID Read Cycle No. 2 (OE Controlled) DATA VALID [12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATA VALID tPD tPU 50% IICC CC 50% IISB SB Notes: 11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Page 5 of 9 WCFS1016V1C Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled) [14, 15] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA I/O Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O Notes: 14. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Page 6 of 9 WCFS1016V1C Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Truth Table CE OE H X L L L X WE BLE BHE X X X High Z High Z Power-Down Standby (ISB) H L L Data Out Data Out Read - All bits Active (ICC) L H Data Out High Z Read - Lower bits only Active (ICC) H L High Z Data Out Read - Upper bits only Active (ICC) L L Data In Data In Write - All bits Active (ICC) L H Data In High Z Write - Lower bits only Active (ICC) H L High Z Data In Write - Upper bits only Active (ICC) L I/O1–I/O8 I/O9–I/O16 Mode Power L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) L X X H H High Z High Z Selected, Outputs Disabled Active (ICC) Page 7 of 9 WCFS1016V1C Ordering Information Speed (ns) 12 Ordering Code WCFS1016V1C-JC12 Package Name J Package Type 44-Lead (400-Mil) Molded SOJ Operating Range Commercial Package Diagrams 44-Lead (400-Mil) Molded SOJ J Page 8 of 9 WCFS1016V1C Document Title: WCFS1016V1C 64K x 16 Static RAM REV. Issue Date Orig. of Change Description of Change ** 4/19/02 XFL NEW DATASHEET Page 9 of 9