LM3478 LM3478-Q1 www.ti.com SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 High-Efficiency Low-Side N-Channel Controller for Switching Regulator Check for Samples: LM3478, LM3478-Q1 FEATURES APPLICATIONS • • • • • • 1 2 • • • • • • • LM3478Q in VSSOP-8 package is AEC-Q100 qualified and manufactured on an Automotive Grade Flow 8-lead VSSOP-8 and SOIC-8 packages Internal push-pull driver with 1A peak current capability Current limit and thermal shutdown Frequency compensation optimized with a capacitor and a resistor Internal soft start Current Mode Operation Undervoltage Lockout with hysteresis Distributed Power Systems Battery Chargers Offline Power Supplies Telecom Power Supplies Automotive Power Systems KEY SPECIFICATIONS • • • • Wide supply voltage range of 2.97V to 40V 100kHz to 1MHz Adjustable clock frequency ±2.5% (over temperature) internal reference 10µA shutdown current (over temperature) DESCRIPTION The LM3478 is a versatile Low-Side N-Channel MOSFET controller for switching regulators. It is suitable for use in topologies requiring a low side MOSFET, such as boost, flyback, SEPIC, etc. Moreover, the LM3478 can be operated at extremely high switching frequency in order to reduce the overall solution size. The switching frequency of the LM3478 can be adjusted to any value between 100kHz and 1MHz by using a single external resistor. Current mode control provides superior bandwidth and transient response, besides cycle-by-cycle current limiting. Output current can be programmed with a single external resistor. The LM3478 has built in features such as thermal shutdown, short-circuit protection, over voltage protection, etc. Power saving shutdown mode reduces the total supply current to 5µA and allows power supply sequencing. Internal soft-start limits the inrush current at start-up. Typical Application Circuit Figure 1. Typical High Efficiency Step-Up (Boost) Converter 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2013, Texas Instruments Incorporated LM3478 LM3478-Q1 SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 www.ti.com Connection Diagram Figure 2. 8-Lead VSSOP-8 Package Figure 3. 8-Lead SOIC-8 Package Table 1. Pin Descriptions Pin Name Pin No. ISEN 1 Current sense input pin. Voltage generated across an external sense resistor is fed into this pin. Description COMP 2 Compensation pin. A resistor, capacitor combination connected to this pin provides compensation for the control loop. FB 3 Feedback pin. The output voltage should be adjusted using a resistor divider to provide 1.26V at this pin. AGND 4 Analog ground pin. PGND 5 Power ground pin. DR 6 Drive pin. The gate of the external MOSFET should be connected to this pin. FA/SD 7 Frequency adjust and Shutdown pin. A resistor connected to this pin sets the oscillator frequency. A high level on this pin for longer than 30 µs will turn the device off. The device will then draw less than 10µA from the supply. VIN 8 Power Supply Input pin. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) Input Voltage 45V FB Pin Voltage -0.4V < VFB < 7V FA/SD Pin Voltage -0.4V < VFA/SD < 7V Peak Driver Output Current (<10µs) 1.0A Power Dissipation Internally Limited Storage Temperature Range −65°C to +150°C Junction Temperature ESD Susceptibility Human Body Model +150°C (2) 2kV Lead Temperature Vapor Phase (60 sec.) Infrared (15 sec.) 260°C −0.4V ≤ VDR ≤ 8V DR Pin Voltage ISEN Pin Voltage (1) (2) 500mV Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. Operating Ratings (1) 2.97V ≤ VIN ≤ 40V Supply Voltage −40°C ≤ TJ ≤ +125°C Junction Temperature Range 100kHz ≤ FSW ≤ 1MHz Switching Frequency (1) 2 215°C Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 LM3478 LM3478-Q1 www.ti.com SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 Electrical Characteristics Specifications in Standard type face are for TJ = 25°C, and in bold type face apply over the full Operating Temperature Range. Unless otherwise specified, VIN = 12V, RFA = 40kΩ Symbol VFB Parameter Feedback Voltage Conditions Typical VCOMP = 1.4V, 2.97 ≤ VIN ≤ 40V 1.26 Limit Unit 1.2416/1.228 1.2843/1.292 V V(min) V(max) ΔVLINE Feedback Voltage Line Regulation 2.97 ≤ VIN ≤ 40V 0.001 %/V ΔVLOAD Output Voltage Load Regulation IEAO Source/Sink ±0.5 %/A (max) VUVLO Input Undervoltage Lock-out VUV(HYS) Fnom 2.85 Input Undervoltage Lock-out Hysteresis Nominal Switching Frequency 2.97 V V(max) 130 210 mV mV (min) mV (max) 350 440 kHz kHz(min) kHz(max) 170 RFA = 40KΩ 400 RDS1 (ON) Driver Switch On Resistance (top) IDR = 0.2A, VIN= 5V 16 Ω RDS2 (ON) Driver Switch On Resistance (bottom) IDR = 0.2A 4.5 Ω VDR (max) Maximum Drive Voltage Swing (1) VIN < 7.2V VIN V Dmax Maximum Duty Cycle (2) 100 % Tmin (on) Minimum On Time 325 210 600 nsec nsec(min) nsec(max) 3.3 mA mA (max) 10 µA µA (max) 135/ 125 180/ 190 mV mV (min) mV (max) ISUPPLY IQ VIN ≥ 7.2V 7.2 (3) Supply Current (non-switching) 2.7 (4) Quiescent Current in Shutdown Mode VFA/SD = 5V VIN = 5V Current Sense Threshold Voltage VIN = 5V VSC Short-Circuit Current Limit Sense Voltage VIN = 5V 343 VSL Internal Compensation Ramp Voltage VIN = 5V 92 VSENSE , VSL ratio VSL/VSENSE VOVP Output Over-voltage Protection VCOMP = 1.4V (with respect to feedback voltage) (5) VSSOP Package 5 156 0.49 (1) (2) (3) (4) (5) Output Over-Voltage Protection Hysteresis (5) VCOMP = 1.4V mV mV (min) mV (max) 52 132 mV mV(min) mV(max) 0.30 0.70 (min) (max) 32/ 25 mV mV(min) 50 SOIC Package VOVP(HYS) 250 415 78/ 85 mV(max) 78/100 mV(max) 20 110 mV mV(min) mV(max) 60 The voltage on the drive pin, VDR is equal to the input voltage when input voltage is less than 7.2V. VDR is equal to 7.2V when the input voltage is greater than or equal to 7.2V. The limits for the maximum duty cycle can not be specified since the part does not permit less than 100% maximum duty cycle operation. For this test, the FA/SD pin is pulled to ground using a 40K resistor. For this test, the FA/SD pin is pulled to 5V using a 40K resistor. The over-voltage protection is specified with respect to the feedback voltage. This is because the over-voltage protection tracks the feedback voltage. The overvoltage protection threshold is given by adding the feedback voltage, VFB to the over-voltage protection specification. Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 Submit Documentation Feedback 3 LM3478 LM3478-Q1 SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 www.ti.com Electrical Characteristics (continued) Specifications in Standard type face are for TJ = 25°C, and in bold type face apply over the full Operating Temperature Range. Unless otherwise specified, VIN = 12V, RFA = 40kΩ Symbol Gm AVOL IEAO Parameter Conditions Typical Error Amplifier Transconductance VCOMP = 1.4V IEAO = 100µA (Source/Sink) 800 Error Amplifier Voltage Gain VCOMP = 1.4V IEAO = 100µA (Source/Sink) 38 Source, VCOMP = 1.4V, VFB = 0V 110 Error Amplifier Output Current (Source/ Sink) Error Amplifier Output Voltage Swing Unit 600/ 365 1000/ 1265 µmho µmho (min) µmho (max) 26 44 V/V V/V (min) V/V (max) 80/ 50 140/ 180 µA µA (min) µA (max) −100/ −85 −180/ −185 µA µA (min) µA (max) 1.8 2.4 V V(min) V(max) 0.2 1.0 V V(min) V(max) −140 Sink, VCOMP = 1.4V, VFB = 1.4V VEAO Limit Upper Limit VFB = 0V COMP Pin = Floating 2.2 Lower Limit VFB = 1.4V 0.56 TSS Internal Soft-Start Delay VFB = 1.2V, VCOMP = Floating 4 msec Tr Drive Pin Rise Time Cgs = 3000pf, VDR = 0 to 3V 25 ns Tf Drive Pin Fall Time VSD Shutdown threshold ISD Cgs = 3000pf, VDR = 0 to 3V (6) Shutdown Pin Current 25 ns Output = High 1.27 1.4 V V (max) Output = Low 0.65 0.3 V V (min) VSD = 5V −1 VSD = 0V +1 µA IFB Feedback Pin Current 15 nA TSD Thermal Shutdown 165 °C Tsh Thermal Shutdown Hysteresis 10 °C θJA Thermal Resistance VSSOP Package 200 °C/W SOIC Package 151 (6) 4 The FA/SD pin should be pulled to VIN through a resistor to turn the regulator off. The voltage on the FA/SD pin must be above the maximum limit for Output = High to keep the regulator off and must be below the limit for Output = Low to keep the regulator on. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 LM3478 LM3478-Q1 www.ti.com SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 Typical Performance Characteristics Unless otherwise specified, VIN = 12V, TJ = 25°C. IQ vs Input Voltage (Shutdown) ISupply vs Input Voltage (Non-Switching) Figure 4. Figure 5. ISupply vs VIN (Switching) Switching Frequency vs RFA Figure 6. Figure 7. Frequency vs Temperature Drive Voltage vs Input Voltage Figure 8. Figure 9. Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 Submit Documentation Feedback 5 LM3478 LM3478-Q1 SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, VIN = 12V, TJ = 25°C. 6 Current Sense Threshold vs Input Voltage COMP Pin Voltage vs Load Current Figure 10. Figure 11. Efficiency vs Load Current (3.3V In and 12V Out) Efficiency vs Load Current (5V In and 12V Out) Figure 12. Figure 13. Efficiency vs Load Current (9V In and 12V Out) Efficiency vs Load Current (3.3V In and 5V Out) Figure 14. Figure 15. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 LM3478 LM3478-Q1 www.ti.com SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 Typical Performance Characteristics (continued) Unless otherwise specified, VIN = 12V, TJ = 25°C. Error Amplifier Gain Error Amplifier Phase Figure 16. Figure 17. COMP Pin Source Current vs Temperature Short Circuit Sense Voltage vs Input Voltage Figure 18. Figure 19. Compensation Ramp vs Compensation Resistor Shutdown Threshold Hysteresis vs Temperature Figure 20. Figure 21. Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 Submit Documentation Feedback 7 LM3478 LM3478-Q1 SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, VIN = 12V, TJ = 25°C. Duty Cycle vs Current Sense Voltage Figure 22. FUNCTIONAL BLOCK DIAGRAM VIN FA/SD Fixed Frequency Detect Oscillator Softstart internal slope compensation Under Voltage Lockout LDO 1.26V Reference COMP 7.2V internal Vcc Gm Error Amplifier PWM DR FB S Q DRIVER logic Isen Vfb+Vovp OVP 325mV AGND R Short Circuit Comparator THERMAL LIMIT (165°C) slope compensation ramp adjust current source PGND Figure 23. 8 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 LM3478 LM3478-Q1 www.ti.com SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 FUNCTIONAL DESCRIPTION The LM3478 uses a fixed frequency, Pulse Width Modulated (PWM) current mode control architecture. The block diagram above shows the basic functionality. In a typical application circuit, the peak current through the external MOSFET is sensed through an external sense resistor. The voltage across this resistor is fed into the ISEN pin. This voltage is fed into the positive input of the PWM comparator. The output voltage is also sensed through an external feedback resistor divider network and fed into the error amplifier negative input (feedback pin, FB). The output of the error amplifier (COMP pin) is added to the slope compensation ramp and fed into the negative input of the PWM comparator. At the start of any switching cycle, the oscillator sets the RS latch using the switch logic block. This forces a high signal on the DR pin (gate of the external MOSFET) and the external MOSFET turns on. When the voltage on the positive input of the PWM comparator exceeds the negative input, the RS latch is reset and the external MOSFET turns off. The voltage sensed across the sense resistor generally contains spurious noise spikes, as shown in Figure 25. These spikes can force the PWM comparator to reset the RS latch prematurely. To prevent these spikes from resetting the latch, a blank-out circuit inside the IC prevents the PWM comparator from resetting the latch for a short duration after the latch is set. This duration is about 325ns and is called the blanking interval and is specified as minimum on-time in the Electrical Characteristics section. Under extremely light-load or no-load conditions, the energy delivered to the output capacitor when the external MOSFET in on during the blanking interval is more than what is delivered to the load. An over-voltage comparator inside the LM3478 prevents the output voltage from rising under these conditions. The over-voltage comparator senses the feedback (FB pin) voltage and resets the RS latch. The latch remains in reset state until the output decays to the nominal value. OVER VOLTAGE PROTECTION The LM3478 has over voltage protection (OVP) for the output voltage. OVP is sensed at the feedback pin (pin 3). If at anytime the voltage at the feedback pin rises to VFB+ VOVP, OVP is triggered. See ELECTRICAL CHARACTERISTICS section for limits on VFB and VOVP. OVP will cause the drive pin to go low, forcing the power MOSFET off. With the MOSFET off, the output voltage will drop. The LM3478 will begin switching again when the feedback voltage reaches VFB + (VOVP - VOVP(HYS)). See ELECTRICAL CHARACTERISTICS for limits on VOVP(HYS). OVP can be triggered if the unregulated input voltage crosses 7.2V, the output voltage will react as shown in Figure 24. The internal bias of the LM3478 comes from either the internal LDO as shown in the block diagram or the voltage at the Vin pin is used directly. At Vin voltages lower than 7.2V the internal IC bias is the Vin voltage and at voltages above 7.2V the internal LDO of the LM3478 provides the bias. At the switch over threshold at 7.2V a sudden small change in bias voltage is seen by all the internal blocks of the LM3478. The control voltage shifts because of the bias change, the PWM comparator tries to keep regulation. To the PWM comparator, the scenario is identical to a step change in the load current, so the response at the output voltage is the same as would be observed in a step load change. Hence, the output voltage overshoot here can also trigger OVP. The LM3478 will regulate in hysteretic mode for several cycles, or may not recover and simply stay in hysteretic mode until the load current drops or Vin is not crossing the 7.2V threshold anymore. Note that the output is still regulated in hysteretic mode. Depending on the requirements of the application there is some influence one has over this effect. The threshold of 7.2V can be shifted to higher voltages by adding a resistor in series with Vin. In case Vin is right at the threshold of 7.2V it can happen that the threshold is crossed over and over due to some slight ripple on Vin. To minimize the effect on the output voltage one can filter the Vin pin with an RC filter. Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 Submit Documentation Feedback 9 LM3478 LM3478-Q1 SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 www.ti.com VIN (V) 7.2V t VFB (V) OVP (1.31V) 1.26V t Figure 24. The Feedback Voltage Experiences an Oscillation if the Input Voltage crosses the 7.2V Internal Bias Threshold Blank-Out prevents false reset PWM Comparator resets the RS latch 92 mV typ + PWM Comparator Oscillator Sets the RS Latch 325 ns Blank-Out time Figure 25. Basic Operation of the PWM Comparator SLOPE COMPENSATION RAMP The LM3478 uses a current mode control scheme. The main advantages of current mode control are inherent cycle-by-cycle current limit for the switch and simpler control loop characteristics. It is also easy to parallel power stages using current mode control since current sharing is automatic. However, current mode control has an inherent instability for duty cycles greater than 50%, as shown in Figure 26. A small increase in the load current causes the switch current to increase by ΔI0. The effect of this load change is ΔI1. The two solid waveforms shown are the waveforms compared at the internal pulse width modulator, used to generate the MOSFET drive signal. The top waveform with the slope Se is the internally generated control waveform VC. The bottom waveform with slopes Sn and Sf is the sensed inductor current waveform VSEN. 10 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 LM3478 LM3478-Q1 www.ti.com SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 Voltage VC PWM Comparator Waveforms Se 'I0 VSEN 'I2 Sn Sf 'I1 Time Figure 26. Sub-Harmonic Oscillation for D>0.5 and Compensation Ramp to Avoid Sub-Harmonic Oscillation Sub-harmonic Oscillation can be easily understood as a geometric problem. If the control signal does not have slope, the slope representing the inductor current ramps up until the control signal is reached and then slopes down again. If the duty cycle is above 50%, any perturbation will not converge but diverge from cycle to cycle and causes sub-harmonic oscillation. It is apparent that the difference in the inductor current from one cycle to the next is a function of Sn, Sf and Se as follows: 'In = Sf - Se 'I Sn + Se n-1 (1) Hence, if the quantity (Sf - Se)/(Sn + Se) is greater than 1, the inductor current diverges and subharmonic oscillation results. This counts for all current mode topologies. The LM3478 has some internal slope compensation VSL which is enough for many applications above 50% duty cycle to avoid subharmonic oscillation . For boost applications, the slopes Se, Sf and Sn can be calculated with the formulas below: Se = VSL x fs (2) Sf = Rsen x (VOUT - VIN)/L (3) Sn = VIN x Rsen/L (4) When Se increases then the factor which determines if subharmonic oscillation will occur decreases. When the duty cycle is greater than 50%, and the inductance becomes less, the factor increases. For more flexibility slope compensation can be increased by adding one external resistor, RSL, in the Isens path. Figure 27 shows the setup. The externally generated slope compensation is then added to the internal slope compensation of the LM3478. When using external slope compensation, the formula for Se becomes: Se = (VSL + (K x RSL)) x fs (5) A typical value for factor K is 40 µA. The factor changes with switching frequency. Figure 28 is used to determine the factor K for individual applications and the formula below gives the factor K. K = ΔVSL / RSL (6) It is a good design practice to only add as much slope compensation as needed to avoid subharmonic oscillation. Additional slope compensation minimizes the influence of the sensed current in the control loop. With very large slope compensation the control loop characteristics are similar to a voltage mode regulator which compares the error voltage to a saw tooth waveform rather than the inductor current. Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 Submit Documentation Feedback 11 LM3478 LM3478-Q1 SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 DR www.ti.com Q LM3478 ISEN RSL RSEN Figure 27. Adding External Slope Compensation Figure 28. External Slope Compensation ΔVSL vs RSL FREQUENCY ADJUST/SHUTDOWN The switching frequency of the LM3478 can be adjusted between 100kHz and 1MHz using a single external resistor. This resistor must be connected between FA/SD pin and ground, as shown in Figure 29. To determine the value of the resistor required for a desired switching frequency refer to Typical Performance Characteristics or use the following equation: RFA = 4.503 x 1011 x fS- 1.26 (7) Figure 29. Frequency Adjust The FA/SD pin also functions as a shutdown pin. If a high signal (>1.35V) appears on the FA/SD pin, the LM3478 stops switching and goes into a low current mode. The total supply current of the IC reduces to less than 10 µA under these conditions. Figure 30 shows implementation of the shutdown function when operating in frequency adjust mode. In this mode a high signal for more than 30us shuts down the IC. However, the voltage on the FA/SD pin should be always less than the absolute maximum of 7V to avoid any damage to the device. 12 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 LM3478 LM3478-Q1 www.ti.com SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 Figure 30. Shutdown Operation in Frequency Adjust Mode SHORT-CIRCUIT PROTECTION When the voltage across the sense resistor measured on the ISEN pin exceeds 343 mV, short circuit current limit protection gets activated. A comparator inside the LM3478 reduces the switching frequency by a factor of 5 and maintains this condition until the short is removed. In normal operation the sensed current will trigger the power MOSFET to turn off. During the blanking interval the PWM comparator will not react to an over current so that this additional 343 mV current limit threshold is implemented to protect the device in a short circuit or severe overload condition. Typical Applications The LM3478 may be operated in either the continuous (CCM) or the discontinuous current conduction mode (DCM). The following applications are designed for the CCM operation. This mode of operation has higher efficiency and usually lower EMI characteristics than the DCM. BOOST CONVERTER The boost converter converts a low input voltage into a higher output voltage. The basic configuration for a boost converter is shown in Figure 31. In the CCM (when the inductor current never reaches zero at steady state), the boost regulator operates in two states. In the first state of operation, MOSFET Q is turned on and energy is stored in the inductor. During this state, diode D is reverse biased and load current is supplied by the output capacitor, Cout. In the second state, MOSFET Q is off and the diode is forward biased. The energy stored in the inductor is transferred to the load and the output capacitor. The ratio of the switch on time to the total period is the duty cycle D: D = 1 - (Vin / Vout) (8) Including the voltage drop across the MOSFET and the diode the definition for the duty cycle is: D = 1 - ((Vin - Vq)/(Vout + Vd)) (9) Vd is the forward voltage drop of the diode and Vq is the voltage drop across the MOSFET when it is on. Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 Submit Documentation Feedback 13 LM3478 LM3478-Q1 SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 www.ti.com Figure 31. Simplified Boost Converter (a) First Cycle Operation (b) Second Cycle of Operation POWER INDUCTOR SELECTION The inductor is one of the two energy storage elements in a boost converter. Figure 32 shows how the inductor current varies during a switching cycle. The current through an inductor is quantified by the following relationship of L, IL and VL: (10) The important quantities in determining a proper inductance value are IL (the average inductor current) and ΔIL (the inductor current ripple). If ΔIL is larger than IL, the inductor current will drop to zero for a portion of the cycle and the converter will operate in the DCM. All the analysis in this datasheet assumes operation in the CCM. To operate in the CCM, the following condition must be met: (11) Choose the minimum Iout to determine the minimum inductance value. A common choice is to set ΔIL to 30% of IL. Choosing an appropriate core size for the inductor involves calculating the average and peak currents expected through the inductor. In a boost converter the peak inductor current is: ILPEAK = Average IL(max) + ΔIL(max) Average IL(max) = Iout / (1-D) ΔIL(max) = D x Vin / (2 x fs x L) (12) (13) (14) An inductor size with ratings higher than these values has to be selected. If the inductor is not properly rated, saturation will occur and may cause the circuit to malfunction. The LM3478 can be set to switch at very high frequencies. When the switching frequency is high, the converter can be operated with very small inductor values. The LM3478 senses the peak current through the switch which is the same as the peak inductor current as calculated above. 14 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 LM3478 LM3478-Q1 www.ti.com SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 IL (A) VIN L VIN VOUT L 'iL IL_AVG t (s) D*Ts Ts (a) ID (A) VIN - V OUT L ID_AVG =IOUT_AVG t (s) D*Ts Ts (b) ISW (A) VIN L ISW_AVG t (s) D*Ts Ts (C) Figure 32. Inductor Current and Diode Current Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 Submit Documentation Feedback 15 LM3478 LM3478-Q1 SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 www.ti.com PROGRAMMING THE OUTPUT VOLTAGE The output voltage can be programmed using a resistor divider between the output and the FB pin. The resistors are selected such that the voltage at the FB pin is 1.26V. Pick RF1 (the resistor between the output voltage and the feedback pin) and RF2 (the resistor between the feedback pin and ground) can be selected using the following equation, RF2 = (1.26V x RF1) / (Vout - 1.26V) (15) A 100pF capacitor may be connected between the feedback and ground pins to reduce noise. SETTING THE CURRENT LIMIT The maximum amount of current that can be delivered to the load is set by the sense resistor, RSEN. Current limit occurs when the voltage that is generated across the sense resistor equals the current sense threshold voltage, VSENSE. When this threshold is reached, the switch will be turned off until the next cycle. Limits for VSENSE are specified in the electrical characteristics section. VSENSE represents the maximum value of the internal control signal VCS as shown in Figure 33. This control signal, however, is not a constant value and changes over the course of a period as a result of the internal compensation ramp (VSL). Therefore the current limit threshold will also change. The actual current limit threshold is a function of the sense voltage (VSENSE) and the internal compensation ramp: RSEN x ISWLIMIT = VCSMAX = VSENSE - (D x VSL) (16) Where ISWLIMIT is the peak switch current limit, defined by the equation below. 120 VSL DUTY CYCLE (%) 100 80 VSENSE 60 FS = 500 kHz 40 20 FS = 250 kHz 0 0.000 0.100 0.200 0.300 0.400 0.500 CURRENT SENSE VOLTAGE (V) Figure 33. Current Sense Voltage vs Duty Cycle Figure 33 shows how VCS (and current limit threshold voltage) change with duty cycle. The curve is equivalent to the internal compensation ramp slope (Se) and is bounded at low duty cycle by VSENSE, shown as a dotted line. As duty cycle increases, the control voltage is reduced as VSL ramps up. The graph also shows the short circuit current limit threshold of 343 mV (typical) during the 325 ns (typical) blanking time. For higher frequencies this fixed blanking time obviously occupies more duty cycle, percentage wise. Since current limit threshold varies with duty cycle, the following equation should be used to select RSEN and set the desired current limit threshold: VSENSE - (D x VSL) RSEN = ISWLIMIT (17) The numerator of the above equation is VCS, and ISWLIMIT is calculated as: ISWLIMIT = IOUT + (D x VIN) (1-D) (2 x fS x L) (18) To avoid false triggering, the current limit value should have some margin above the maximum operating value, typically 120%. Values for both VSENSE and VSL are specified in Electrical Characteristics. However, calculating with the limits of these two specs could result in an unrealistically wide current limit or RSEN range. Therefore, the following equation is recommended, using the VSL ratio value given in Electrical Characteristics: 16 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 LM3478 LM3478-Q1 www.ti.com RSEN = SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 VSENSE - (D x VSENSE x VSLratio) ISWLIMIT (19) RSEN is part of the current mode control loop and has some influence on control loop stability. Therefore, once the current limit threshold is set, loop stability must be verified. As described in the slope compensation section, the following must hold true for a current mode converter to be stable: Sf - Se < Sn + Se (20) To verify that this equation holds true, use the following equation: 2 x VSL x fS x L RSEN < Vo - (2 x VIN) (21) If the selected RSEN is greater than this value, additional slope compensation must be added to ensure stability, as described in the section below. CURRENT LIMIT WITH EXTERNAL SLOPE COMPENSATION RSL is used to add additional slope compensation when required. It is not necessary in most designs and RSL should be no larger than necessary. Select RSL according to the following equation: RSEN x (Vo - 2VIN) - VSL 2 x fS x L RSL > 40 PA (22) Where RSEN is the selected value based on current limit. With RSL installed, the control signal includes additional external slope to stabilize the loop, which will also have an effect on the current limit threshold. Therefore, the current limit threshold must be re-verified, as illustrated in the equations below : VCS = VSENSE – (D x (VSL + ΔVSL)) (23) Where ΔVSL is the additional slope compensation generated as discussed in the slope compensation ramp section and calculated as: ΔVSL = 40 µA x RSL (24) This changes the equation for current limit (or RSEN) to: VSENSE - (D x(VSL + 'VSL)) ISWLIMIT = RSEN (25) The RSEN and RSL values may have to be calculated iteratively in order to achieve both the desired current limit and stable operation. In some designs RSL can also help to filter noise on the ISEN pin. If the inductor is selected such that ripple current is the recommended 30% value, and the current limit threshold is 120% of the maximum peak, a simpler method can be used to determine RSEN. The equation below will provide optimum stability without RSL, provided that the above 2 conditions are met: VSENSE RSEN = Vo - Vi xD ISWLIMIT + L x fS (26) POWER DIODE SELECTION Observation of the boost converter circuit shows that the average current through the diode is the average load current, and the peak current through the diode is the peak current through the inductor. The diode should be rated to handle more than its peak current. The peak diode current can be calculated using the formula: ID(Peak) = IOUT/ (1−D) + ΔIL (27) Thermally the diode must be able to handle the maximum average current delivered to the output. The peak reverse voltage for boost converters is equal to the regulated output voltage. The diode must be capable of handling this voltage. To improve efficiency, a low forward drop schottky diode is recommended. Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 Submit Documentation Feedback 17 LM3478 LM3478-Q1 SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 www.ti.com POWER MOSFET SELECTION The drive pin of the LM3478 must be connected to the gate of an external MOSFET. The drive pin (DR) voltage depends on the input voltage (see typical performance characteristics). In most applications, a logic level MOSFET can be used. For very low input voltages, a sub logic level MOSFET should be used. The selected MOSFET has a great influence on the system efficiency. The critical parameters for selecting a MOSFET are: 1. Minimum threshold voltage, VTH(MIN) 2. On-resistance, RDS(ON) 3. Total gate charge, Qg 4. Reverse transfer capacitance, CRSS 5. Maximum drain to source voltage, VDS(MAX) The off-state voltage of the MOSFET is approximately equal to the output voltage. Vds(max) must be greater than the output voltage. The power losses in the MOSFET can be categorized into conduction losses and switching losses. Rds(on) is needed to estimate the conduction losses, Pcond: Pcond = I2 x RDS(ON) x D (28) The temperature effect on the RDS(ON) usually is quite significant. Assume 30% increase at hot. For the current I in the formula above the average inductor current may be used. Especially at high switching frequencies the switching losses may be the largest portion of the total losses. The switching losses are very difficult to calculate due to changing parasitics of a given MOSFET in operation. Often the individual MOSFET's data sheet does not give enough information to yield a useful result. The following formulas give a rough idea how the switching losses are calculated: PSW = ILmax x Vout 2 tLH = Qgd + x fSW x (tLH + tHL) (29) RdrOn Qgs x Vdr - Vgsth 2 (30) INPUT CAPACITOR SELECTION Due to the presence of an inductor at the input of a boost converter, the input current waveform is continuous and triangular as shown in Figure 32. The inductor ensures that the input capacitor sees fairly low ripple currents. However, as the input capacitor gets smaller, the input ripple goes up. The RMS current in the input capacitor is given by: (31) The input capacitor should be capable of handling the RMS current. Although the input capacitor is not as critical in a boost application, low values can cause impedance interactions. Therefore a good quality capacitor should be chosen in the range of 10µF to 20µF. If a value lower than 10µF is used, then problems with impedance interactions or switching noise can affect the LM3478. To improve performance, especially with Vin below 8 volts, it is recommended to use a 20 Ohm resistor at the input to provide an RC filter. The resistor is placed in series with the VIN pin with only a bypass capacitor attached to the VIN pin directly (see Figure 34). A 0.1µF or 1µF ceramic capacitor is necessary in this configuration. The bulk input capacitor and inductor will connect on the other side of the resistor at the input power supply. RIN VIN LM3478 CBYPASS VIN CIN Figure 34. Reducing IC Input Noise 18 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 LM3478 LM3478-Q1 www.ti.com SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 OUTPUT CAPACITOR SELECTION The output capacitor in a boost converter provides all the output current when the inductor is charging. As a result it sees very large ripple currents. The output capacitor should be capable of handling the maximum RMS current. The RMS current in the output capacitor is: (32) Where (33) The ESR and ESL of the capacitor directly control the output ripple. Use capacitors with low ESR and ESL at the output for high efficiency and low ripple voltage. Surface mount tantalums, surface mount polymer electrolytic, polymer tantalum, or multi-layer ceramic capacitors are recommended at the output. For applications that require very low output voltage ripple, a second stage LC filter often is a good solution. Most of the time it is lower cost to use a small second Inductor in the power path and an additional final output capacitor than to reduce the output voltage ripple by purely increasing the output capacitor without an additional LC filter. LAYOUT GUIDELINES Good board layout is critical for switching controllers. First the ground plane area must be sufficient for thermal dissipation purposes and second, appropriate guidelines must be followed to reduce the effects of switching noise. Switching converters are very fast switching devices. In such devices, the rapid increase of input current combined with the parasitic trace inductance generates unwanted Ldi/dt noise spikes. The magnitude of this noise tends to increase as the output current increases. This parasitic spike noise may turn into electromagnetic interference (EMI), and can also cause problems in device performance. Therefore, care must be taken in layout to minimize the effect of this switching noise. The current sensing circuit in current mode devices can be easily affected by switching noise. This noise can cause duty cycle jittering which leads to increased spectral noise. Although the LM3478 has 325ns blanking time at the beginning of every cycle to ignore this noise, some noise may remain after the blanking time. The most important layout rule is to keep the AC current loops as small as possible. Figure 35 shows the current flow of a boost converter. The top schematic shows a dotted line which represents the current flow during onstate and the middle schematic shows the current flow during off-state. The bottom schematic shows the currents we refer to as AC currents. They are the most critical ones since current is changing in very short time periods. The dotted lined traces of the bottom schematic are the once to make as short as possible. Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 Submit Documentation Feedback 19 LM3478 LM3478-Q1 SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 www.ti.com Figure 35. Current Flow In A Boost Application The PGND and AGND pins have to be connected to the same ground very close to the IC. To avoid ground loop currents, attach all the grounds of the system only at one point. A ceramic input capacitor should be connected as close as possible to the Vin pin and grounded close to the GND pin. For a layout example please see AN-1204. For more information about layout in switch mode power supplies please refer to AN-1229. COMPENSATION For detailed explanation on how to select the right compensation components to attach to the compensation pin for a boost topology please see AN-1286. Designing SEPIC Using the LM3478 Since the LM3478 controls a low-side N-Channel MOSFET, it can also be used in SEPIC (Single Ended Primary Inductance Converter) applications. An example of a SEPIC using the LM3478 is shown in Figure 36. Note that the output voltage can be higher or lower than the input voltage. The SEPIC uses two inductors to step-up or step-down the input voltage. The inductors L1 and L2 can be two discrete inductors or two windings of a coupled inductor since equal voltages are applied across the inductor throughout the switching cycle. Using two discrete inductors allows use of catalog magnetics, as opposed to a custom inductor. The input ripple can be reduced along with size by using the coupled windings for L1 and L2. Due to the presence of the inductor L1 at the input, the SEPIC inherits all the benefits of a boost converter. One main advantage of a SEPIC over a boost converter is the inherent input to output isolation. The capacitor CS isolates the input from the output and provides protection against a shorted or malfunctioning load. Hence, the SEPIC is useful for replacing boost circuits when true shutdown is required. This means that the output voltage falls to 0V when the switch is turned off. In a boost converter, the output can only fall to the input voltage minus a diode drop. The duty cycle of a SEPIC is given by: (34) In the above equation, VQ is the on-state voltage of the MOSFET, Q, and VDIODE is the forward voltage drop of the diode. 20 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 LM3478 LM3478-Q1 www.ti.com SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 Figure 36. Typical SEPIC Converter POWER MOSFET SELECTION As in a boost converter, parameters governing the selection of the MOSFET are the minimum threshold voltage, VTH(MIN), the on-resistance, RDS(ON), the total gate charge, Qg, the reverse transfer capacitance, CRSS, and the maximum drain to source voltage, VDS(MAX). The peak switch voltage in a SEPIC is given by: VSW(PEAK) = VIN + VOUT + VDIODE (35) The selected MOSFET should satisfy the condition: VDS(MAX) > VSW(PEAK) (36) The peak switch current is given by: (37) The RMS current through the switch is given by: (38) POWER DIODE SELECTION The Power diode must be selected to handle the peak current and the peak reverse voltage. In a SEPIC, the diode peak current is the same as the switch peak current. The off-state voltage or peak reverse voltage of the diode is VIN + VOUT. Similar to the boost converter, the average diode current is equal to the output current. Schottky diodes are recommended. SELECTION OF INDUCTORS L1 AND L2 Proper selection of inductors L1 and L2 to maintain continuous current conduction mode requires calculations of the following parameters. Average current in the inductors: (39) (40) IL2AVE = IOUT Peak to peak ripple current, to calculate core loss if necessary: Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 Submit Documentation Feedback 21 LM3478 LM3478-Q1 SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 www.ti.com (41) (42) Maintaining the condition IL > ΔiL/2 to ensure continuous current conduction yields: (VIN - VQ)(1-D) L1 > 2IOUTfS L2 > (43) (VIN - VQ)D 2IOUTfS (44) Peak current in the inductor, to ensure the inductor does not saturate: (45) (46) IL1PK must be lower than the maximum current rating set by the current sense resistor. The value of L1 can be increased above the minimum recommended to reduce input ripple and output ripple. However, once DIL1 is less than 20% of IL1AVE, the benefit to output ripple is minimal. By increasing the value of L2 above the minimum recommended, ΔIL2 can be reduced, which in turn will reduce the output ripple voltage: 'VOUT = ( IOUT 1-D + 'IL2 2 ) ESR (47) where ESR is the effective series resistance of the output capacitor. If L1 and L2 are wound on the same core, then L1 = L2 = L. All the equations above will hold true if the inductance is replaced by 2L. SENSE RESISTOR SELECTION The peak current through the switch, ISW(PEAK) can be adjusted using the current sense resistor, RSEN, to provide a certain output current. Resistor RSEN can be selected using the formula: VSENSE - D(VSL + 'VSL) RSEN = ISWPEAK (48) Sepic Capacitor Selection The selection of the SEPIC capacitor, CS, depends on the RMS current. The RMS current of the SEPIC capacitor is given by: (49) The SEPIC capacitor must be rated for a large ACrms current relative to the output power. This property makes the SEPIC much better suited to lower power applications where the RMS current through the capacitor is relatively small (relative to capacitor technology). The voltage rating of the SEPIC capacitor must be greater than the maximum input voltage. There is an energy balance between CS and L1, which can be used to determine the value of the capacitor. The basic energy balance equation is: (50) where 22 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 LM3478 LM3478-Q1 www.ti.com SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 (51) is the ripple voltage across the SEPIC capacitor, and (52) is the ripple current through the inductor L1. The energy balance equation can be solved to provide a minimum value for CS: (53) Input Capacitor Selection Similar to a boost converter, the SEPIC has an inductor at the input. Hence, the input current waveform is continuous and triangular. The inductor ensures that the input capacitor sees fairly low ripple currents. However, as the input capacitor gets smaller, the input ripple goes up. The RMS current in the input capacitor is given by: (54) The input capacitor should be capable of handling the RMS current. Although the input capacitor is not as critical in a boost application, low values can cause impedance interactions. Therefore a good quality capacitor should be chosen in the range of 10µF to 20µF. If a value lower than 10µF is used than problems with impedance interactions or switching noise can affect the LM3478. To improve performance, especially with VIN below 8 volts, it is recommended to use a 20Ω resistor at the input to provide a RC filter. The resistor is placed in series with the VIN pin with only a bypass capacitor attached to the VIN pin directly (see Figure 34). A 0.1µF or 1µF ceramic capacitor is necessary in this configuration. The bulk input capacitor and inductor will connect on the other side of the resistor with the input power supply. Output Capacitor Selection The output capacitor of the SEPIC sees very large ripple currents (similar to the output capacitor of a boost converter). The RMS current through the output capacitor is given by: IRMS = 2 ISWPK2 - ISWPK ('IL1 + 'IL2)+ ('IL1 + 'IL2) (1-D) - IOUT2 3 (55) The ESR and ESL of the output capacitor directly control the output ripple. Use low capacitors with low ESR and ESL at the output for high efficiency and low ripple voltage. Surface mount tantalums, surface mount polymer electrolytic and polymer tantalum, Sanyo-OSCON, or multi-layer ceramic capacitors are recommended at the output for low ripple. Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 Submit Documentation Feedback 23 LM3478 LM3478-Q1 SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 www.ti.com Other Application Circuits Figure 37. Typical Flyback Circuit RBYP 10: RSL 604: CSEN 10 nF CC2 0.47 PF ISEN RC 100: VIN CC 1 PF FB VIN = from 5V to 0.5V L1 3.3 PH + CIN 2 x 10 PF, 16V MBRS130LT3 VOUT = 9V, 20 mA D1 COUT 3 x 10 PF, 16V FA/SD COMP RFB1 10 k: RFA 71.5 k: D2 BAT54C-7-F LM3478 Q1 FDS6690A DR AGND PGND CHF 10 nF CBYP 100 nF RFB2 61.9 k: RSEN 0.03: Figure 38. Back Powering Circuit for Vin < 3V (>3V input needed for startup) 24 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 LM3478 LM3478-Q1 www.ti.com SNVS085V – JULY 2000 – REVISED FEBRUARY 2013 REVISION HISTORY Changes from Revision U (February 2013) to Revision V • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 24 Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3478 LM3478-Q1 Submit Documentation Feedback 25 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LM3478MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM L3478 MA LM3478MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM L3478 MA LM3478MM ACTIVE VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 125 S14B LM3478MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 S14B LM3478MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 S14B LM3478QMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SSFB LM3478QMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SSFB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM3478MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM3478MM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM3478MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM3478MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM3478QMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM3478QMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM3478MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM3478MM VSSOP DGK 8 1000 203.0 190.0 41.0 LM3478MM/NOPB VSSOP DGK 8 1000 203.0 190.0 41.0 LM3478MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LM3478QMM/NOPB VSSOP DGK 8 1000 203.0 190.0 41.0 LM3478QMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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