W9816G6IB 512K 2 BANKS 16 BITS SDRAM Table of Contents1. GENERAL DESCRIPTION.......................................................................................................... 3 2. FEATURES ................................................................................................................................. 3 3. AVAILABLE PART NUMBER ...................................................................................................... 3 4. BALL CONFIGURATION ............................................................................................................ 4 5. BALL DESCRIPTION .................................................................................................................. 5 6. BLOCK DIAGRAM ...................................................................................................................... 6 7. FUNCTIONAL DESCRIPTION.................................................................................................... 7 7.1 Power Up and Initialization .............................................................................................. 7 7.2 Programming Mode Register .......................................................................................... 7 7.3 Bank Activate Command ................................................................................................ 7 7.4 Read and Write Access Modes ...................................................................................... 7 7.5 Burst Read Command .................................................................................................... 8 7.6 Burst Write Command .................................................................................................... 8 7.7 Read Interrupted by a Read ............................................................................................ 8 7.8 Read Interrupted by a Write ............................................................................................ 8 7.9 Write Interrupted by a Write ............................................................................................ 8 7.10 Write Interrupted by a Read ............................................................................................ 8 7.11 Burst Stop Command ..................................................................................................... 9 7.12 Addressing Sequence of Sequential Mode ..................................................................... 9 7.13 Addressing Sequence of Interleave Mode ...................................................................... 9 7.14 Auto-precharge Command ........................................................................................... 10 7.15 Precharge Command .................................................................................................... 10 7.16 Self Refresh Command ................................................................................................ 10 7.17 Power Down Mode ........................................................................................................ 11 7.18 No Operation Command ............................................................................................... 11 7.19 Deselect Command ...................................................................................................... 11 7.20 Clock Suspend Mode .................................................................................................... 11 8. OPERATION MODE ................................................................................................................. 12 9. ELECTRICAL CHARACTERISTICS ......................................................................................... 13 9.1 Absolute Maximum Ratings .......................................................................................... 13 9.2 Recommended DC Operating Conditions .................................................................... 13 9.3 Capacitance .................................................................................................................. 13 -1- Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 10. 11. 12. 9.4 DC Characteristics ........................................................................................................ 14 9.5 AC Characteristics ........................................................................................................ 15 TIMING WAVEFORMS ............................................................................................................. 17 10.1 Command Input Timing ................................................................................................ 17 10.2 Read Timing.................................................................................................................. 18 10.3 Control Timing of Input/Output Data ............................................................................. 19 10.4 Mode Register Set Cycle .............................................................................................. 20 OPERATING TIMING EXAMPLE ............................................................................................. 21 11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ...................................... 21 11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) ............ 22 11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ...................................... 23 11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) ............ 24 11.5 Interleaved Bank Write (Burst Length = 8) ................................................................... 25 11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ......................................... 26 11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) ............................................... 27 11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3).................................... 28 11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3) ........................................ 29 11.10 Auto Precharge Write (Burst Length = 4) .................................................................... 30 11.11 Auto Refresh Cycle ...................................................................................................... 31 11.12 Self Refresh Cycle ....................................................................................................... 32 11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) ............................ 33 11.14 Power Down Mode ...................................................................................................... 34 11.15 Auto-precharge Timing (Read Cycle) .......................................................................... 35 11.16 Auto-precharge Timing (Write Cycle) .......................................................................... 36 11.17 Timing Chart of Read to Write Cycle ........................................................................... 37 11.18 Timing Chart of Write to Read Cycle ........................................................................... 37 11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) .......................................... 38 11.20 Timing Chart of Burst Stop Cycle (Precharge Command) .......................................... 38 11.21 CKE/DQM Input Timing (Write Cycle) ......................................................................... 39 11.22 CKE/DQM Input Timing (Read Cycle) ......................................................................... 40 PACKAGE SPECIFICATION .................................................................................................... 41 12.1 13. VFBGA 60 Ball (6.4X10.10 mm, Ball pitch:0.65mm, Ø =0.4mm) .................................. 41 REVISION HISTORY ................................................................................................................ 42 -2- Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 1. GENERAL DESCRIPTION W9816G6IB is a high-speed synchronous dynamic random access memory (SDRAM), organized as 512K words 2 banks 16 bits. W9816G6IB delivers a data bandwidth of up to 166M words per second (-6). For different applications the W9816G6IB is sorted into the following speed grades: -6/-6I and -7. The -6/-6I parts can run up to 166MHz/CL3 (the -6I industrial grade which is guaranteed to support -40°C ~ 85°C). The -7 parts can run up to 143MHz/CL3. Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9816G6IB is ideal for main memory in high performance applications. 2. FEATURES 2.7V~3.6V power supply for -7 speed grade 3.3V 0.3V power supply for -6/-6I speed grade 524,288 words x 2 banks x 16 bits organization Self Refresh current: standard and low power CAS Latency: 2 and 3 Burst Length: 1, 2, 4, 8 and Full Page Burst Read, Single Writes Mode Byte Data Controlled by LDQM, UDQM Auto-precharge and Controlled Precharge 4K Refresh Cycles/64 mS Interface: LVTTL Packaged in VFBGA 60 balls pitch=0.65mm, using Lead free materials with RoHS compliant 3. AVAILABLE PART NUMBER PART NUMBER SPEED GRADE SELF REFRESH CURRENT (MAX.) OPERATING TEMPERATURE W9816G6IB-6 166MHz/CL3 2mA 0°C ~ 70°C W9816G6IB-6I 166MHz/CL3 2mA -40°C ~ 85°C W9816G6IB-7 143MHz/CL3 2mA 0°C ~ 70°C -3- Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 4. BALL CONFIGURATION Top View 1 2 Bottom View 6 7 7 6 2 1 A Vss DQ15 DQ0 VDD VDD DQ0 DQ15 Vss A B DQ14 VssQ VDDQ DQ1 DQ1 VDDQ VssQ DQ14 B C DQ13 VDDQ VssQ DQ2 DQ2 VssQ VDDQ DQ13 C D DQ12 DQ11 DQ4 DQ3 DQ3 DQ4 DQ11 DQ12 D E DQ10 VssQ VDDQ DQ5 DQ5 VDDQ VssQ DQ10 E F DQ9 VDDQ VssQ DQ6 DQ6 VssQ VDDQ DQ9 F G DQ8 NC NC DQ7 DQ7 NC NC DQ8 G H NC NC NC NC NC NC NC NC H J NC UDQM LDQM WE# WE# LDQM UDQM NC J K NC CLK RAS# CAS# CAS# RAS# CLK NC K L CKE NC NC CS# CS# NC NC CKE L M BA A9 NC NC NC NC A9 BA M N A8 A7 A0 A10 A10 A0 A7 A8 N P A6 A5 A2 A1 A1 A2 A5 A6 P R Vss A4 A3 VDD VDD A3 A4 Vss R -4- Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 5. BALL DESCRIPTION Ball-Location Ball Name Function N6, P7, P6, R6, R2, P2, P1, N2, N1, M2, N7 A0A10 Address M1 BA Bank Address Description Multiplexed pins for row and column address. Row address: A0A10. Column address: A0A7. Select bank to activate during row address latch time, or bank to read/write during column address latch time. A6, B7, C7, D7, D6, E7, F7, G7, DQ0DQ15 Data Input/ Output Multiplexed pins for data input and output. G1, F1, E1, D2, D1, C1, B1, A2, L7 CS Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. K6 RAS Row Address Strobe Command input. When sampled at the rising edge of the clock, RAS , CAS and WE define the operation to be executed. K7 CAS J7 WE Write Enable Referred to RAS UDQM/ LDQM Input/Output Mask The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. K2 CLK Clock Inputs System clock used to sample inputs on the rising edge of clock. L1 CKE Clock Enable CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. A7, R7 VCC Power (+3.3V) Power for input buffers and logic circuit inside DRAM. A1, R1 VSS Ground Ground for input buffers and logic circuit inside DRAM. B6, C2, E6, F2 VCCQ B2, C6, E2, F6 VSSQ Ground for I/O buffer G2, G6, H1, H2, H6, H7, J1, K1, L2, L6, M6, M7 NC No Connection J2/J6 Column Address Referred to RAS Strobe Power (+3.3V) for Separated power from VCC, used for output buffers I/O buffer to improve noise immunity. Separated ground from VSS, used for output buffers to improve noise immunity. No connection. (NC pin should be connected to GND or floating) -5- Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 6. BLOCK DIAGRAM CLK CLOCK BUFFER CK E CS CO NT RO L SI G NAL RA S CA S G ENERAT O R COMMAND DE CODE R COLUMN DE CODER R O W D E C O D E R WE CE LL ARRA Y BA NK #0 SE NS E A MP LIFIER A10 MODE RE GIS T E R A0 A9 BA ADDRES S BUFFER DQ BUFFER DA T A CONT ROL CIRCUIT DQ0 DQ15 LDQM UDQM RE FRES H COUNT E R COLUMN COUNT E R COLUMN DE CODER R O W D E C O D E R CE LL ARRA Y BA NK #1 SE NS E A MP LIFIER Note: The cell array conf iguration is 2048 * 256 * 16 -6- Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 7. FUNCTIONAL DESCRIPTION 7.1 Power Up and Initialization The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs during power up, all VCC and VCCQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power up voltage must not exceed VCC + 0.3V on any of the input pins or VCC supplies. After power up, an initial pause of 200 µS is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation. 7.2 Programming Mode Register After initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS , CAS , CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table. 7.3 Bank Activate Command The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t RC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank-to-Bank delay time (tRRD). The maximum time that each bank can be held active is specified as tRAS(max.). 7.4 Read and Write Access Modes After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The address inputs determine the starting column address. Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle. -7- Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 7.5 Burst Read Command The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8 and full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequence mode. 7.6 Burst Write Command The Burst Write command is initiated by applying logic low level to CS , CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored. 7.7 Read Interrupted by a Read A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS Latency from the interrupting Read Command the is satisfied. 7.8 Read Interrupted by a Write To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed. 7.9 Write Interrupted by a Write A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. 7.10 Write Interrupted by a Read A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored. -8- Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 7.11 Burst Stop Command A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored. 7.12 Addressing Sequence of Sequential Mode A column access is performed by increasing the address from the column address, which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2. Table 2 Address Sequence of Sequential Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 n BL = 2 (disturb address is A0) Data 1 n+1 No address carry from A0 to A1 Data 2 n+2 BL = 4 (disturb addresses are A0 and A1) Data 3 n+3 No address carry from A1 to A2 Data 4 n+4 Data 5 n+5 BL = 8 (disturb addresses are A0, A1 and A2) Data 6 n+6 No address carry from A2 to A3 Data 7 n+7 7.13 Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3. Table 3 Address Sequence of Interleave Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2 Data 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 2 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 3 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 4 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 5 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 6 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0 -9- BL = 4 BL = 8 Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 7.14 Auto-precharge Command If A10 is set to high when the Read or Write Command is issued, then the Auto-precharge function is entered. During Auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS Latency. A Read or Write Command with Auto-precharge can not be interrupted before the entire burst operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with Auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-precharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-precharge function is initiated. The SDRAM automatically enters the precharge operation two clock delay from the last burst write cycle. This delay is referred to as Write t WR. The bank undergoing Auto-precharge can not be reactivated until tWR and tRP are satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS(min). 7.15 Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS , RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. The address bits, A10, and BA, are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP). 7.16 Self Refresh Command The Self-Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self-Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self-Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self-Refresh Operation to save power. The device will exit SelfRefresh operation after CKE is returned high. Any subsequent commands can be issued after t XSR from the end of Self Refresh command. If, during normal operation, Auto-Refresh cycles are issued in bursts (as opposed to being evenly distributed), a burst of 2,048 Auto-Refresh cycles should be completed just prior to entering and just after exiting the Self-Refresh mode. - 10 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 7.17 Power Down Mode The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations; therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on tCK. The input buffers need to be enabled with CKE held high for a period equal to tCKS(min) + tCK(min). 7.18 No Operation Command The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS , CAS and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 7.19 Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS , CAS and WE signals become don't cares. 7.20 Clock Suspend Mode During normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one-clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one-clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. - 11 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 8. OPERATION MODE Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands. TABLE 1 TRUTH TABLE (NOTE 1, 2) COMMAND DEVICE STATE CKEn-1 CKEn DQM BA A10 A9-A0 CS V V L L H H RAS CAS WE Bank Active Idle H X X V Bank Precharge Any H X X V L X L L H L Precharge All Any H X X X H X L L H L Write Active (3) H X X V L V L H L L Write with Auto-precharge Active (3) H X X V H V L H L L Read Active (3) H X X V L V L H L H Read with Auto-precharge Active (3) H X X V H V L H L H Idle H X X V V V L L L L H Mode Register Set No-Operation Any H X X X X X L H H Active (4) H X X X X X L H H L Device Deselect Any H X X X X X H X X X Auto-Refresh Idle H H X X X X L L L H Self-Refresh Entry Idle H L X X X X L L L H Self-Refresh Exit Idle (S.R) L L H H X X X X X X X X H L X H X H X X Clock Suspend Mode Entry Active H L X X X X X X X X Power Down Mode Entry Idle Active (5) H H L L X X X X X X X X H L X H X H X X Clock Suspend Mode Exit Active L H X X X X X X X X Any (power down) L L H H X X X X X X X X H X X X L H H X Data Write/Output Enable Active H X L X X X X X X X Data Write/Output Disable Active X H X X X X X X X Burst Stop Power Down Mode Exit H Notes :(1) V = Valid, X = Don't care, L = Low Level, H = High Level (2) CKEn signal is input level when commands are provided. CKEn-1 signal is the input level one clock cycle before the command is issued. (3) These are state of bank designated by BA signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode. - 12 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 9. ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings SYMBOL RATING UNIT NOTES Input, Output Voltage PARAMETER VIN, VOUT -1 ~ VCC + 0.3 V 1 Power Supply Voltage VCC, VCCQ -1~ 4.6 V 1 Operating Temperature for -6/-7 TOPR 0 ~ 70 °C 1 Operating Temperature for -6I TOPR -40 ~ 85 °C 1 Storage Temperature TSTG -55 ~ 150 °C 1 TSOLDER 260 °C 1 PD 1 W 1 IOUT 50 mA 1 Soldering Temperature (10s) Power Dissipation Short Circuit Output Current Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 9.2 Recommended DC Operating Conditions (TA = 0 to 70°C for -6/-7 , TA= -40 to 85°C for -6I) PARAMETER SYM. MIN. TYP. MAX. UNIT NOTES Power Supply Voltage for -6/-6I VCC 3.0 3.3 3.6 V 2 Power Supply Voltage for -7 VCC 2.7 3.3 3.6 V 2 Power Supply Voltage for -6/-6I (for I/O Buffer) VCCQ 3.0 3.3 3.6 V 2 Power Supply Voltage for -7 (for I/O Buffer) VCCQ 2.7 3.3 3.6 V 2 Input High Voltage VIH 2.0 - VCC + 0.3 V 2 Input Low Voltage VIL -0.3 - 0.8 V 2 Note: VIH (max.) = VCC/VCCQ +1.5V for pulse width < 5 nS VIL (min.) = VSS/VSSQ -1.5V for pulse width < 5 nS 9.3 Capacitance (VCC = 3.3V ±0.3V, TA = 25 C, f = 1MHz) PARAMETER Input Capacitance (A0 to A10, BA, CS , RAS , CAS , WE , UDQM, LDQM, CKE) SYM. MIN. MAX. UNIT CI - 4 pf - 4 pf - 5.5 pf Input Capacitance (CLK) Input/Output capacitance (DQ0 to DQ15) CIO Note: These parameters are periodically sampled and not 100% tested - 13 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 9.4 DC Characteristics (VCC = 3.3V ±0.3V for -6/-6I, VCC = 2.7V to 3.6V for -7, TA = 0 to 70°C for -6/-7, TA= -40 to 85°C for -6I) PARAMETER Operating Current tCK = min., t RC = min. Active precharge command cycling without burst operation SYM. MAX. -6/-6I -7 UNIT NOTES 1 Bank Operation ICC1 60 50 3 CKE = VIH ICC2 30 25 3 ICC2P 2 2 3 ICC2S 10 10 ICC2PS 2 2 ICC3 40 35 ICC3P 10 10 ICC4 110 100 3, 4 ICC5 55 50 3 ICC6 2 2 mA SYM. MIN. MAX. UNIT Input Leakage Current (0V VIN VCC, all other pins not under test = 0V) II(L) -5 5 µA Output Leakage Current (Output disable , 0V VOUT VCCQ ) IO(L) -5 5 µA LVTTL Output H Level Voltage (IOUT = -2 mA) VOH 2.4 - V LVTTL Output L Level Voltage (IOUT = 2 mA) VOL - 0.4 V Standby Current tCK = min., CS = VIH VIH /L = VIH (min.) / VIL (max.) Bank: inactive state Standby Current CKE = VIL (Power Down mode) CKE = VIH CLK = VIL, CS = VIH VIH/L = VIH (min.) / VIL (max.) Bank: inactive state CKE = VIL No Operating Current CKE = VIH tCK = min., CS = VIH (min.) Bank: active state (2 Banks) CKE = VIL (Power Down mode) (Power Down mode) Burst Operating Current (t CK = min.) Read/ Write command cycling Auto Refresh Current (t CK = min.) Auto refresh command cycling Self Refresh Current (CKE = 0.2V) Self refresh mode PARAMETER - 14 - mA NOTES Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 9.5 AC Characteristics (VCC = 3.3V ±0.3V for -6/-6I, VCC = 2.7V to 3.6V for -7, TA = 0 to 70°C for -6/-7, TA= -40 to 85°C for -6I) -6/-6I PARAMETER -7 SYM. UNIT MIN. MAX. MIN. Ref/Active to Ref/Active Command Period tRC 60 Active to Precharge Command Period tRAS 42 Active to Read/Write Command Delay Time tRCD 18 20 Read/Write(a) to Read/Write(b)Command Period tCCD 1 1 Precharge to Active(b) Command Period tRP 18 18 Active(a) to Active(b) Command Period tRRD 12 14 2 2 2 2 Write Recovery Time CLK Cycle Time CL* = 2 CL* = 3 CL* = 2 CL* = 3 tWR tCK NOTES MAX. 65 100000 45 100000 nS tCK nS tCK 8 1000 10 1000 6 1000 7 1000 CLK High Level Width tCH 2 2 8 CLK Low Level Width tCL 2 2 8 Access Time from CLK CL* = 2 CL* = 3 tAC 5.5 5.5 9 5 5 9 Output Data Hold Time tOH 2 Output Data High Impedance Time tHZ 2 Output Data Low Impedance Time tLZ 0 Power Down Mode Entry Time tSB 0 Data-in-Set-up Time tDS 1.5 1.5 8 Data-in Hold Time tDH 0.7 1 8 Address Set-up Time tAS 1.5 1.5 8 Address Hold Time tAH 0.7 1 8 CKE Set-up Time tCKS 1.5 1.5 8 CKE Hold Time tCKH 0.7 1 8 Command Set-up Time tCMS 1.5 1.5 8 Command Hold Time tCMH 0.7 1 8 Refresh Time tREF Mode Register Set Cycle Time tRSC 2 2 tCK Exit self refresh to ACTIVE command tXSR 72 75 nS - 15 - 2 6 2.5 9 7 0 6 0 64 7 64 7 nS 9 mS Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB Notes: 1. Operation exceeds "Absolute Maximum Ratings" may cause permanent damage to the devices. 2. All voltages are referenced to VSS. 2.7V~3.6V power supply for -7 speed grade. 3.3V 0.3V power supply for -6/-6I speed grades. 3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK and tRC. 4. These parameters depend on the output loading conditions. Specified values are obtained with output open. 5. Power up sequence please refer to "Functional Description" section described before. 6. AC Test Load diagram. 1.4 V 50 ohms output Z = 50 ohms 30pF AC TEST LOAD 7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. 8. Assumed input rise and fall time (tT ) = 1nS. If tr & tf is longer than 1nS, transient time compensation should be considered, i.e., [(tr + tf)/2-1]nS should be added to the parameter ( The tT maximum can’t be more than 10nS for low frequency application. ) 9. If clock rising time (tT) is longer than 1nS, (tT /2-0.5)nS should be added to the parameter. - 16 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 10. TIMING WAVEFORMS 10.1 Command Input Timing tCL tCK tCH VIH CLK VIL tT tCMS tCMH tCMS tCMH tCMS tCMH tCMS tCMH tAS tAH tCMH tT tCMS CS RAS CAS WE A0-A10 BA tCKS tCKH tCKS tCKH tCKS tCKH CKE - 17 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 10.2 Read Timing Read CAS Latency CLK CS RAS CAS WE A0-A10 BA tAC tAC tLZ tHZ tOH tOH Valid Data-Out Valid Data-Out DQ Read Command Burst Length - 18 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 10.3 Control Timing of Input/Output Data Control Timing of Input Data (Word Mask) CLK tCMS tCMH t CMH tCMS DQM t DS t DH tDS Valid Data-in DQ0 -15 t DH tDS Valid Data-in t DH t DS Valid Data-in t DH Valid Data-in (Clock Mask) CLK t CKH tCKS t CKH t DH t DS t DH tCKS CKE t DS DQ0 -15 Valid Data-in t DS Valid Data-in tDS t DH t DH Valid Data-in Valid Data-in Control Timing of Output Data (Output Enable) CLK t CMS t CMH tCMS t CMH DQM t AC t LZ t OH Valid Data-Out DQ0 -15 t AC t HZ t AC t OH t OH Valid Data-Out t AC t OH Valid Data-Out OPEN (Clock Mask) CLK t CKH t CKS tCKH tCKS CKE t AC t OH DQ0 -15 t AC t AC t OH t OH Valid Data-Out Valid Data-Out - 19 - t AC t OH Valid Data-Out Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 10.4 Mode Register Set Cycle tRSC CLK tCMS tCMH tCMS tCMH tCMS tCMH tCMS tCMH tAS tAH CS RAS CAS WE A0-A10 BA Register set data A0 A1 Burst Length A2 A3 Addressing Mode A4 A5 CAS Latency next command A0 A0 A0 A2 A1 0 A0 0 0 0 A0 0 1 0 A0 1 0 0 A0 1 1 1 A0 0 0 1 A0 0 1 1 A0 1 0 1 A0 1 1 A0 A3 A0 0 A0 1 A6 A0 A7 "0" (Test Mode) A8 "0" Reserved Write Mode A9 A10 "0" A0 BA "0" Reserved A6 0 0 0 0 1 A0 A5 A0 0 A0 0 A0 1 A0 1 A0 0 A0 A9 A0 0 A0 1 - 20 - BurstA0 Length A0 A0 Sequential Interleave 1 A0 1 A0 A0 2 2 A0 A0 4 4 A0 A0 8 8 A0 Reserved A0 Reserved FullA0 Page A0 Mode Addressing A0 Sequential A0 Interleave A4 0 1 0 1 0 CAS A0 Latency A0 Reserved A0 Reserved 2 A0 3 Reserved Single Write Mode A0 Burst write Burst read and A0 single write Burst read and Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11. OPERATING TIMING EXAMPLE 11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC RAS tRAS tRP tRAS tRAS tRP tRP tRAS CAS WE BA tRCD A10 RAa A0-A9 RAa tRCD tRCD RBb CAw tRCD RAc CBx RBb RBd RAc CAy RAe RBd CBz RAe DQM CKE aw0 tRRD Bank #0 Active Bank #1 tAC tAC tAC DQ aw1 aw2 aw3 bx0 Precharge Active bx2 bx3 Active - 21 - cy1 cy2 cy3 tRRD Precharge Read Precharge Read tAC cy0 tRRD tRRD Read bx1 Active Active Read Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC RAS tRAS tRP tRAS tRP tRAS tRP tRAS CAS WE BA tRCD tRCD A10 RAa A0-A9 RAa RBb CAw tRCD tRCD RBd RAc CBx RBb CAy RAc RAe CBz RBd RAe DQM CKE tAC tAC DQ aw0 tRRD Bank #0 Bank #1 Active aw1 aw2 aw3 tAC bx0 bx1 Active AP* Active bx3 tAC cy0 cy1 tRRD tRRD Read bx2 Read cy3 dz0 tRRD AP* Read AP* cy2 Active Active Read * AP is the internal precharge start timing - 22 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS t RC RAS t RAS tRP t RAS tRP CAS WE BA t RCD A10 RAa A0-A9 RAa t RCD t RCD RAc RBb CAx RBb CBy RAc CAz DQM CKE tAC DQ tAC ax0 ax1 t RRD Bank #0 Bank #1 Active ax2 ax3 ax4 by0 by1 by4 by5 by6 by7 CZ0 t RRD Read Precharge ax6 ax5 tAC Precharge Active Read - 23 - Active Read Precharge Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tRC CS RAS tRAS tRAS tRP tRAS tRP CAS WE BA tRCD A10 RAa A0-A9 RAa tRCD tRCD RAc RBb CAx RAc CBy RBb CAz DQM CKE tAC DQ ax0 ax1 ax2 tRRD Bank #0 Bank #1 Active tAC tAC ax3 ax4 ax5 ax6 ax7 by0 by1 by4 Active Read by5 by6 CZ0 tRRD AP* Read Active Read AP* * AP is the internal precharge start timing - 24 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11.5 Interleaved Bank Write (Burst Length = 8) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRAS CAS tRCD tRCD tRCD WE BA A10 RAa A0-A9 RAa RBb RAc RBb CAx CBy CAz RAc DQM CKE DQ ax0 ax1 ax4 ax5 ax6 ax7 by0 tRRD Bank #0 Bank #1 Active by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD Precharge Write Active Write - 25 - Active Write Precharge Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRAS tRAS tRP CAS WE BA tRCD tRCD A10 RAa A0-A9 RAa tRCD RBb CAx RAb RBb CBy CAz RAc DQM CKE ax0 DQ ax1 ax4 ax5 ax6 ax7 by0 by1 Bank #1 Active by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD tRRD Bank #0 by2 Write Active AP* Active Write AP* Write * AP is the internal precharge start timing - 26 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tCCD tCCD tCCD CS tRAS tRAS RAS CAS WE BA tRCD A10 RAa A0-A9 RAa tRCD RBb RBb CAI CBx CAy CAm CBz DQM CKE tAC a0 DQ tAC tAC a2 a1 a3 bx0 bx1 Ay0 tAC Ay1 Ay2 tAC am0 am1 am2 bz0 bz1 bz2 bz3 tRRD Bank #0 Active Bank #1 Read Active Read Read Precharge Read Read AP* * AP is the internal precharge start timing - 27 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) 0 1 2 3 5 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRAS RAS CAS WE BA tRCD A10 RAa A0-A9 RAa CAy CAx DQM CKE tAC DQ tWR ax0 Q Q Bank #0 Active ax1 ax3 ax2 Q Q ax5 ax4 Q Q Read ay1 ay0 D D Write ay2 D ay3 D ay4 D Precharge Bank #1 - 28 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRAS tRP CAS WE BA tRCD A10 RAa A0-A9 RAa tRCD RAb CAw RAb CAx DQM CKE tAC DQ Bank #0 tAC aw0 Active Read aw1 AP* aw2 bx0 aw3 Active Read bx1 bx2 bx3 AP* Bank #1 * AP is the internal precharge start timing - 29 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11.10 Auto Precharge Write (Burst Length = 4) CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS tRC tRC RAS tRP tRAS tRAS tRP CAS WE BA tRCD tRCD A10 RAa A0-A9 RAa RAc RAb CAw RAb CAx RAc DQM CKE aw0 DQ Bank #0 Active Write aw1 aw2 aw3 bx0 AP* Active bx1 bx2 bx3 AP* Write Active Bank #1 * AP is the internal precharge start timing - 30 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11.11 Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tRP tRC tRC CS RAS CAS WE BA A10 A0-A9 DQM CKE DQ All Banks Prechage Auto Refresh Auto Refresh (Arbitrary Cycle) - 31 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11.12 Self Refresh Cycle CLK CS tRP RAS CAS WE BA A10 A0-A9 DQM tCKS tSB CKE tCKS DQ tXSR Self Refresh Cycle All Banks Precharge Self Refresh Entry No Operation / Command Inhibit Self Refresh Exit - 32 - Arbitrary Cycle Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS tRCD WE BA A10 RBa A0-A9 RBa CBv CBw CBx CBy CBz DQM CKE tAC tAC DQ av0 Q Bank #0 Active av1 Q av2 av3 aw0 ax0 ay0 az0 az1 az2 az3 Q Q D D D Q Q Q Q Read Single Write Read Bank #1 - 33 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11.14 Power Down Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS WE BA A10 RAa A0-A9 RAa RAa CAa RAa CAx DQM tSB tSB CKE tCKS tCKS DQ ax0 Active tCKS tCKS ax1 ax2 NOP Read ax3 Precharge NOP Active Precharge Standby Power Down mode Active Standby Power Down mode Note: The PowerDown Mode is entered by asserting CKE "low". All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode. When CKE goes high, command input must be No operation at next CLK rising edge. Violating refresh requirements during power-down may result in a loss of data. - 34 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11.15 Auto-precharge Timing (Read Cycle) 0 1 Read AP 2 3 4 5 6 7 8 9 10 11 (1) CAS Latency =2 ( a ) burst length = 1 Command Act tRP DQ Q0 ( b ) burst length = 2 Command Read AP Act tRP DQ Q0 Q1 ( c ) burst length = 4 Command Read AP Act tRP DQ Q0 Q1 Q2 Q3 ( d ) burst length = 8 Command Read AP Q0 DQ Q1 Q2 Q3 Q4 Q5 Q6 Act tRP Q7 (2) CAS Latency =3 ( a ) burst length = 1 Command Read AP Act tRP Q0 DQ ( b ) burst length = 2 Command Read AP Act tRP Q0 DQ Q1 ( c ) burst length = 4 Command Read AP Act tRP Q0 DQ Q1 Q2 Q3 ( d ) burst length = 8 Command Read AP Act tRP Q0 DQ Q1 Q2 Q3 Q4 Q5 Q6 Q7 Note: Read AP Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least RAS t (min). - 35 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11.16 Auto-precharge Timing (Write Cycle) 0 1 2 3 4 5 6 7 8 9 10 11 12 CLK (1) CAS Latency = 2 (a) burst length = 1 Command Write AP tWR DQ Act tRP D0 (b) burst length = 2 Command Write AP Act tWR DQ D0 tRP D1 (c) burst length = 4 Command AP Write DQ D0 D1 D2 Act tRP tWR D3 (d) burst length = 8 Command Write AP tWR DQ D0 D1 D2 D3 D4 D5 D6 Act tRP D7 (2) CAS Latency = 3 (a) burst length = 1 Command Write AP Act tWR DQ (b) burst length = 2 Command tRP D0 Write AP Act tWR DQ D0 tRP D1 (c) burst length = 4 Command Write AP Act tWR DQ D0 D1 D2 tRP D3 (d) burst length = 8 Command Write AP tWR DQ D0 D1 D2 D3 D4 D5 D6 Act tRP D7 Note ) Write represents the Write with Auto precharge command. AP represents the start of internal precharing. Act represents the Bank Activ e command. When the /auto precharge command is asserted,the period f rom Bank Activ ate command to the start of intermal precgarging must be at least tRAS (min). - 36 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11.17 Timing Chart of Read to Write Cycle In the case of Burst Length = 4 (1) CAS Latency=2 0 1 2 3 4 5 D1 D2 D3 D0 D1 D2 D1 D2 D3 D1 D2 6 7 8 9 10 11 9 10 11 Read Write ( a ) C ommand D QM DQ D0 Read ( b ) C ommand Write D QM DQ D3 (2) CAS Latency=3 Read Write ( a ) C ommand D QM D0 DQ Read ( b ) C ommand Write D QM D0 DQ D3 Note: The Output data must be masked by DQM to avoid I/O conflict 11.18 Timing Chart of Write to Read Cycle In the case of Burst Length=4 0 1 2 3 4 5 6 7 8 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 (1) CAS Latency=2 ( a ) C ommand Write Read D QM DQ ( b ) C ommand D0 Read Write D QM DQ D0 D1 (2) CAS Latency=3 ( a ) C ommand Write Read D QM DQ ( b ) C ommand D0 Write Read D QM DQ D0 D1 - 37 - Q3 Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) 0 1 2 3 4 5 6 7 8 9 10 11 (1) Read cycle ( a ) CAS latency =2 Command Read BST Q0 DQ Q1 Q2 Q0 Q1 Q3 Q4 ( b )CAS latency = 3 Read Command BST DQ Q2 Q3 Q4 (2) W rite cycle Write Command DQ Q0 BST Q1 Q2 Note: Q3 Q4 BST represents the Burst stop command 11.20 Timing Chart of Burst Stop Cycle (Precharge Command) 0 1 2 3 4 5 6 7 8 9 10 11 (1) Read cycle (a) CAS latency =2 Command Read PRCG DQ (b) CAS latency =3 Command Q0 Q1 Q2 Read Q3 Q4 PRCG DQ Q0 Q1 Q2 Q3 Q4 (2) Write cycle Command PRCG Write tWR DQM DQ Q0 Q1 Q2 Q3 Q4 - 38 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11.21 CKE/DQM Input Timing (Write Cycle) CLK cy cle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ D5 DQM MASK D6 CKE MASK (1) CLK cy cle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ DQM MASK D5 D6 5 6 7 D4 D5 D6 CKE MASK (2) CLK cy cle No. 1 2 3 D1 D2 D3 4 External CLK Internal CKE DQM DQ CKE MASK (3) - 39 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 11.22 CKE/DQM Input Timing (Read Cycle) CLK cy cle No. 1 2 3 4 Q1 Q2 Q3 Q4 6 5 7 External CLK Internal CKE DQM DQ Q6 Open Open (1) CLK cy cle No. 1 2 3 Q1 Q2 Q3 4 5 6 7 External CLK Internal CKE DQM DQ Q6 Q4 Open (2) CLK cy cle No. 1 2 Q1 Q2 3 4 5 6 7 Q4 Q5 Q6 External CLK Internal CKE DQM DQ Q3 (3) - 40 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 12. PACKAGE SPECIFICATION 12.1 VFBGA 60 Ball (6.4X10.10 mm, Ball pitch:0.65mm, Ø =0.4mm) - 41 - Publication Release Date: Mar. 28, 2011 Revision A02 W9816G6IB 13. REVISION HISTORY VERSION DATE PAGE A01 Dec. 24, 2009 All A02 Mar. 28, 2011 DESCRIPTION Initial formal data sheet 3, 13~16 Add -6I industrial speed grade parts Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 42 - Publication Release Date: Mar. 28, 2011 Revision A02