W9864G6JH 1M 4 BANKS 16 BITS SDRAM Table of Contents1. GENERAL DESCRIPTION.......................................................................................................... 3 2. FEATURES ................................................................................................................................. 3 3. AVAILABLE PART NUMBER ...................................................................................................... 4 4. PIN CONFIGURATION ............................................................................................................... 4 5. PIN DESCRIPTION ..................................................................................................................... 5 6. BLOCK DIAGRAM ...................................................................................................................... 6 7. FUNCTIONAL DESCRIPTION.................................................................................................... 7 7.1 Power Up and Initialization .............................................................................................. 7 7.2 Programming Mode Register Set command .................................................................. 7 7.3 Bank Activate Command ................................................................................................ 7 7.4 Read and Write Access Modes ...................................................................................... 7 7.5 Burst Read Command .................................................................................................... 8 7.6 Burst Command .............................................................................................................. 8 7.7 Read Interrupted by a Read ............................................................................................ 8 7.8 Read Interrupted by a Write ............................................................................................ 8 7.9 Write Interrupted by a Write ............................................................................................ 8 7.10 Write Interrupted by a Read ............................................................................................ 8 7.11 Burst Stop Command ..................................................................................................... 9 7.12 Addressing Sequence of Sequential Mode ..................................................................... 9 7.13 Addressing Sequence of Interleave Mode ...................................................................... 9 7.14 Auto-precharge Command ........................................................................................... 10 7.15 Precharge Command .................................................................................................... 10 7.16 Self Refresh Command ................................................................................................ 10 7.17 Power Down Mode ........................................................................................................ 11 7.18 No Operation Command ............................................................................................... 11 7.19 Deselect Command ...................................................................................................... 11 7.20 Clock Suspend Mode .................................................................................................... 11 8. OPERATION MODE ................................................................................................................. 12 9. ELECTRICAL CHARACTERISTICS ......................................................................................... 13 9.1 Absolute Maximum Ratings .......................................................................................... 13 9.2 Recommended DC Operating Conditions .................................................................... 13 9.3 Capacitance .................................................................................................................. 13 -1- Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 10. 11. 12. 9.4 DC Characteristics ........................................................................................................ 14 9.5 AC Characteristics and Operating Condition ................................................................ 15 TIMING WAVEFORMS ............................................................................................................. 18 10.1 Command Input Timing ................................................................................................ 18 10.2 Read Timing.................................................................................................................. 19 10.3 Control Timing of Input/Output Data ............................................................................. 20 10.4 Mode Register Set Cycle .............................................................................................. 21 OPERATINOPERATING TIMING EXAMPLE ........................................................................... 22 11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ...................................... 22 11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) ............ 23 11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ...................................... 24 11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) ............ 25 11.5 Interleaved Bank Write (Burst Length = 8) ................................................................... 26 11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ......................................... 27 11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) ............................................... 28 11.8 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3)...................................... 29 11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3) ......................................... 30 11.10 Auto-precharge Write (Burst Length = 4) .................................................................... 31 11.11 Auto Refresh Cycle ...................................................................................................... 32 11.12 Self Refresh Cycle ....................................................................................................... 33 11.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3) ............................. 34 11.14 Power down Mode ....................................................................................................... 35 11.15 Auto-precharge Timing (Write Cycle) .......................................................................... 36 11.16 Auto-precharge Timing (Read Cycle) .......................................................................... 37 11.17 Timing Chart of Read to Write Cycle ........................................................................... 38 11.18 Timing Chart of Write to Read Cycle ........................................................................... 38 11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) .......................................... 39 11.20 Timing Chart of Burst Stop Cycle (Precharge Command) .......................................... 39 11.21 CKE/DQM Input Timing (Write Cycle) ......................................................................... 40 11.22 CKE/DQM Input Timing (Read Cycle) ......................................................................... 41 PACKAGE SPECIFICATION .................................................................................................... 42 12.1 13. 54L TSOP (II)-400 mil ................................................................................................... 42 REVISION HISTORY ................................................................................................................ 43 -2- Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 1. GENERAL DESCRIPTION W9864G6JH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 1M words 4 banks 16 bits. W9864G6JH delivers a data bandwidth of up to 200M words per second. For different application, W9864G6JH is sorted into the following speed grades: -5/-6/-6I/-6A/-7/-7S. The -5 parts can run up to 200MHz/CL3. The -6/-6I/-6A parts can run up to 166MHz/CL3 (the -6I industrial grade, -6A automotive grade which is guaranteed to support -40°C ~ 85°C). The -7/-7S parts can run up to 143MHz/CL3 and with tRP = 18nS. Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9864G6JH is ideal for main memory in high performance applications. 2. FEATURES 3.3V± 0.3V for -5/-6/-6I/-6A speed grades power supply 2. 7V~3.6V for -7/-7S speed grades power supply 1,048,576 words 4 banks 16 bits organization Self Refresh Current: Standard and Low Power CAS Latency: 2 & 3 Burst Length: 1, 2, 4, 8 and full page Sequential and Interleave Burst Byte data controlled by LDQM, UDQM Auto-precharge and controlled precharge Burst read, single write operation 4K refresh cycles/64mS Interface: LVTTL Packaged in TSOP II 54-pin, 400 mil using Lead free materials with RoHS complian -3- Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 3. AVAILABLE PART NUMBER PART NUMBER SPEED SELF REFRESH CURRENT (MAX.) OPERATING TEMPERATURE W9864G6JH-5 200MHz/CL3 2 mA 0°C ~ 70°C W9864G6JH-6 166MHz/CL3 2 mA 0°C ~ 70°C W9864G6JH-6I 166MHz/CL3 2 mA -40°C ~ 85°C W9864G6JH-6A 166MHz/CL3 2 mA -40°C ~ 85°C W9864G6JH-7 143MHz/CL3 2 mA 0°C ~ 70°C W9864G6JH-7S 143MHz/CL3 2 mA 0°C ~ 70°C 4. PIN CONFIGURATION VDD 1 54 VSS DQ0 2 53 DQ15 VDDQ 3 52 VSSQ DQ1 4 51 DQ14 DQ2 5 50 DQ13 VSSQ 6 49 VDDQ DQ3 7 48 DQ12 8 47 DQ11 VSSQ DQ4 VDDQ 9 46 DQ5 10 45 DQ10 DQ6 11 44 DQ9 VSSQ 12 43 VDDQ DQ7 13 42 DQ8 VDD 14 41 VSS LDQM 15 40 NC WE 16 39 UDQM CAS 17 38 CLK RAS 18 37 CKE CS 19 36 NC BS0 20 35 A11 21 34 A9 A8 BS1 22 33 A0 23 32 A7 A1 24 31 A6 A2 25 30 A5 A3 26 29 A4 VDD 27 28 VSS A10/AP -4- Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 5. PIN DESCRIPTION PIN NUMBER PIN NAME FUNCTION DESCRIPTION Multiplexed pins for row and column address. Row address: A0A11. Column address: A0A7. 23 ~ 26, 22, 29 ~35 A0A11 Address 20, 21 BS0, BS1 Bank Select 2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, DQ0DQ15 51, 53 Data Input/ Output A10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by BS0, BS1. Select bank to activate during row address latch time, or bank to read/write during address latch time. Multiplexed pins for data output and input. Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. CS Chip Select 18 RAS Row Address Strobe 17 CAS 16 WE Write Enable Referred to RAS UDQM LDQM Input/output mask The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. 38 CLK Clock Inputs System clock used to sample inputs on the rising edge of clock. 37 CKE Clock Enable CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. 1, 14, 27 VDD Power Power for input buffers and logic circuit inside DRAM. 28, 41, 54 VSS Ground Ground for input buffers and logic circuit inside DRAM. 3, 9, 43, 49 VDDQ Power for I/O buffer Separated power from VDD, to improve DQ noise immunity. 6, 12, 46, 52 VSSQ Ground for I/O buffer Separated ground from VSS, to improve DQ noise immunity. 36, 40 NC 19 39, 15 Command input. When sampled at the rising edge of the clock RAS , CAS and WE define the operation to be executed. Column Address Strobe Referred to RAS No Connection No connection. -5- Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 6. BLOCK DIAGRAM CLK CLOCK BUFFER CKE CONT RO L CS SIG NAL RAS G ENERATO R COMMAND CAS DECODER COLUMN DECODER A10 MODE REGIST ER A0 CELL ARRAY BANK #0 CELL ARRAY BANK #1 SENSE AMPLIFIER SENSE AMPLIFIER ADDRESS BUFFER DAT A CONT ROL CIRCUIT DQ BUFFER DQ0 DQ15 COLUMN UDQM LDQM COUNT ER COLUMN DECODER COLUMN DECODER ROW DECODER REFRESH COUNT ER ROW DECODER A9 A11 BS0 BS1 COLUMN DECODER ROW DECODER ROW DECODER WE CELL ARRAY BANK #2 SENSE AMPLIFIER CELL ARRAY BANK #3 SENSE AMPLIFIER NOTE: The cell array configuration is 4096 * 256 * 16 -6- Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 7. FUNCTIONAL DESCRIPTION 7.1 Power Up and Initialization The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs. During power up, all VDD and VDDQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power up voltage must not exceed VDD + 0.3V on any of the input pins or VDD supplies. After power up, an initial pause of 200 µS is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation. 7.2 Programming Mode Register Set command After initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS , CAS , CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table. 7.3 Bank Activate Command The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t RC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is specified as tRAS (max.). 7.4 Read and Write Access Modes After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The address inputs determine the starting column address. Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle. -7- Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 7.5 Burst Read Command The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequence mode. 7.6 Burst Command The Burst Write command is initiated by applying logic low level to CS , CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored. 7.7 Read Interrupted by a Read A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS Latency from the interrupting Read Command the is satisfied. 7.8 Read Interrupted by a Write To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed. 7.9 Write Interrupted by a Write A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. 7.10 Write Interrupted by a Read A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored. -8- Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 7.11 Burst Stop Command A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS Latency in a burst read cycle, interrupted by Burst Stop. 7.12 Addressing Sequence of Sequential Mode A column access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2. Table 2 Address Sequence of Sequential Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 n BL = 2 (disturb address is A0) Data 1 n+1 No address carry from A0 to A1 Data 2 n+2 BL = 4 (disturb addresses are A0 and A1) Data 3 n+3 No address carry from A1 to A2 Data 4 n+4 Data 5 n+5 BL = 8 (disturb addresses are A0, A1 and A2) Data 6 n+6 No address carry from A2 to A3 Data 7 n+7 7.13 Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3. Table 3 Address Sequence of Interleave Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2 Data 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 2 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 3 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 4 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 5 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 6 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0 -9- BL = 4 BL = 8 Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 7.14 Auto-precharge Command If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS Latency. A Read or Write Command with auto-precharge cannot be interrupted before the entire burst operation is completed for the same bank. Therefore, use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-Precharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation two clocks delay from the last burst write cycle. This delay is referred to as write tWR. The bank undergoing auto-precharge cannot be reactivated until tWR and tRP are satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS (min). 7.15 Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS , RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BS0, and BS1 are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP). 7.16 Self Refresh Command The Self Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high. Any subsequent commands can be issued after t XSR from the end of Self Refresh Command. If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode. - 10 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 7.17 Power Down Mode The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (t REF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on t CK. The input buffers need to be enabled with CKE held high for a period equal to tCKS (min.) + tCK (min.). 7.18 No Operation Command The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS , CAS , and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 7.19 Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS , CAS , and WE signals become don't Care. 7.20 Clock Suspend Mode During normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. - 11 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 8. OPERATION MODE Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands. Table 1 Truth Table (Note (1), (2)) COMMAND DEVICE STATE CKEn-1 CKEn DQM BS0, 1 A10 A0-A9, A11 CS RAS CAS WE Bank Active Idle H x x v v V L L H H Bank Precharge Any H x x v L x L L H L Precharge All Any H x L L H L H x x x Write Active (3) H x x v L v L H L L Write with Auto-precharge Active (3) H x x v H v L H L L Active (3) H x x v L v L H L H Active (3) H x x v H v L H L H Read Read with Auto-precharge Mode Register Set Idle H x x v v v L L L L No-Operation Any H x x x x x L H H H Active (4) H x x x x x L H H L Device Deselect Any H x x x x x H x x x Auto-Refresh Idle H H x x x x L L L H Self-Refresh Entry Idle H L x x x x L L L H Burst Stop Self Refresh Exit Clock suspend Mode Entry Power Down Mode Entry Clock Suspend Mode Exit idle L H x x x x H x x x (S.R) L H x x x x L H H x Active H L x x x x x x x x Idle H L x x x x H x x X H L x x x x L H H H L H x x x x x x x X L H x x x x H x x X L H x x x x L H H H H x L x x x x x x x x H x x x x x x x Active (5) Active Any Power Down Mode Exit (Power Down) Data write/Output Enable Active Data write/Output Disable Active H Notes: (1) v = valid, x = Don't care, L = Low Level, H = High Level (2) CKEn signal is input leve l when commands are provided. (3) These are state of bank designated by BS0, BS1 signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode. - 12 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 9. ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings PARAMETER SYMBOL RATING UNIT NOTES Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ VDD + 0.5 ( 4.6V max.) V 1 Voltage on VDD/VDDQ supply relative to VSS VDD, VDDQ -0.5 ~ 4.6 V 1 Operating Temperature (-5/-6/-7/-7S) TOPR 0 ~ 70 °C 1 Operating Temperature (-6I/-6A) TOPR -40 ~ 85 °C 1 Storage Temperature TSTG -55 ~ 150 °C 1 TSOLDER 260 °C 1 PD 1 W 1 IOUT 50 mA 1 Soldering Temperature (10s) Power Dissipation Short Circuit Output Current Note: 1. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 9.2 Recommended DC Operating Conditions (TA = 0°C~70°C for -5/-6/-7/-7S, TA= -40°C~85°C for -6I/-6A) PARAMETER SYM. MIN. TYP. MAX. UNIT NOTES Power Supply Voltage for -5/-6/-6I/-6A VDD 3.0 3.3 3.6 V 2 Power Supply Voltage for -7/-7S VDD 2.7 - 3.6 V 2 Power Supply Voltage for -5/-6/-6I/-6A (for I/O Buffer) VDDQ 3.0 3.3 3.6 V 2 Power Supply Voltage for -7/-7S (for I/O Buffer) VDDQ 2.7 - 3.6 V 2 Input High Voltage VIH 2.0 - VDD + 0.3 V 2 Input Low Voltage VIL -0.3 - 0.8 V 2 SYM. MIN. MAX. UNIT Ci1 2.5 4 pf CCLK 2.5 4 pf Input/Output Capacitance (DQ0DQ15) Co 4 6.5 pf Input Capacitance DQM Ci2 3.0 5.5 pf Note: VIH(max) = VDD/ VDDQ+1.5V for pulse width < 5 nS VIL(min) = VSS/ VSSQ-1.5V for pulse width < 5 nS 9.3 Capacitance (VDD =3.3V±0.3V, TA = 25°C, f = 1 MHz) PARAMETER Input Capacitance (A0 to A11, BS0, BS1, CS , RAS , CAS , WE , CKE) Input Capacitance (CLK) Note: These parameters are periodically sampled and not 100% tested - 13 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 9.4 DC Characteristics (VDD = 3.3V±0.3V for-5/-6 ,VDD = 2.7V~3.6V for -7/-7S on TA = 0°C~70°C, VDD =3.3V±0.3V for -6I/-6A on TA = -40°C~85°C) PARAMETER Operating Current tCK = min., tRC = min. Active precharge command cycling without burst operation SYM. MAX. -5 -6/-6I/-6A -7/-7S UNIT NOTES 1 Bank Operation IDD1 55 50 45 3 CKE = VIH IDD2 30 25 20 3 CKE = VIL (Power Down mode) IDD2P 2 2 2 3 CKE = VIH IDD2S 12 12 12 CKE = VIL (Power Down mode) IDD2PS 2 2 2 CKE = VIH IDD3 40 35 30 CKE = VIL (Power Down mode) IDD3P 12 12 12 Burst Operating Current (tCK = min.) Read/Write command cycling IDD4 80 75 70 3, 4 Auto Refresh Current (tCK = min.) Auto refresh command cycling IDD5 65 60 55 3 Self Refresh Current Self refresh mode (CKE = 0.2V) IDD6 2 2 2 Standby Current tCK = min., CS = VIH VIH/L = VIH (min.)/VIL (max.) Bank: Inactive State Standby Current CLK = VIL, CS = VIH VIH/L=VIH (min.)/VIL (max.) Bank: Inactive State No Operating Current tCK = min., CS = VIH (min.) Bank: Active State (4 Banks) PARAMETER Input Leakage Current (0V VIN VDD, all other pins not under test = 0V) Output Leakage Current (Output disable, 0V VOUT VDDQ) LVTTL Output “H” Level Voltage (IOUT = -2 mA) LVTTL Output “L” Level Voltage (IOUT = 2 mA) mA SYMBOL MIN. MAX. UNIT II(L) -5 5 µA lO(L) -5 5 µA VOH 2.4 - V VOL - 0.4 V - 14 - NOTES Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 9.5 AC Characteristics and Operating Condition (VDD = 3.3V±0.3V for-5/-6, VDD = 2.7V-3.6V for -7/-7S on TA = 0°C~70°C, VDD = 3.3V±0.3V for -6I/-6A on TA = -40°C~85°C) (Notes: 5, 6) PARAMETER SYM. -5 MIN. -6/-6I/-6A MAX. MIN. MAX. -7/-7S MIN. Ref/Active to Ref/Active Command Period tRC 55 Active to precharge Command Period tRAS 40 Active to Read/Write Command Delay Time tRCD 15 15 20 Read/Write(a) to Read/Write(b) Command Period tCCD 1 1 1 Precharge to Active Command Period tRP 15 15 18 Active(a) to Active(b) Command Period tRRD 10 12 14 2 2 2 2 2 2 Write Recovery Time CLK Cycle Time CL* = 2 CL* = 3 CL* = 2 CL* = 3 tWR tCK 60 100000 42 MAX. UNIT NOTES 65 100000 45 100000 nS tCK nS tCK 10 1000 7.5 1000 10 1000 5 1000 6 1000 7 1000 CLK High Level Width tCH 2 2 2 9 CLK Low Level Width tCL 2 2 2 9 Access Time from CLK CL* = 2 CL* = 3 Output Data Hold Time tAC tOH 3 - 6 6 10 4.5 5 5.5 10 3 3 10 tHZ 2 Output Data Low Impedance Time tLZ 0 Power Down Mode Entry Time tSB 0 Transition Time of CLK (Rise and Fall) tT Data-in Set-up Time tDS 1.5 1.5 1.5 9 Data-in Hold Time tDH 1 1 1 9 Address Set-up Time tAS 1.5 1.5 1.5 9 Output Data High Impedance Time 5 2 6 0 5 0 1 2 7 7 0 6 0 1 10 7 nS 1 Address Hold Time tAH 1 1 1 9 CKE Set-up Time tCKS 1.5 1.5 1.5 9 CKE Hold Time tCKH 1 1 1 9 Command Set-up Time tCMS 1.5 1.5 1.5 9 Command Hold Time tCMH 1 1 1 9 Refresh Time tREF Mode register Set Cycle Time tRSC 2 2 2 tCK Exit self refresh to ACTIVE command tXSR 70 72 75 nS 64 64 64 mS *CL = CAS Latency - 15 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH Notes: 1. Operation exceeds “Absolute Maximum Ratings” may cause permanent damage to the devices. 2. All voltages are referenced to VSS. • 2.7V~3.6V power supply for -7/-7S speed grades. 3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK and tRC. 4. These parameters depend on the output loading conditions. Specified values are obtained with output open. 5. Power up sequence please refer to "Functional Description" section described before. 6. AC test load diagram. 1.4 V 50 ohms output Z = 50 ohms 30pF AC TEST LOAD 7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. - 16 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 8. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows the number of clock cycles = specified value of timing/ clock period (count fractions as whole number). (1)tCH is the pulse width of CLK measured from the positive edge to the negative edge referenced to V IH (min.). tCL is the pulse width of CLK measured from the negative edge to the positive edge referenced to V IL (max.). (2)A.C Latency Characteristics CKE to clock disable (CKE Latency) 1 DQM to output to HI-Z (Read DQM Latency) 2 DQM to output to HI-Z (Write DQM Latency) 0 Write command to input data (Write Data Latency) 0 CS to Command input ( CS Latency) 0 CL = 2 2 CL = 3 3 CL = 2 1 CL = 3 2 CL = 2 2 CL = 3 3 CL = 2 1 tCK Precharge to DQ Hi-Z Lead time Precharge to Last Valid data out Bust Stop Command to DQ Hi-Z Lead time Bust Stop Command to Last Valid Data out CL = 3 2 CL = 2 BL + tRP CL = 3 BL + tRP CL = 2 (BL+1) + tRP CL = 3 (BL+1) + tRP Read with Auto-precharge Command to Active/Ref Command Write with Auto-precharge Command to Active/Ref Command tCK + nS 9. Assumed input rise and fall time (t T) = 1nS. If tr & tf is longer than 1nS, transient time compensation should be considered, i.e., [(tr + tf)/2-1]nS should be added to the parameter ( The tT maximum can’t be more than 10nS for low frequency application. ) 10. If clock rising time (tT) is longer than 1nS, (tT/2-0.5)nS should be added to the parameter. - 17 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 10. TIMING WAVEFORMS 10.1 Command Input Timing tCK tCL tCH VIH CLK VIL tT tCMS tCMH tCMS tCMH tCMS tCMH tCMS tCMH tAS tAH tCMH tT tCMS CS RAS CAS WE A0-A11 BS0,1 tCKS tCKH tCKS tCKH tCKS tCKH CKE - 18 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 10.2 Read Timing Read CAS Latency CLK CS RAS CAS WE A0-A11 BS0,1 tAC tLZ tAC tOH Valid Data-Out Valid Data-Out DQ Read Command tHZ tOH Burst Length - 19 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 10.3 Control Timing of Input/Output Data Control Timing of Input Data (Word Mask) CLK tCMS tCMH tCMH tCMS DQM tDS tDH tDS tDS Valid Data-in Valid Data-in DQ0~15 tDH tDH tDS tDH Valid Data-in Valid Data-in (Clock Mask) CLK tCKH tCKS tCKH tDH tDS tDH tCKS CKE tDS DQ0~15 Valid Data-in tDS Valid Data-in tDH tDS tDH Valid Data-in Valid Data-in Control Timing of Output Data (Output Enable) CLK tCMS tCMH tCMH tCMS DQM tAC tOH tAC tLZ Valid Data-Out Valid Data-Out DQ0~15 tAC tHZ tOH tOH tAC tOH Valid Data-Out OPEN (Clock Mask) CLK tCKS tCKH tCKH tCKS CKE DQ0~15 tAC tAC tAC tAC tOH tOH tOH Valid Data-Out Valid Data-Out - 20 - tOH Valid Data-Out Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 10.4 Mode Register Set Cycle tRSC CLK tCMS tCMH tCMS tCMH tCMS tCMH tCMS tCMH tAS tAH CS RAS CAS WE A0-A11 BS0,1 Register set data next command A0 A1 Burst Length A2 A3 Addressing Mode A4 A5 CAS Latency A2 0 0 0 0 1 1 1 1 A6 A0 A7 "0" (Test Mode) A8 "0" Reserved WriteA0 Mode A9 A10 "0" A0 A11 "0" BS0 "0" BS1 "0" Reserved A1 A0 A0 A0 0 0 A0 0 1 A0 1 0 A0 1 1 A0 0 0 A0 0 1 A0 1 0 A0 1 1 A0 A3 0 1 A6 0 0 0 0 1 A5 A0 A4 A0 0 0 A0 0 1 A0 1 0 A0 1 1 A0 0 0 A0 A9 0 1 Burst Length Sequential Interleave 1 1 2 2 4 4 8 8 Reserved Reserved Full Page Addressing Mode Sequential Interleave CAS Latency Reserved Reserved 2 3 Reserved Single Write Mode Burst read and Burst write Burst read and single write * "Reserved" should stay "0" during MRS cycle. - 21 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11. OPERATINOPERATING TIMING EXAMPLE 11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC RAS tRAS tRP tRP tRAS tRAS tRP tRAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11 RAa tRCD tRCD RBb CAw tRCD RAc CBx RBb RAe RBd RAc CAy RBd CBz RAe DQM CKE tAC DQ tRRD Bank #0 Active Bank #1 aw1 aw2 aw3 bx0 tRRD Read Precharge Active bx1 bx2 bx3 cy0 tRRD Active cy1 cy2 cy3 tRRD Precharge Read Precharge Read tAC tAC tAC aw0 Active Active Read Bank #2 Idle Bank #3 - 22 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) 0 1 2 3 4 5 6 7 8 9 11 10 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC RAS tRAS tRP tRAS tRP tRAS tRP CAS WE BS0 BS1 tRCD tRCD tRCD A10 RAa RBb A0-A9, A11 RAa CAw RBb tRCD RBd RAc CBx RAc RAe RBd CAy CBz RAe DQM CKE tAC DQ tRRD Bank #0 Active Bank #1 aw1 aw2 aw3 bx0 bx1 tRRD Read Active tAC tAC tAC aw0 bx2 bx3 cy0 cy1 tRRD Active AP* cy3 dz0 tRRD Read AP* Read cy2 Active AP* Active Read Bank #2 Idle Bank #3 * AP is the internal precharge start timing - 23 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRAS tRP CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11 RAa tRCD tRCD RBb CAx RAc RBb RAc CBy CAz DQM CKE tAC DQ tAC ax0 ax1 tRRD Bank #0 Active Bank #1 ax2 ax3 ax4 ax5 tAC by0 by4 by1 by5 by6 by7 CZ0 tRRD Read Precharge ax6 Precharge Active Read Active Read Precharge Bank #2 Idle Bank #3 - 24 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) 0 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tRC CS RAS tRAS tRP tRAS tRAS tRP CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11 RAa tRCD tRCD RAc RBb CAx CBy RBb RAc CAz DQM CKE tAC DQ ax0 ax1 ax2 Active Bank #1 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 Active Read by5 by6 CZ0 tRRD tRRD Bank #0 tAC tAC Read AP* Active Read AP* Bank #2 Idle Bank #3 * AP is the internal precharge start timing - 25 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11.5 Interleaved Bank Write (Burst Length = 8) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRAS CAS tRCD tRCD tRCD WE BS0 BS1 A10 A0-A9, A11 RBb RAa RAa CAx RAc CBy RBb RAc CAz DQM CKE DQ ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 tRRD Bank #0 Active Bank #1 Bank #2 Bank #3 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD Precharge Write Active Write Active Write Precharge Idle - 26 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRP tRAS tRAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11 RAa tRCD tRCD RBb CAx RAb CBy RBb RAc CAz DQM CKE ax0 DQ ax1 ax4 ax5 ax6 ax7 by0 tRRD Bank #0 Active by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD AP* Write Active Bank #1 by1 Write Active Write AP* Bank #2 Idle Bank #3 * AP is the internal precharge start timing - 27 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tCCD tCCD tCCD CS tRAS tRAS RAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11 RAa tRCD RBb CAI RBb CBx CAy CAm CBz DQM CKE DQ a0 a1 a2 a3 tAC tAC tAC tAC bx0 bx1 tAC Ay0 Ay1 Ay2 am0 am1 am2 bz0 bz1 bz2 bz3 tRRD Bank #0 Active Read Active Bank #1 Read Read Read Precharge Read AP* Bank #2 Idle Bank #3 * AP is the internal precharge start timing - 28 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11.8 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) 0 1 2 3 5 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRAS RAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11 RAa CAx CAy DQM CKE tAC DQ tWR ax0 Q Q Bank #0 Active ax1 ax3 ax2 Q Q ax5 ax4 Q Q Read ay1 ay0 D D Write ay2 D ay3 D ay4 D Precharge Bank #1 Bank #2 Bank #3 Idle - 29 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRAS CAS WE BS0 BS1 tRCD A10 tRCD RAa A0-A9, A11 RAa RAb CAw RAb CAx DQM CKE tAC DQ tAC aw0 Bank #0 Active Read aw1 AP* aw2 aw3 bx0 Active Read bx1 bx2 bx3 AP* Bank #1 Bank #2 Idle Bank #3 * AP is the internal precharge start timing - 30 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11.10 Auto-precharge Write (Burst Length = 4) 0 1 2 3 6 5 4 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC RAS tRAS tRP tRAS tRP CAS WE BS0 BS1 tRCD tRCD A10 RAa A0-A9, A11 RAa RAb CAw RAb RAc CAx RAc DQM CKE DQ aw0 Active Bank #0 Write aw1 aw2 aw3 bx0 AP* Active Write bx1 bx2 bx3 AP* Active Bank #1 Bank #2 Idle * AP is the internal precharge start timing Bank #3 - 31 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11.11 Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tRP tRC tRC CS RAS CAS WE BS0,1 A10 A0-A9, A11 DQM CKE DQ All Banks Prechage Auto Refresh Auto Refresh (Arbitrary Cycle) - 32 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11.12 Self Refresh Cycle CLK CS tRP RAS CAS WE BS0,1 A10 A0-A9, A11 DQM tCKS tSB CKE tCKS DQ tXSR Self Refresh Cycle All Banks Precharge Self Refresh Entry No Operation / Command Inhibit Self Refresh Exit - 33 - Arbitrary Cycle Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS t RCD WE BS0 BS1 A10 RBa A0-A9, A11 RBa CBv CBw CBx CBy CBz aw0 ax0 ay0 az0 az1 az2 az3 D D D Q Q Q Q DQM CKE tAC tAC DQ Bank #0 Active av0 av1 av2 av3 Q Q Q Q Read Single Write Read Bank #1 Bank #2 Idle Bank #3 - 34 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11.14 Power down Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS WE BS A10 A0-A9, A11 RAa RAa CAa RAa RAa CAx DQM tSB tSB CKE tCKS tCKS tCKS DQ ax0 Active ax1 ax2 NOP Read tCKS ax3 Precharge NOP Active Precharge Standby Power Down mode Active Standby Power Down mode Note: The Power Down Mode is entered by asserting CKE "low". All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode. When CKE goes high, command input must be No operation at next CLK rising edge. Violating refresh requirements during power-down may result in a loss of data. - 35 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11.15 Auto-precharge Timing (Write Cycle) 0 1 2 3 4 5 6 7 8 9 10 11 12 CLK (1) CAS Latency = 2 (a) burst length = 1 Command Write AP tWR DQ Act tRP D0 (b) burst length = 2 Command Write AP Act tWR DQ D0 tRP D1 (c) burst length = 4 Command AP Write DQ D0 D1 D2 Act tRP tWR D3 (d) burst length = 8 Command Write AP tWR DQ D0 D1 D2 D3 D4 D5 D6 Act tRP D7 (2) CAS Latency = 3 (a) burst length = 1 Command Write AP Act tWR DQ (b) burst length = 2 Command tRP D0 Write AP Act tWR DQ D0 tRP D1 (c) burst length = 4 Command Write AP Act tWR DQ D0 D1 D2 tRP D3 (d) burst length = 8 Command Write AP tWR DQ D0 D1 D2 D3 D4 D5 D6 Act tRP D7 Note ) Write represents the Write with Auto precharge command. AP represents the start of internal precharing. Act represents the Bank Activ e command. When the /auto precharge command is asserted,the period f rom Bank Activ ate command to the start of intermal precgarging must be at least tRAS (min). - 36 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11.16 Auto-precharge Timing (Read Cycle) 0 1 Read AP 2 3 4 5 6 7 8 9 10 11 (1) CAS Latency =2 ( a ) burst length = 1 Command DQ Act tRP Q0 ( b ) burst length = 2 Command Read AP Act tRP DQ Q0 Q1 ( c ) burst length = 4 Command Read AP Act tRP DQ Q0 Q1 Q2 Q3 ( d ) burst length = 8 Command Read AP Q0 DQ Q1 Q2 Q3 Q4 Q5 Q6 Act tRP Q7 (2) CAS Latency =3 ( a ) burst length = 1 Command Read AP Act tRP Q0 DQ ( b ) burst length = 2 Command Read AP Act tRP Q0 DQ ( c ) burst length = 4 Command Read Q1 AP Act tRP Q0 DQ Q1 Q2 Q3 ( d ) burst length = 8 Command Read AP Act tRP Q0 DQ Q1 Q2 Q3 Q4 Q5 Q6 Q7 Note ) Read represents the Read w ith Auto precharge command. AP represents the start of internal precharging. Act represents the Bank Activate command. When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least t RAS(min). - 37 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11.17 Timing Chart of Read to Write Cycle In the case of Burst Length = 4 1 0 (1) CAS Latency=2 2 3 4 5 6 D1 D2 D3 D0 D1 D2 D1 D2 D3 D1 D2 7 8 9 10 11 Read Write ( a ) C ommand D QM DQ D0 Read ( b ) C ommand Write D QM DQ D3 (2) CAS Latency=3 Read Write ( a ) C ommand D QM D0 DQ Read ( b ) C ommand Write D QM D0 DQ D3 Note: The Output data must be masked by DQM to avoid I/O conflict 11.18 Timing Chart of Write to Read Cycle In the case of Burst Length=4 0 1 2 3 4 5 6 7 8 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 9 10 11 (1) CAS Latency=2 ( a ) C ommand Write Read D QM DQ ( b ) C ommand D0 Read Write D QM DQ D0 D1 (2) CAS Latency=3 ( a ) C ommand Write Read D QM DQ ( b ) C ommand D0 Write Read D QM DQ D0 D1 - 38 - Q3 Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) 0 1 2 3 4 5 6 7 8 9 10 11 (1) Read cycle ( a ) CAS latency =2 Command Read BST Q0 DQ Q1 Q2 Q0 Q1 Q3 Q4 ( b )CAS latency = 3 Read Command BST DQ Q2 Q3 Q4 (2) W rite cycle Write Command DQ Q0 BST Q1 Q2 Note: Q3 Q4 BST represents the Burst stop command 11.20 Timing Chart of Burst Stop Cycle (Precharge Command) 0 1 2 3 4 5 6 7 8 9 10 11 (1) Read cycle (a) CAS latency =2 Command Read PRCG DQ (b) CAS latency =3 Command Q0 Q1 Q2 Read Q3 Q4 PRCG DQ Q0 Q1 Q2 Q3 Q4 (2) Write cycle Command PRCG Write tWR DQM DQ Q0 Q1 Q2 Q3 Q4 - 39 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11.21 CKE/DQM Input Timing (Write Cycle) CLK cy cle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ D5 DQM MASK D6 CKE MASK (1) CLK cy cle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ DQM MASK D5 D6 5 6 7 D4 D5 D6 CKE MASK (2) CLK cy cle No. 1 2 3 D1 D2 D3 4 External CLK Internal CKE DQM DQ CKE MASK (3) - 40 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 11.22 CKE/DQM Input Timing (Read Cycle) CLK cy cle No. 1 2 3 4 Q1 Q2 Q3 Q4 6 5 7 External CLK Internal CKE DQM DQ Q6 Open Open (1) CLK cy cle No. 1 2 3 Q1 Q2 Q3 4 5 6 7 External CLK Internal CKE DQM DQ Q6 Q4 Open (2) CLK cy cle No. 1 2 Q1 Q2 3 4 5 6 7 Q4 Q5 Q6 External CLK Internal CKE DQM DQ Q3 (3) - 41 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 12. PACKAGE SPECIFICATION 12.1 54L TSOP (II)-400 mil 54 28 HE E 1 27 e b C D A2 ZD L A L1 A1 Y SEATING PLANE Controlling Dimension : Millimeters Note:‘*’is only for -7S DIMENSION (MM) DIMENSION (INCH) SYMBOL MIN. NOM. A MAX. MIN. 1.20 0.15 0.002 1.05 0.037 0.45 0.21 0.012 NOM. MAX. 0.047 A1 0.05 A2 b 0.95 c 0.12 D E 22.09 22.22 22.35 0.870 0.875 0.880 10.03 10.16 10.29 0.395 0.400 0.405 HE 11.56 11.76 11.96 0.455 0.463 0.471 0.30 e L L1 1.00 0.50 ZD 0.008 0.031 0.60 0.016 0.80 Y 0.041 0.018 0.005 0.80 0.40 0.006 0.039 0.020 0.024 0.031 0.1 (*0.08) 0.004 (*0.00315) 0.71 0.028 - 42 - Publication Release Date: Oct. 19, 2011 Revision A03 W9864G6JH 13. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A01 Mar. 12, 2010 All Initial formally data sheet A02 Aug. 31, 2010 15 Revise -6I parts tRP and tRCD value from 18nS to 15nS A03 Oct. 19, 2011 3, 4, 13~15 Added -6A automotive grade parts Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 43 - Publication Release Date: Oct. 19, 2011 Revision A03