SLLS368E − JULY 1999 − REVISED JUNE 2001 D Meets or Exceeds the Requirements of D D D D D D D D D D ANSI EIA/TIA-644 Standard for Signaling Rates† up to 400 Mbps Operates With a Single 3.3-V Supply −2-V to 4.4-V Common-Mode Input Voltage Range Differential Input Thresholds <50 mV With 50 mV of Hysteresis Over Entire Common-Mode Input Voltage Range Integrated 110-Ω Line Termination Resistors Offered With the LVDT Series Propagation Delay Times 4 ns (typ) Active Fail Safe Assures a High-Level Output With No Input Recommended Maximum Parallel Rate of 100 M-Transfers/s Outputs High-Impedance With VCC <1.5 V Available in Small-Outline Package With 1,27 mm Terminal Pitch Pin-Compatible With the AM26LS32, MC3486, or µA9637 NOT RECOMMENDED FOR NEW DESIGNS For Replacement Use SN65LVDS32B or SN65LVDT32B SN65LVDS32A, SN65LVDT32A Logic Diagram (positive logic) G G D PACKAGE (TOP VIEW) SN65LVDT32A ONLY (4 Places) 1A 1B 1A 1Y G 2Y 2A 2B GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 4B 4A 4Y G 3Y 3A 3B 1Y 1B 2A 2Y 2B 3A 3Y 3B 4A 4Y 4B For Replacement Use SN65LVDS3486B or SN65LVDT3486B SN65LVDS3486A, SN65LVDT3486A Logic Diagram (positive logic) D PACKAGE (TOP VIEW) description This family of differential line receivers offers improved performance and features that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS is defined in the TIA/EIA-644 standard. This improved performance represents the second generation of receiver products for this standard, providing a better overall solution for the cabled environment. The next generation family of products is an extension to TI’s overall product portfolio and is not necessarily a replacement for older LVDS receivers. 1B 1A 1Y 1,2EN 2Y 2A 2B GND SN65LVDT3486A 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC ONLY (4 Places) 1A 4B 4A 1B 1,2EN 4Y 2A 3,4EN 3Y 2B 3A 3A 3B 3B 3,4EN 4A 1Y 2Y 3Y 4Y 4B Improved features include an input common- For Replacement Use SN65LVDS9637B or SN65LVDT9637B mode voltage range 2 V wider than the minimum SN65LVDS9637A, SN65LVDT9637A required by the standard. This will allow longer D PACKAGE Logic Diagram cable lengths by tripling the allowable ground (TOP VIEW) (positive logic) noise tolerance to 3 V between a driver and VCC 1 8 1A receiver. 1Y 2Y GND 2 7 3 6 4 5 1B 2A 2B 1A 1Y 1B SN65LVDT9637A ONLY 2A 2Y 2B Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second) Copyright 2001, Texas Instruments Incorporated !"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2 #++ )#!#"($(!%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLLS368E − JULY 1999 − REVISED JUNE 2001 description (continued) Precise control of the differential input voltage thresholds now allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than ±50 mV over the full input common-mode voltage range. The high-speed switching of LVDS signals almost always necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available for multidrop or other termination circuits. The receivers also include a (patent pending) fail-safe circuit that will provide a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. This prevents noise from being received as valid data under these fault conditions. This feature may also be used for wired-OR bus signaling. The intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A, SN65LVDT3486A, SN65LVDS9637A, and SN65LVDT9637A are characterized for operation from -40°C to 85°C. Function Tables SN65LVDS32A and SN65LVDT32A DIFFERENTIAL INPUT ENABLES OUTPUT A-B G G Y VID ≥ -70 mV H X X L H H -100 mV < VID ≤ -70 mV H X X L ? ? VID ≤ -100 mV H X X L L L X L H Z Open H X X L H H H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate SN65LVDS3486A and SN65LVDT3486A DIFFERENTIAL INPUT ENABLES OUTPUT A-B EN Y VID ≥ -70 mV -100 mV < VID ≤ -70 mV H H H ? VID ≤ -100 mV X H L L Z Open H H H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLLS368E − JULY 1999 − REVISED JUNE 2001 Function Tables (Continued) SN65LVDS9637A and SN65LVDT9637A DIFFERENTIAL INPUT OUTPUT A-B Y VID ≥ -70 mV -100 mV < VID ≤ -70 mV H VID ≤ -100 mV Open L H = high level, ? H L = low level, ? = indeterminate equivalent input and output schematic diagrams VCC Attenuation Network A Input 7V Attenuation Network Attenuation Network VCC B Input 7V 7V 7V LVDT Only 110 Ω VCC VCC 300 kΩ (G Only) Enable Inputs 50 Ω 37 Ω Y Output 7V 7V 300 kΩ (EN and G Only) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLLS368E − JULY 1999 − REVISED JUNE 2001 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V Voltage range: Enables or Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 3 V A or B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −4 V to 6 V Bus-pin (A, B) electrostatic discharge (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. 2. Tested in accordance with MIL-STD-883C Method 3015.7. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING OPERATING FACTOR‡ ABOVE TA = 25°C TA = 85°C POWER RATING D8 725 mW 5.8 mW/°C 377 mW D16 950 mW 7.6 mW/°C 494 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. recommended operating conditions Supply voltage, VCC High-level input voltage, VIH Enables Low-level input voltage, VIL Enables MIN NOM MAX 3 3.3 3.6 2 UNIT V V 0.8 V Magnitude of differential input voltage, VID 0.1 3 V Common-mode input voltage, VIC −2 4.4 V Operating free-air temperature, TA −40 85 °C 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLLS368E − JULY 1999 − REVISED JUNE 2001 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VITH1 VITH2 Positive-going differential input voltage threshold Negative-going differential input voltage threshold VIB =-2 V or 4.4 V, See Figure 1 −50 VITH3 Differential input fail-safe voltage threshold See Figure 2 and Table 1 −70 VID(HYS) Differential input voltage hysteresis, VITH1 - VITH2 VOH VOL ICC ‘32A or ‘3486A G or EN at VCC, Steady-state V 0.4 No load, 16 23 1.1 5 Steady-state Other input open ±20 Other input open ±20 VI =-2 V, VI = 4.4 V, Other input open ±40 Other input open ±40 VI = 0 V, VI =2.4 V, Other input open ±40 Other input open ±40 VI =-2 V, VI = 4.4 V, Other input open ±80 Other input open ±80 SN65LVDS VID= 100 mV, See Figure 1 VIC= −2 V or 4.4 V, SN65LVDT VID= 0.4 V, VID= −0.4 V, VIC= −2 V or 4.4 V VIC= −2 V or 4.4 V II(OFF) Power-off input current (A or B inputs) IIH IIL High-level input current (enables) 8 IOZ High-impedance output current CIN Input capacitance, A or B input to GND † All typical values are at 25°C and with a 3.3 V supply. µA A 3.1 4.5 mA −3.1 −4.5 mA VA or VB =−2 V or 4.4 V, VCC= 0 V ±50 • DALLAS, TEXAS 75265 µA A µA ±30 POST OFFICE BOX 655303 mA 12 VA or VB =0 or 2.4 V, VCC= 0 V VI = 0.4 sin (4E6πt) + 0.5 V V ±2 A µA VIH = 2 V VIL = 0.8 V Low-level input current (enables) mV mV VI = 0 V, VI =2.4 V, SN65LVDT IID −100 No load, Input current (A or B inputs) Differential input current (IIA - IIB) mV 2.4 G or EN at GND SN65LVDS UNIT 50 IOH = −8 mA IOL = 8 mA Low-level output voltage ‘9637A II MAX 50 High-level output voltage Supply current TYP† 5 10 µA 10 µA ±10 µA pF 5 SLLS368E − JULY 1999 − REVISED JUNE 2001 switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT tPLH tPHL Propagation delay time, low-to-high-level output 2.5 4 6 ns Propagation delay time, high-to-low-level output 2.5 4 6 ns td1 td2 Delay time, fail-safe deactivate time 6.1 ns 1 µs tsk(p) tsk(o) Pulse skew (|tPHL1 – tPLH1|) Output skew§ tsk(pp) tr Part-to-part skew‡ Output signal rise time 600 ps tf tPHZ Output signal fall time 600 ps Propagation delay time, high-level-to-high-impedance output 5.5 9 ns tPLZ tPZH Propagation delay time, low-level-to-high-impedance output 4.4 9 ns 3.8 9 ns Delay time, fail-safe activate time 0.3 CL = 10 pF, See Figure 3 200 ps 150 ps 1 See Figure 4 Propagation delay time, high-impedance -to-high-level output ns tPZL Propagation delay time, high-impedance-to-low-level output 7 9 ns † All typical values are at 25°C and with a 3.3 V supply. ‡ tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. § tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all receivers of a single device with all of their inputs driven together. PARAMETER MEASUREMENT INFORMATION IIA A VO Y VID B VIA (VIA + VIB)/2 VIC IIB VO VIB Figure 1. Voltage and Current Definitions 2 µs 1 µs VID VIA VIB CL < 50 pF VO VID 0.2 V VIT− VIT+ −0.2 V VO Figure 2. VITH3 Input Voltage Threshold Test Circuit and Definitions 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLLS368E − JULY 1999 − REVISED JUNE 2001 PARAMETER MEASUREMENT INFORMATION Table 1. Receiver Minimum and Maximum Fail-Safe Input Threshold Test Voltages APPLIED VOLTAGES† RESULTANT INPUTS VIA (mV) −2050 VIB (mV) −1950 VID (mV) −100 VIC (mV) −2000 Output −2035 −1965 −70 −2000 H 4350 4450 −100 4400 L 4365 4435 −70 4400 H L † These voltages are applied for a minimum of 1 µs. VID VIA VO CL = 10 pF VIB VIA 1.4 V VIB 1V 0.4 V VID >1 µs 0V −0.2 V −0.4 V tPHL tPLH 80% VO 20% tf tD1 tD2 VOH 1.4 V VOL 80% 20% tr NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 3. Timing Test Circuit and Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SLLS368E − JULY 1999 − REVISED JUNE 2001 PARAMETER MEASUREMENT INFORMATION 1.2 V B 500 Ω A 10 pF Inputs ± VO G VTEST G 1,2,EN, or 3,4, EN NOTE B: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. 2.5 V VTEST A 1V 2V 1.4 V 0.8 V G, 1,2EN,or 3,4EN 2V 1.4 V 0.8 V tPLZ G tPLZ tPZL tPZL Y VTEST 2.5 V 1.4 V VOL +0.5 V VOL 0 1.4 V A G, 1,2EN,or 3,4EN 2V 1.4 V 0.8 V G 2V 1.4 V 0.8 V tPHZ tPHZ tPZH tPZH Y VOH VOH −0.5 V 1.4 V 0 Figure 4. Enable/Disable Time Test Circuit and Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLLS368E − JULY 1999 − REVISED JUNE 2001 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4 VCC = 3.3 V TA = 25°C VOH − High-Level Output Voltage − V VOL − Low-Level Output Voltage − V 5 4 3 2 1 0 0 20 40 60 80 VCC = 3.3 V TA = 25°C 3 2 1 0 −100 100 IOL − Low-Level Output Current − mA −80 0 5 4.5 VCC = 3 V VCC = 3.3 V VCC = 3.6 V 3.5 0 50 TA − Free-Air Temperature − °C HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE t PHL− High-To-Low Propagation Delay Time − ns t PLH − Low-To-High Propagation Delay Time − ns −20 Figure 6 LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 3 −50 −40 IOH − High-Level Output Current − mA Figure 5 4 −60 100 5 4.5 VCC = 3 V 4 VCC = 3.3 V VCC = 3.6 V 3.5 3 −50 Figure 7 0 50 TA − Free-Air Temperature − °C 100 Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SLLS368E − JULY 1999 − REVISED JUNE 2001 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY 140 I CC − Supply Current − mA 120 VCC = 3.3 V 100 80 VCC = 3.6 V 60 VCC = 3 V 40 20 0 0 150 100 f − Switching Frequency − MHz Figure 9 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 200 SLLS368E − JULY 1999 − REVISED JUNE 2001 APPLICATION INFORMATION 0.01 µF 1 VCC 16 0.1 µF (see Note A) 1B 100 Ω 2 3 VCC 4 5 6 1A 4B 2Y 4Y G 2A 100 Ω 7 4A 2B 3Y 3A 5V 1N645 (2 places) 15 1Y G ≈3.6 V 14 100 Ω (see Note B) 13 12 11 See Note C 10 100 Ω 8 GND 3B 9 NOTES: A. Place a 0.1 µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground plane. The capacitor should be located as close as possible to the device terminals. B. The termination resistance value should match the nominal characteristic impedance of the transmission media with ±10%. C. Unused enable inputs should be tied to VCC or GND as appropriate. Figure 10. Operation with 5-V Supply related information IBIS modeling is available for this device. Please contact the local TI sales office or the TI Web site at www.ti.com for more information. For more application guidelines, please see the following documents: D D D D D D Low-Voltage Differential Signalling Design Notes (TI literature number SLLA014) Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038) Reducing EMI With LVDS (SLLA030) Slew Rate Control of LVDS Circuits (SLLA034) Using an LVDS Receiver With RS-422 Data (SLLA031) Evaluating the LVDS EVM (SLLA033) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SLLS368E − JULY 1999 − REVISED JUNE 2001 APPLICATION INFORMATION abstract terminated failsafe A differential line receiver commonly has a fail-safe circuit to prevent it from switching on input noise. Current LVDS fail-safe solutions require either external components with subsequent reduction in signal quality or integrated solutions with limited application. This family of receivers has a new integrated fail-safe that solves the limitations in present solutions. A detailed theory of operation is presented in the application note The Active Fail-Safe Feature of the SN65LVDS32A, literature number SLLA082. Figure 11 shows one receiver channel with active fail-safe. It consists of a main receiver that can respond to a high-speed input differential signal. Also connected to the input pair are two fail-safe receivers that form a window comparator. The window comparator has a much slower response than the main receiver and detects when the input differential falls below 80 mV. A 600-ns fail-safe timer filters the window comparator outputs. When fail-safe is asserted, the fail-safe logic drives the main receiver output to logic high. Output Buffer Main Receiver A B + _ R Reset Failsafe Timer A > B + 80 mV + _ Failsafe B > A + 80 mV + _ Window Comparator Figure 11. Receiver With Terminated Failsafe 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLLS368E − JULY 1999 − REVISED JUNE 2001 APPLICATION INFORMATION test conditions D VCC = 3.3 V D TA = 25°C (ambient temperature) D All four channels switching simultaneously with NRZ data. Scope is pulse-triggered simultaneously with NRZ data. equipment D Tektronix PS25216 programmable power supply D Tektronix HFS 9003 stimulus system D Tektronix TDS 784D 4-channel digital phosphor oscilloscope − DPO Tektronix PS25216 Programmable Power Supply Tektronix HFS 9003 Stimulus System Trigger Tektronix TDS 784D 4-Channel Digital Phosphor Oscilloscope − DPO Bench Test Board Figure 12. Equipment Setup Figure 13. Typical Eye Pattern SN65LVDS32A 100 Mbit/s POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SLLS368E − JULY 1999 − REVISED JUNE 2001 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°−ā 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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