SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386 SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999 D D D D D D D D D D D Eight (‘388) or Sixteen (‘386) Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard Integrated 110-Ω Line Termination Resistors on LVDT Products Designed for Signaling Rates† Up To 630 Mbps SN65 Version’s Bus-Terminal ESD Exceeds 15 kV Operates From a Single 3.3-V Supply Typical Propagation Delay Time of 2.6 ns Output Skew 100 ps (Typ) Part-To-Part Skew is Less Than 1 ns LVTTL Levels are 5-V Tolerant Open-Circuit Fail Safe Flow-Through Pin Out Packaged in Thin Shrink Small-Outline Package With 20-mil Terminal Pitch SN65LVDS388, SN75LVDS388 SN65LVDT388, SN75LVDT388 DBT PACKAGE (TOP VIEW) description The ‘LVDS388 and ‘LVDT388 (T designates integrated termination) are eight and the ‘LVDS386 and ‘LVDT386 sixteen differential line receivers respectively that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail. Any of the eight or sixteen differential receivers will provide a valid logical output state with a ±100 mV differential input voltage within the input commonmode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. Additionally, the high-speed switching of LVDS signals almost always require the use of a line impedance matching resistor at the receiving end of the cable or transmission media. The LVDT products eliminate this external resistor by integrating it with the receiver. A1A A1B A2A A2B NC B1A B1B B2A B2B NC C1A C1B C2A C2B NC D1A D1B D2A D2B 1 38 2 37 3 36 4 35 5 34 6 33 7 32 8 31 9 30 10 29 11 28 12 27 13 26 14 25 15 24 16 23 17 22 18 21 19 20 GND VCC ENA A1Y A2Y ENB B1Y B2Y GND VCC GND C1Y C2Y ENC D1Y D2Y END VCC GND SN65LVDS386, SN75LVDS386 SN65LVDT386, SN75LVDT386 DGG PACKAGE (TOP VIEW) A1A A1B A2A A2B A3A A3B A4A A4B B1A B1B B2A B2B B3A B3B B4A B4B C1A C1B C2A C2B C3A C3B C4A C4B D1A D1B D2A D2B D3A D3B D4A D4B 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 GND VCC VCC GND ENA A1Y A2Y A3Y A4Y ENB B1Y B2Y B3Y B4Y GND VCC VCC GND C1Y C2Y C3Y C4Y ENC D1Y D2Y D3Y D4Y END GND VCC VCC GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second) Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386 SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999 description (continued) The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed circuit board traces, backplanes, or cables. The large number of receivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. When used with its companion, 8- or 16-channel driver, the SN65LVDS389 or SN65LVDS387, over 300 million data transfers per second in single-edge clocked systems are possible with very little power. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.) Available Options Temperature Range Number of Receivers Bus-Pin ESD SN65LVDS386DGG –40_C to 85_C 16 15 kV SN65LVDT386DGG –40_C to 85_C 16 15 kV SN75LVDS386DGG 0_C to 70_C 16 4 kV SN75LVDT386DGG 0_C to 70_C 16 4 kV SN65LVDS388DBT –40_C to 85_C 8 15 kV SN65LVDT388DBT –40_C to 85_C 8 15 kV SN75LVDS388DBT 0_C to 70_C 8 4 kV SN75LVDT388DBT 0_C to 70_C 8 4 kV Part number logic diagram (positive logic) ’LVDx386 ’LVDT386 ONLY 1A ’LVDx388 1Y 1B ’LVDT388 ONLY 2A 2B EN 3A 1A 2Y 1Y 1B EN 2A 3Y 3B 4A 2Y 2B 4Y 4B Function Table SNx5LVD386/388 and SNx5LVDT386/388 DIFFERENTIAL INPUT ENABLES OUTPUT A-B EN Y VID ≥ 100 mV -100 mV < VID ≤ 100 mV H H H ? VID ≤ -100 mV X H L L Z Open H H H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386 SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999 equivalent input and output schematic diagrams VCC VCC 300 kΩ VCC 300 kΩ 100 Ω 5Ω EN Y Output A Input B Input 7V 7V 300 kΩ 7V 7V 110 Ω ’LVDT Devices Only absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4 V Voltage range: Enables or Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 2 V A or B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4 V Electrostatic discharge: (see Note 2) SN65’ (A, B, and GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:15 kV, B: 700 V SN65’ (All pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A: 8 kV, B:600 V SN75’ (A, B, and GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2, A:4 kV, B: 400 V SN75’ (All pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2, A: 2 kV, B:200 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. 2. Tested in accordance with MIL-STD-883C Method 3015.7. DISSIPATION RATING TABLE DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING PACKAGE TA ≤ 25°C DBT 1071 mW 8.5 mW/°C 688 mW 556 mW DGG 2094 mW 16.7 mW/°C 1342 mW 1089 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386 SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999 recommended operating conditions MIN NOM Supply voltage, VCC 3 3.3 High-level input voltage, VIH 2 MAX 0.1 |V ID 2 Common–mode input voltage, VIC (see Figure 4) Operating O erating free-air tem temperature erature, TA 4 POST OFFICE BOX 655303 | 2.4 0.8 V 0.6 V * |V2ID| V °C °C SN75’ 0 VCC – 0.8 70 SN65’ – 40 85 • DALLAS, TEXAS 75265 V V Low-level input voltage, VIL Magnitude of differential input voltage, VID UNIT 3.6 SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386 SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999 electrical characteristics over recommended operating conditions (unless otherwise noted). PARAMETER TEST CONDITIONS VITH+ VITH– Positive–going differential input voltage threshold VOH VOL High–level output voltage ICC II Negative–going differential input voltage threshold See Figure 1 and Table 1 IOH = –8 mA IOL = 8 mA Low–level output voltage Enabled, Supply current MIN TYP† 2.4 No load VI = 0 V VI = 2.4 V ’LVDT VI = 0 V, other input open VI = 2.4 V, other input open Differential input current |IIA – IIB| ‘LVDS IID Differential input current (IIA – IIB) ‘LVDT II(OFF) II(OFF) Power–off Input current (A or B inputs) ‘LVDS Power–off Input current (A or B inputs) ‘LVDT IIH IIL High–level input current (enables) Low–level input current (enables) IOZ High impedance output current High–impedance CIN Input Capacitance, A or B input to GND Z(t) Termination impedance † All typical values are at 25°C and with a 3.3 V supply. mV mV 3 V 0.2 0.4 50 70 3 ’LVDS IID UNIT 100 –100 Disabled Input current (A or B inputs) MAX –13 –1.2 VIA= 0 V, VIA= 2.4 V, VIA= 0.2 V, VIA= 2.4 V, VCC = 0 V, VIB = 0.1V, VIB = 2.3 V VIB = 0V, VIB = 2.2 V VI=2.4 V VCC = 0 V, VIH = 2 V VI=2.4 V V mA –20 –3 –40 µA –2.4 ±2 µA 2.2 mA ±20 µA ±40 µA 10 µA VIL = 0.8 V VO = 0 V 10 µA VO = 3.6 V VID = 0.4 sin 2.5E09 t V 10 VID = 0.4 sin 2.5E09 t V 1.5 12 ±1 5 88 µA pF 132 Ω switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX 1 2.6 4 ns UNIT tPLH tPHL Propagation delay time, low-to-high-level output 1 2.5 4 ns tr tf Differential output signal rise time 500 800 1200 ps Differential output signal fall time 500 800 1200 ps tsk(p) Pulse skew (|tPHL – tPLH|) 150 600 ps tsk(o) tsk(pp) Output skew‡ 100 400 ps 1 ns tPZH tPZL Propagation delay time, high-impedance-to-high-level output 7 15 ns Propagation delay time, high-impedance-to-low-level output 7 15 ns tPHZ tPLZ Propagation delay time, high-level-to-high-impedance output 7 15 ns 7 15 ns Propagation delay time, high-to-low-level output See Figure 2 g Part-to-part skew§ See Figure 3 Propagation delay time, low-level-to-high-impedance output † All typical values are at 25°C and with a 3.3 V supply. ‡ tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all drivers of a single device with all of their inputs connected together. § tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386 SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION A V IA ) VIB VID 2 R VIA VIC B VO VIB Figure 1. Voltage Definitions Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages Applied Voltages 6 Resulting Differential Input Voltage Resulting Common– Mode Input Voltage VIC 1.2 V VIA 1.25 V VIB 1.15 V VID 100 mV 1.15 V 1.25 V –100 mV 1.2 V 2.4 V 2.3 V 100 mV 2.35 V 2.3 V 2.4 V –100 mV 2.35 V 0.1 V 0V 100 mV 0.05 V 0V 0.1 V –100 mV 0.05 V 1.5 V 0.9 V 600 mV 1.2 V 0.9 V 1.5 V –600 mV 1.2 V 2.4 V 1.8 V 600 mV 2.1 V 1.8 V 2.4 V –600 mV 2.1 V 0.6 V 0V 600 mV 0.3 V 0V 0.6 V –600 mV 0.3 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386 SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION VID VIA VIB CL 10 pF VO VIA 1.4 V VIB 1V VID 0.4 V 0V – 0.4 V tPHL VO tPLH VOH 2.4 V 1.4 V 0.4 V VOL tf tr NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, Pulse Repetition Rate (PRR) = 50 Mpps, Pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 2. Timing Test Circuit and Wave Forms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386 SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION 1.2 V B 500 Ω A Inputs EN CL 10 pF + – VO VTEST NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. 2.5 V VTEST A 1V 2V 1.4 V EN 0.8 V tPZL tPLZ 2.5 V 1.4 V Y VOL +0.5 V VOL 0V VTEST A 1.4 V 2V EN 1.4 V 0.8 V tPZH Y tPHZ VOH 1.4 V VOH –0.5 V 0V Figure 3. Enable/Disable Time Test Circuit and Wave Forms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386 SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999 TYPICAL CHARACTERISTICS LVDx388 SUPPLY CURRENT vs SWITCHING FREQUENCY COMMON-MODE INPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE 200 2.5 180 Max at VCC = 3 V 2.0 160 I CC – Supply Current – mA VIC – Common-Mode Input Voltage – V Max at VCC > 3.15 V 1.5 1.0 VCC = 3.6 V 140 120 VCC = 3 V 100 80 VCC = 3.3 V 60 40 0.5 Minimum 20 0 0 0 0.1 0.2 0.3 0.4 0.5 0 0.6 20 40 60 Figure 4 Figure 5 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4.0 5.0 3.5 4.5 VOL – Low-Level Output Voltage – V VOH – High-Level Output Voltage – V HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 3.0 2.5 2.0 1.5 1.0 0.5 0 –70 80 100 120 140 160 180 200 f – Switching Frequency – MHz |VID| – Differential Input Voltage – V 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 –60 –50 –40 –30 –20 –10 0 IOH – High-Level Output Current – mA 0 0 10 20 30 40 50 60 70 80 IOL – Low-Level Output Current – mA Figure 6 Figure 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386 SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999 TYPICAL CHARACTERISTICS HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 3.0 t PHL – High-To-Low Propagation Delay Time – ns t PLH – Low-To-High Propagation Delay Time – ns LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 2.9 2.8 VCC = 3 V 2.7 2.6 VCC = 3.6 V 2.5 2.4 VCC = 3.3 V 2.3 2.2 2.1 2 –50 –30 –10 10 30 50 70 90 Ta – Free-Air Temperature – °C 3.0 2.9 2.8 2.7 2.6 2.5 VCC = 3 V 2.3 2.2 VCC = 3.3 V 2.1 2 –50 –30 –10 10 Figure 9 POST OFFICE BOX 655303 30 50 TA – Free-Air Temperature – °C Figure 8 10 VCC = 3.6 V 2.4 • DALLAS, TEXAS 75265 70 90 SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386 SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999 APPLICATION INFORMATION Host Power Balanced Interconnect Target Power T Host Controller DBn DBn T DBn–1 Target Controller DBn–1 T DBn–2 DBn–2 T DBn–3 DBn–3 T DB2 DB2 T DB1 DB1 T DB0 DB0 T TX Clock RX Clock LVDx386 or LVDx388 LVDS Drivers Indicates twisting of the conductors. T Indicates the line termination circuit. Figure 10. Typical Application Schematic POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386 SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999 APPLICATION INFORMATION fail safe One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how it handles the open-input circuit situation, however. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver will pull each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 10. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high-level regardless of the differential input voltage. VCC 300 kΩ 300 kΩ A Rt = 100 Ω (Typ) Y B VIT ≈ 2.3 V Figure 11. Open-Circuit Fail Safe of the LVDS Receiver It is only under these conditions that the output of the receiver will be valid with less than a 100 mV differential input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeat the pull-up currents from the receiver and the fail-safe feature. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386 SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999 MECHANICAL DATA DBT (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 30 PINS SHOWN 0,50 0,27 0,17 30 16 0,08 M 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 15 0°– 8° 0,75 0,50 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 28 30 38 44 50 A MAX 7,90 7,90 9,80 11,10 12,60 A MIN 7,70 7,70 9,60 10,90 12,40 DIM 4073252/D 09/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386 SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999 MECHANICAL DATA DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. 14 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated