TI SN55LVDS31J

SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS261F – JULY 1997 – REVISED MARCH 2000
The
SN55LVDS31,
SN65LVDS31,
SN65LVDS3487, and SN65LVDS9638 are
differential line drivers that implement the
electrical characteristics of low-voltage differential
signaling (LVDS). This signaling technique lowers
the output voltage levels of 5 V differential
standard levels (such as TIA/EIA-422B) to reduce
the power, increase the switching speeds, and
allow operation with a 3.3-V supply rail. Any of the
four current-mode drivers will deliver a minimum
differential output voltage magnitude of 247 mV
into a 100-Ω load when enabled.
The intended application of these devices and
signaling technique is for point-to-point baseband
data transmission over controlled impedance
media of approximately 100 Ω. The transmission
media may be printed-circuit board traces,
backplanes, or cables. The ultimate rate and
distance of data transfer is dependent upon the
attenuation characteristics of the media and the
noise coupling to the environment.
14
4
13
5
12
6
11
7
10
8
9
VCC
4A
4Y
4Z
G
3Z
3Y
3A
3
2
1
20 19
4A
VCC
SN55LVDS31FK
(TOP VIEW)
1Z
4
18 4Y
G
5
17 4Z
NC
6
16 NC
2Z
7
15 G
2Y
8
14 3Z
9
10 11 12 13
3Y
description
3
3A
D
15
NC
D
D
16
2
NC
D
1
1A
D
D
D
1A
1Y
1Z
G
2Z
2Y
2A
GND
GND
D
SN55LVDS31 . . . J OR W
SN65LVDS31D
(Marked as LVDS31 or 65LVDS31)
(TOP VIEW)
1Y
D
Meets or Exceeds the Requirements of
ANSI TIA/EIA-644 Standard
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100-Ω Load
Typical Output Voltage Rise and Fall Times
of 500 ps (400 Mbps)
Typical Propagation Delay Times of 1.7 ns
Operates From a Single 3.3-V Supply
Power Dissipation 25 mW Typical per Driver
at 200 MHz
Driver at High Impedance When Disabled or
With VCC = 0
Bus-Terminal ESD Protection Exceeds 8 kV
Low-Voltage TTL (LVTTL) Logic Input
Levels
Pin-Compatible With the AM26LS31,
MC3487, and µA9638
2A
D
SN65LVDS3487D
(Marked as LVDS3487 or 65LVDS3487)
(TOP VIEW)
1A
1Y
1Z
1,2EN
2Z
2Y
2A
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4A
4Y
4Z
3,4EN
3Z
3Y
3A
SN65LVDS9638D (Marked as DK638 or LVDS38)
SN65LVDS9638DGN (Marked as L38)
(TOP VIEW)
The SN65LVDS31, SN65LVDS3487, and
SN65LVDS9638 are characterized for operation
from – 40°C to 85°C. The SN55LVDS31 is
characterized for operation from – 55°C to 125°C.
VCC
1A
2A
GND
1
8
2
7
3
6
4
5
1Y
1Z
2Y
2Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS261F – JULY 1997 – REVISED MARCH 2000
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(D)
– 40°C to 85°C
SN65LVDS9638D
SN65LVDS9638DGN
—
—
—
—
—
SN55LVDS31FK
SN55LVDS31J
SN55LVDS31W
MSOP
(DGN)
CHIP CARRIER
(FK)
CERAMIC DIP
(J)
FLAT PACK
(W)
SN65LVDS31D
—
—
—
—
SN65LVDS3487D
—
—
—
—
– 55°C to 125°C
logic symbol†
’LVDS31 logic diagram (positive logic)
SN55LVDS31, SN65LVDS31
G
G
1A
2A
3A
4A
4
12
≥1
G
EN
G
1A
1
7
2
3
6
5
9
10
11
15
14
13
1Y
1Z
2A
2Y
2Z
3A
12
1
7
3Z
4A
4Y
4Z
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2
3
6
5
9
10
11
3Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
2
4
15
14
13
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS261F – JULY 1997 – REVISED MARCH 2000
logic symbol†
’LVDS3487 logic diagram (positive logic)
SN65LVDS3487
1, 2EN
1A
2A
3, 4EN
3A
4A
4
EN
2
1
3
6
7
12
5
2Y
11
14
15
13
6
7
2A
5
2Z
3Y
11
1Z
2Y
2Z
3Y
3Z
12
3,4EN
3Z
14
15
4A
4Y
10
9
3A
10
1Y
4
1,2EN
EN
9
3
1Y
1Z
2
1
1A
13
4Y
4Z
4Z
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
logic symbol†
’LVDS9638 logic diagram (positive logic)
SN65LVDS9638
1A
2A
2
3
8
7
6
5
1Y
1A
2
8
7
1Y
1Z
1Z
2Y
2A
2Z
3
6
5
2Y
2Z
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS261F – JULY 1997 – REVISED MARCH 2000
Function Tables
SN55LVDS31, SN65LVDS31
INPUT
A
ENABLES
OUTPUTS
G
G
Y
H
H
X
H
L
L
H
X
L
H
H
X
L
H
L
L
X
L
L
H
X
L
H
Z
Z
Open
H
X
L
H
Open
X
L
L
H
H = high level, L = low level,
Z = high impedance (off)
Z
X = irrelevant,
SN65LVDS3487
INPUT
A
ENABLE
EN
OUTPUTS
Y
Z
H
H
H
L
L
H
L
H
X
L
Z
Z
OPEN
H
L
H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off)
SN65LVDS9638
INPUT
A
Y
Z
H
H
L
L
L
H
L
H
OPEN
H = high level,
4
OUTPUTS
POST OFFICE BOX 655303
L = low level
• DALLAS, TEXAS 75265
SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS261F – JULY 1997 – REVISED MARCH 2000
equivalent input and output schematic diagrams
EQUIVALENT OF EACH A INPUT
EQUIVALENT OF G, G, 1,2EN OR
3,4EN INPUTS
VCC
VCC
50 Ω
TYPICAL OF ALL OUTPUTS
VCC
50 Ω
Input
Input
7V
10 kΩ
5Ω
Y or Z
Output
7V
300 kΩ
7V
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65_C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D (8)
725 mW
5.8 mW/°C
464 mW
377 mW
—
D (16)
950 mW
7.6 mW/°C
608 mW
494 mW
—
DGN
2.14 W
17.1 mW/°C
1.37 W
1.11 W
—
FK
1375 mW
11.0 mW/°C
880 mW
715 mW
275 mW
J
1375 mW
11.0 mW/°C
880 mW
715 mW
275 mW
W
1000 mW
8.0 mW/°C
640 mW
520 mW
200 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
MIN
NOM
MAX
Supply voltage, VCC
3
3.3
3.6
High-level input voltage, VIH
2
Low-level input voltage, VIL
POST OFFICE BOX 655303
SN65 prefix
– 40
85
SN55 prefix
– 55
125
• DALLAS, TEXAS 75265
V
V
0.8
Operating free-air
free air temperature,
temperature TA
UNIT
V
°C
5
SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS261F – JULY 1997 – REVISED MARCH 2000
SN65LVDSxxxx electrical characteristics over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VOD
Differential output voltage magnitude
∆VOD
Change in differential output voltage magnitude
between logic states
VOC(SS)
Steady-state common-mode output voltage
See Figure 3
∆VOC(SS)
Change in steady-state common-mode output voltage
between logic states
See Figure
g
3
VOC(PP)
Peak-to-peak common-mode output voltage
247
RL = 100 Ω,
SN65LVDS31
SN65LVDS31,
’3487
ICC
Supply
Su
ly current
SN65LVDS9638
IIH
IIL
IOZ
IO(OFF)
High-impedance output current
1.125
1.2
–50
454
mV
50
mV
1.375
mV
50
V
50
150
mV
9
20
mA
25
35
mA
Enabled,
VI = 0.8 or 2 V,
Enabled
RL = 100 Ω,
VI = 0 or VCC,
Disabled
0.25
1
mA
No load
4.7
8
mA
9
13
mA
4
20
µA
RL = 100 Ω
VO(Y) or VO(Z) = 0
VOD = 0
VO = 0 or 2.4 V
VCC = 0,
Power-off output current
340
– 50
VIH = 2
VIL = 0.8 V
Low-level input current
Short circuit output current
Short-circuit
See Figure 2
UNIT
VI = 0.8 V or 2 V,
No load
VI = 0.8
0 8 V or 2 V
High-level input current
IOS
SN65LVDS31,
’3487, ’ 9638
MIN TYP†
MAX
0.1
10
µA
–4
– 24
mA
± 12
mA
±1
µA
±1
µA
VO = 2.4 V
Input capacitance
CI
† All typical values are at TA = 25°C and with VCC = 3.3 V.
3
pF
SN65LVDSxxxx switching characteristics over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
tpLH
tpHL
Propagation delay time, low-to-high-level output
tr
tf
Differential output signal rise time (20% to 80%)
tsk(p)
tsk(o)
Pulse skew (|tPHL – tPLH|)
tsk(pp)
tpZH
Part-to-part skew§
tpZL
tpHZ
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-to-low-level output
RL = 100 Ω,,
See Figure 2
Differential output signal fall time (80% to 20%)
Channel-to-channel output skew‡
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-level-to-high-impedance output
See Figure 4
CL = 10 pF,,
SN65LVDS31,
’3487, ’ 9638
MIN TYP†
MAX
UNIT
0.5
1.4
2
ns
1
1.7
2.5
ns
0.4
0.5
0.6
ns
0.4
0.5
0.6
ns
0.3
0.6
ns
0
0.3
ns
800
ps
5.4
15
ns
2.5
15
ns
8.1
15
ns
tpLZ
Propagation delay time, low-level-to-high-impedance output
7.3
15
ns
† All typical values are at TA = 25°C and with VCC = 3.3 V.
‡ tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical specified loads.
§ tsk(pp) is the magnitude of the different in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, same temperature, and have identical packages and test circuits.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS261F – JULY 1997 – REVISED MARCH 2000
SN55LVDS31 electrical characteristics over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VOD
Differential output voltage magnitude
∆VOD
Change in differential output voltage magnitude
between logic states
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output voltage
between logic states
VOC(PP)
Peak-to-peak common-mode output voltage
247
RL = 100 Ω,
See Figure 2
See Figure 3
Enabled,
VI = 0.8 or 2 V,
Enabled
RL = 100 Ω,
VI = 0 or VCC,
VIH = 2
Disabled
IIH
IIL
High-level input current
IOS
Short circuit output current
Short-circuit
IOZ
IO(OFF)
High-impedance output current
VOD = 0
VO = 0 or 2.4 V
Power-off output current
VCC = 0,
1.2
– 50
VI = 0.8 V or 2 V,
No load
Supply current
340
– 50
1.125
ICC
Low-level input current
SN55LVDS31
TYP†
MAX
MIN
VIL = 0.8 V
VO(Y) or VO(Z) = 0
454
mV
50
mV
1.375
V
50
mV
50
150
mV
9
20
mA
25
35
mA
0.25
1
mA
4
20
µA
0.1
10
µA
–4
– 24
mA
± 12
mA
±1
µA
±4
µA
VO = 2.4 V
Input capacitance
CI
† All typical values are at TA = 25°C and with VCC = 3.3 V.
UNIT
3
pF
SN55LVDS31 switching characteristics over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN55LVDS31
MIN TYP†
MAX
UNIT
tpLH
tpHL
Propagation delay time, low-to-high-level output
0.5
1.4
4
ns
Propagation delay time, high-to-low-level output
1
1.7
4.5
ns
tr
tf
Differential output signal rise time (20% to 80%)
0.4
0.5
1
ns
0.4
0.5
1
ns
tsk(p)
tsk(o)
Pulse skew (|tPHL – tPLH|)
0.3
0.6
ns
Channel-to-channel output skew‡
0.3
0.6
ns
tpZH
tpZL
Propagation delay time, high-impedance-to-high-level output
5.4
15
ns
Propagation delay time, high-impedance-to-low-level output
2.5
15
ns
8.1
17
ns
7.3
15
ns
Differential output signal fall time (80% to 20%)
RL = 100 Ω,,
See Figure 2
See Figure 4
tpHZ
Propagation delay time, high-level-to-high-impedance output
tpLZ
Propagation delay time, low-level-to-high-impedance output
† All typical values are at TA = 25°C and with VCC = 3.3 V.
‡ tsk(o) is the maximum delay time difference between drivers on the same device.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CL = 10 pF,,
7
SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS261F – JULY 1997 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
IOY
Y
II
A
Z
VOD
IOZ
VOY
VI
VOC
VOZ
(VOY + VOZ)/2
Figure 1. Voltage and Current Definitions
2V
1.4 V
0.8 V
Input
tPLH
Y
Input
(see Note A)
VOD
Z
tPHL
100 ± 1 %
100%
80%
VOD
CL = 10 pF
(2 Places)
(see Note B)
0
20%
0%
tf
tr
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns.
B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
Y
Input
(see Note A)
49.9 Ω ± 1% (2 Places)
3V
A
A
VOC(PP)
(see Note C)
Z
VOC
CL = 10 pF
(2 Places)
(see Note B)
0
VOC(SS)
VOC
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns.
B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
C. The measurement of VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS261F – JULY 1997 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
49.9 Ω ± 1% (2 Places)
Y
Inputs
(see Note A)
0.8 V or 2 V
Z
1.2 V
G
G
1,2EN or 3,4EN
CL = 10 pF
(2 Places)
(see Note B)
G, 1,2EN,
OR 3,4EN
2V
1.4 V
0.8 V
G
2V
1.4 V
0.8 V
VOY
or
VOZ
tPZH
VOY
VOZ
tPHZ
100%, ≅ 1.4 V A at 2 V, G at VCC and Input to G
or
50%
G at GND and Input to G for ’LVDS31 only
0%, 1.2 V
tPZL
tPLZ
A at 0.8 V, G at VCC and Input to G
100%, 1.2 V
VOZ
or
50%
or
G at GND and Input to G for ’LVDS31 only
0%, ≅ 1 V
VOY
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf < 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns.
B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
Figure 4. Enable and Disable Time Circuit and Definitions
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• DALLAS, TEXAS 75265
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SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS261F – JULY 1997 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
SN55LVDS31, SN65LVDS31
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREQUENCY
1.9
Four Drivers Loaded Per
Figure 3 and Switching
Simultaneously.
I CC – Supply Current – mA
33
t PLH – Low-To-High Propagation Delay Time – ns
35
VCC = 3.6 V
31
29
VCC = 3 V
27
25
VCC = 3.3 V
23
21
19
17
15
50
150
100
200
1.8
1.7
1.6
1.5
VCC = 3.3 V
VCC = 3 V
1.4
1.3
VCC = 3.6 V
1.2
1.1
1
–40
–20
f – Frequency – MHz
0
20
40
60
80
TA – Free-Air Temperature – °C
Figure 5
Figure 6
t PHL – High-To-Low Propagation Delay Time – ns
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
1.9
1.8
VCC = 3 V
1.7
1.6
VCC = 3.3 V
1.5
VCC = 3.6 V
1.4
1.3
1.2
1.1
1
–40
–20
60
80
0
20
40
TA – Free-Air Temperature – °C
Figure 7
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
100
100
SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS261F – JULY 1997 – REVISED MARCH 2000
APPLICATIONS INFORMATION
The devices are generally used as building blocks for high-speed point-to-point data transmission where ground
differences are less than 1 V. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers
approach ECL speeds without the power and dual supply requirements.
TRANSMISSION DISTANCE
vs
SIGNALING RATE
Transmission Distance – m
100
30% Jitter
(see Note A)
10
5% Jitter
(see Note A)
1
24 AWG UTP 96 Ω
(PVC Dielectric)
0.1
10
100
1000
Signaling Rate – Mbps
NOTE A: This parameter is the percentage of distortion of the unit interval (UI) with a pseudo-random data pattern.
Figure 8. Typical Transmission Distance Versus Signaling Rate
1
2
ZO = 100 Ω
3
VCC
4
5
1A
VCC
1Y
4A
1Z
4Y
G
4Z
2Z
G
16
15
3.3 V
0.1 µF
(see Note A)
0.001 µF
(see Note A)
14
ZO = 100 Ω
13
12
See Note B
ZO = 100 Ω
6
7
8
2Y
3Z
2A
3Y
GND
3A
11
10
ZO = 100 Ω
9
NOTES: A. Place a 0.1 µF and a 0.001 µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground
plane. The capacitors should be located as close as possible to the device terminals.
B. Unused enable inputs should be tied to VCC or GND as appropriate.
Figure 9. Typical Application Circuit Schematic
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SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS261F – JULY 1997 – REVISED MARCH 2000
APPLICATIONS INFORMATION
1/4 ’LVDS31
Strb/Data_TX
TpBias on
Twisted-Pair A
Strb/Data_Enable
TP
55 Ω
’LVDS32
5 kΩ
Data/Strobe
55 Ω
3.3 V
TP
20 kΩ
500 Ω
VG on
Twisted-Pair B
1 Arb_RX
500 Ω
20 kΩ
3.3 V
20 kΩ
500 Ω
2 Arb_RX
500 Ω
20 kΩ
3.3 V
7 kΩ
Twisted-Pair B Only
7 kΩ
10 kΩ
Port_Status
3.3 kΩ
NOTES: A.
B.
C.
D.
Resistors are leadless thick-film (0603) 5% tolerance.
Decoupling capacitance is not shown but recommended.
VCC is 3 V to 3.6 V.
The differential output voltage of the ’LVDS31 can exceed that specified by IEEE1394.
Figure 10. 100 Mbps IEEE1394 Transceiver
12
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HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS261F – JULY 1997 – REVISED MARCH 2000
APPLICATIONS INFORMATION
0.01 µF
1
1A
VCC
≈3.6 V
16
5V
0.1 µF
(see Note A)
2
ZO = 100 Ω
3
VCC
4
5
1Y
4A
1Z
4Y
G
4Z
2Z
G
1N645
(2 places)
15
14
ZO = 100 Ω
13
12
See Note B
ZO = 100 Ω
6
7
8
2Y
3Z
2A
3Y
GND
3A
11
10
ZO = 100 Ω
9
NOTE A: Place a 0.1 µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground plane. The capacitor
should be located as close as possible to the device terminals.
Figure 11. Operation with a 5-V Supply
related information
IBIS modeling is available for this device. Please contact the local TI sales office or the TI Web site at www.ti.com
for more information.
For more application guidelines, please see the following documents:
D
D
D
D
D
D
Low-Voltage Differential Signalling Design Notes (TI literature number SLLA014)
Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
Reducing EMI with LVDS (SLLA030)
Slew Rate Control of LVDS Circuits (SLLA034)
Using an LVDS Receiver with RS-422 Data (SLLA031)
Evaluating the LVDS EVM (SLLA033)
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HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS261F – JULY 1997 – REVISED MARCH 2000
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047 / D 10/96
NOTES: A.
B.
C.
D.
14
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
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HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS261F – JULY 1997 – REVISED MARCH 2000
MECHANICAL INFORMATION
DGN (S-PDSO-G8)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
0,65
8
0,25 M
5
Thermal Pad
(See Note D)
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
1
0°– 6°
4
3,05
2,95
0,69
0,41
Seating Plane
1,07 MAX
0,15
0,05
0,10
4073271/A 01/98
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions include mold flash or protrusions.
The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-187
PowerPAD is a trademark of Texas Instruments Incorporated.
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HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS261F – JULY 1997 – REVISED MARCH 2000
MECHANICAL INFORMATION
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
25
5
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
16
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
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SLLS261F – JULY 1997 – REVISED MARCH 2000
MECHANICAL INFORMATION
J (R-GDIP-T**)
CERAMIC DUAL-IN-LINE PACKAGE
14 PIN SHOWN
PINS **
14
16
18
20
A MAX
0.310
(7,87)
0.310
(7,87)
0.310
(7,87)
0.310
(7,87)
A MIN
0.290
(7,37)
0.290
(7,37)
0.290
(7,37)
0.290
(7,37)
B MAX
0.785
(19,94)
0.785
(19,94)
0.910
(23,10)
0.975
(24,77)
B MIN
0.755
(19,18)
0.755
(19,18)
C MAX
0.300
(7,62)
0.300
(7,62)
0.300
(7,62)
0.300
(7,62)
C MIN
0.245
(6,22)
0.245
(6,22)
0.245
(6,22)
0.245
(6,22)
DIM
B
8
14
C
1
7
0.065 (1,65)
0.045 (1,14)
0.100 (2,54)
0.070 (1,78)
0.020 (0,51) MIN
0.930
(23,62)
A
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.100 (2,54)
0°–15°
0.023 (0,58)
0.015 (0,38)
0.014 (0,36)
0.008 (0,20)
4040083/D 08/98
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, GDIP1-T20, and GDIP1-T22.
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HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS261F – JULY 1997 – REVISED MARCH 2000
MECHANICAL INFORMATION
W (R-GDFP-F16)
CERAMIC DUAL FLATPACK
Base and Seating Plane
0.285 (7,24)
0.245 (6,22)
0.006 (0,15)
0.004 (0,10)
0.085 (2,16)
0.045 (1,14)
0.045 (1,14)
0.026 (0,66)
0.305 (7,75)
0.275 (6,99)
0.355 (9,02)
0.235 (5,97)
1
0.355 (9,02)
0.235 (5,97)
16
0.019 (0,48)
0.015 (0,38)
0.050 (1,27)
0.440 (11,18)
0.371 (9,42)
0.025 (0,64)
0.015 (0,38)
8
9
1.025 (26,04)
0.745 (18,92)
4040180-3 / B 03/95
NOTES: A.
B.
C.
D.
E.
18
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification only.
Falls within MIL-STD-1835 GDFP1-F16 and JEDEC MO-092AC
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