QS5100 Digital FX LSI 1. General Description 2. Features The QS5100 is a high quality Effect processor LSI that can • High resolution of up to 32k ~ 48kHz sampling rate produce the effects of reverb, chorus, echo, vibrato, tremolo, wahwah, and flanger with a 5 band-equalizer. • Supports 8 bit MCU or Serial EEPROM interface for All functions can be controlled by an external 8bit MCU, making it possible for the QS5100 to be applied to a wide variety of applications. stand alone mode. • 5 band EQ on digital output • Supports 256k words EDO DRAM for delay. • Low power operation 2.7V ~ 3.6V • Support for 16/18/20/22/24 bits Codec I/F Making the QS5100 the best solution for external guitar effectors, car audio, PA and hardware effect modules. • Supports reverb, chorus, echo, wah wah, flanger, tremolo, vibrato • Compact thin package 64 LQFP (10 X 10mm) • f = 8.192 ~ 12.288 MHz • Low power consumption under 10uA in power down mode • IDDOP < 50 mA 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 • Can be assign CODEC I/F (Left or Right Justified) 1 48 2 47 3 4 46 45 5 6 7 8 9 10 11 QS5100 Datecode KOREA 44 43 42 41 40 39 38 37 13 14 36 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 12 64P LQFP 10 X 10mm 0.5 pitch QS5100 Digital FX LSI 3. Pin Description PIN NO PAD NAME PAD TYPE I/O DESCRIPTION P1 CPU_DATA[0] PC3B03U I/O CPU Data I/O for Normal Mode. Serial EEPROM Data I/O for Stand Alone Mode. P2 CPU_DATA[1] PC3B03U I/O CPU Data I/O for Normal Mode. Serial EEPROM Clock for Stand Alone Mode. P3 CPU_DATA[2] PC3B03U I/O CPU Data I/O for Normal Mode. Set[0] for Stand Alone Mode. P4 CPU_DATA[3] PC3B03U I/O CPU Data I/O for Normal Mode. Set[1] for Stand Alone Mode. P5 CPU_DATA[4] PC3B03U I/O CPU Data I/O for Normal Mode. Set[2] for Stand Alone Mode. P6 CPU_DATA[5] PC3B03U I/O CPU Data I/O for Normal Mode. Set[3] for Stand Alone Mode. P7 VDD PVDF P Power P8 VSS PV0F P Ground P9 CPU_DATA[6] PC3B03U I/O CPU Data I/O for Normal Mode. Set[4] for Stand Alone Mode. P10 CPU_DATA[7] PC3B03U I/O CPU Data I/O for Normal Mode. Set[5] for Stand Alone Mode. P11 CPU_REB PC3B03U I/O Data Read Enable for Normal Mode. Used for external data read operation, functions on active low. First Serial Peripheral Interface CS for Stand Alone Mode. P12 CPU_WEB PC3B03U I/O Data Write Enable for Normal Mode. Used for external data write operation, functions on active low. First Serial Peripheral Interface Clock for Stand Alone Mode. P13 CPU_AB0 PC3B03U I/O Address Data Select for Normal Mode. Used to distinguish between Address and Data. Low for Address, High for Data. First Serial Peripheral Interface Data for Stand Alone Mode P14 CSB PC3D21 I QS5100 Chip Select. Data Read/Write operation possible when ‘0’. Cannot when ‘1’. P15 IRQB PC3B03U I/O CPU Interrrupt for Normal Mode. Second Serial Peripheral Interface CS for Stand Alone Mode. P16 SPI2_CLK PC3B03U I/O Second Serial Peripheral Interface Clock for Stand Alone Mode. P17 SPI2_OUT PC3B03U I/O Second Serial Peripheral Interface Data for Stand Alone Mode. P18 MODE0 PC3D21 I System Clock Mode 2X clock is used in System Clock when ‘0’, 1X clock when ‘1’ P19 MODE1 PC3D21 I System Select Mode Normal Mode when ‘0’, Stand Alone Mode when ‘1’ P20 MODE2 PC3D21 I Clock 2X Test Mode Normal mode when ‘0’, Clock 2X test mode when ‘1’ QS5100 Digital FX LSI PIN NO PAD NAME PAD TYPE I/O DESCRIPTION P21 MRSTB PC3D21U I Master Reset Operates on active low. P22 XOUT PC3X11 O Crystal Output P23 XIN PC3X11 I Crystal Input ( f = 8.192 ~ 12.288 Mhz ) P24 VDD PVDF P Power P25 VSS PV0F P Ground P26 SIN PC3D21 I Serial Data Input P27 MCLK PC3O03 O Serial Data System Clock P28 WCLK PC3O03 O Serial Data Sample Rate Clock P29 BCLK PC3O03 O Serial Data Bit Clock P30 SOUT PC3O03 O Serial Data Output P31 DRAM_ADDR[4] PC3O03 O DRAM Address P32 DRAM_ADDR[5] PC3O03 O DRAM Address P33 DRAM_ADDR[6] PC3O03 O DRAM Address P34 DRAM_ADDR[7] PC3O03 O DRAM Address P35 DRAM_ADDR[8] PC3O03 O DRAM Address P36 DRAM_OEB PC3O03 O DRAM Output Enable P37 DRAM_UCASB PC3O03 O DRAM Upper Column Address Strobe P38 DRAM_LCASB PC3O03 O DRAM Lower Column Address Strobe P39 VDD PVDF P Power P40 VSS PV0F P Ground P41 DRAM_ADDR[3] PC3O03 O DRAM Address P42 DRAM_ADDR[2] PC3O03 O DRAM Address P43 DRAM_ADDR[1] PC3O03 O DRAM Address P44 DRAM_ADDR[0] PC3O03 O DRAM Address P45 DRAM_RASB PC3O03 O DRAM Row Address strobe P46 DRAM_WEB PC3O03 O DRAM Write Enable P47 DRAM_DATA[3] PC3B03U I/O DRAM Data Inputs/Outputs P48 DRAM_DATA[2] PC3B03U I/O DRAM Data Inputs/Outputs P49 DRAM_DATA[1] PC3B03U I/O DRAM Data Inputs/Outputs P50 DRAM_DATA[0] PC3B03U I/O DRAM Data Inputs/Outputs P51 DRAM_DATA[4] PC3B03U I/O DRAM Data Inputs/Outputs P52 DRAM_DATA[5] PC3B03U I/O DRAM Data Inputs/Outputs P53 DRAM_DATA[6] PC3B03U I/O DRAM Data Inputs/Outputs P54 DRAM_DATA[7] PC3B03U I/O DRAM Data Inputs/Outputs P55 DRAM_DATA[8] PC3B03U I/O DRAM Data Inputs/Outputs QS5100 Digital FX LSI PIN NO PAD NAME PAD TYPE I/O DESCRIPTION P56 VDD PVDF P Power P57 VSS PV0F P Ground P58 DRAM_DATA[9] PC3B03U I/O DRAM Data Inputs/Outputs P59 DRAM_DATA[10] PC3B03U I/O DRAM Data Inputs/Outputs P60 DRAM_DATA[11] PC3B03U I/O DRAM Data Inputs/Outputs P61 DRAM_DATA[15] PC3B03U I/O DRAM Data Inputs/Outputs P62 DRAM_DATA[14] PC3B03U I/O DRAM Data Inputs/Outputs P63 DRAM_DATA[13] PC3B03U I/O DRAM Data Inputs/Outputs P64 DRAM_DATA[12] PC3B03U I/O DRAM Data Inputs/Outputs QS5100 Digital FX LSI 4. Block Diagram DRAM I/F CPU_DATA[0~7] MCUInterface CPU_RDB CPU_WRB CSB CPU_AB0 SOUT SIN FX DSP MCLK BCLK WCLK IRQB EIL TIL WIL TIR FIL FIR CIL CIR RIL RIR EIR ROR Lin Wah Flanger Tremolo Reverb Chorus Echo Rin WO WIR FO TO CO ROL EOL /EOR BOR WSOR TSOR RSOR CSOR FSOR BOL WSOL TSOL FSOL CSOL RSOL EQOL Data out EQ EQOR QS5100 Digital FX LSI 5. Application 5-1. Typical Hardware Configuration 5-1-1. Using with CODEC Interface C_DATA[0..7] BCLK 8bit MICOM SIN QS5100 ATMEGA-8L WCLK SOUT or ROUT 16/18/ 20/22/ 24 bits CODEC AUDIO OUT PreAMP LOUT MCLK LINE_IN Serial ROM & Select S/W 11.2896 MHz 5-2. Recommended System Reset Circuit and Clock circuit 3.3V 20pF XIN KIA7027 10K 1M 11.2896 MHz MRSTB 3 XOUT VCC OUT GND 1 2 + 47 20pF 1uF * KIA7027 is Voltage Detector made by KEC QS5100 Digital FX LSI 6. Electrical Characteristics 6-1. DC Characteristics Absolute Maximum range ITEMS Symbol Min Max Unit VDD 2.7 3.6 V TAOP -20 85 °C TCA -40 125 °C Symbol Min Max Unit VDD terminal power supply voltage VDD 2.7 3.6 V Digital input voltage VIND -0.3 VDD+0.3 V Operating ambient temperature TAOP 0 70 °C Carrier temperature TACA -20 125 °C VDD terminal power supply voltage Operating ambient temperature Carrier temperature Note Industrial Recommended operating condition ITEMS DC Characteristics ITEMS Symbol Min INPUT Voltage “H” Level VIH INPUT Voltage “L” Level Max Unit VDD*0.7 VDD + 0.5V V VIL -0.5V VDD*0.3 V OUTPUT Voltage “H” Level VOH VDD - 0.1V OUTPUT Voltage “L” Level VOL Input Leakage current IL Input capacity CI Typ V 1 VSS + 0.1V V 1000 uA 10 pF QS5100 Digital FX LSI 6-2. AC Characteristics 모든 Timing Condition은 내부 System Clock이 24MHz (출력 Sample Frequency는 48 KHz)로 동작한 다고 가정하였다. 6-2-1. External CPU Interface Timing 6-2-1-1. READ Operation tRC CSB tACC tCS CPU AB0 tAS tCH CPU WEB tWP tWR CPU REB tDS tDH tOH tRE Valid Address Valid Data CPU DATA ITEM SYMBOL MIN TYP MAX UNIT Read Cycle Time tRC 136 Access Time from AB0 tACC Chip Enable Setup Time tCS 0 ns Chip Enable Hold Time tCH 0 ns AB0 Setup Time tAS 0 ns Write Pulse Width tWP 42 ns Write Enable to Read Enable Delay tWR 85 ns Data Setup Time tDS 5 ns Data Hold Time tDH 0 ns Read Enable to Data setup time tRE 5 ns Hold Time from rising edge of CPU_RDB tOH 5 ns ns 113 ns QS5100 Digital FX LSI 6-2-1-2. WRITE Operation tWC CSB tCH tCS CPU AB0 tAS tAH tAW tAP CPU WEB tDS tWP tDH Valid Address Valid Data CPU DATA ITEM SYMBOL MIN TYP MAX UNIT Write Cycle Time tWC 173 ns Chip Enable Setup Time tCS 0 ns Chip Enable Hold Time tCH 0 ns AB0 Setup Time tAS 0 ns AB0 Hold Time tAH 0 ns Write Pulse Width tWP 42 ns AB0 High to Write Enable Delay tAW 42 ns AB0 Preset Time tAP 42 Ns Data Setup Time tDS 5 ns Data Hold Time tDH 0 ns QS5100 Digital FX LSI 6-2-2. CODEC Interface Timing 6-2-2-1. Clock Characteristics ITEM SYMBOL MIN Left/Right Clock Input WCLK Bit Clock Input BCLK TYP MAX UNIT 32 48 KHz 2.048 3.072 MHz 6-2-2-2. CODEC Interface Timing in Mode0 (DAC: MSB-First, Right Justified) WCLK Left Channel Right Channel 32Bits 32Bits BCLK DOUT Sign Extension MSB LSB Sign Extension MSB LSB 6-2-2-3. CODEC Interface Timing in Mode1 (DAC: MSB-First, Left Justified) WCLK Left Channel Right Channel 32Bits 32Bits BCLK DOUT MSB LSB Zero MSB LSB Zero QS5100 Digital FX LSI 6-2-2-3. CODEC Interface Timing in Mode0/1 (ADC: MSB-First, Left Justified) WCLK Left Channel Right Channel 32Bits 32Bits BCLK DIN MSB LSB Zero MSB LSB Zero 6-2-2-4. CODEC Interface Timing in Mode2 (DAC/ADC: MSB-First, I2S) WCLK Left Channel Right Channel 32Bits 32Bits BCLK DIN/DOUT 1bit Zero MSB LSB Zero 1bit Zero MSB LSB Zero QS5100 Digital FX LSI 6-3. Power Consumption Xin = 11.2896 MHz Items Symbol 3.0V 3.3V Unit Standby IDD & Operating ICCST/ ICCOP 45 50 mA Power Down Mode 7. Package Dimension ICCPD Max 10 uA QS5100 Digital FX LSI A. APPENDIX A-1. DFX Module Solution A-1-1. DFX Module Overview Digital FX Presets ADJUST Control DFX-MA4 DFX-MA16 4 Presets 16 Presets Rotary Encoder, Gray Encoder Rotary Linear Volume Level Control FX Level, Reverb Level DSP arithmetic 24bit Ext.DRAM MAX 256KWORD AD Converter AK4554VT(AK) DA Converter S/N(A-weight) 90dB Dynamic range 90dB Frequency passband 20Hz ~ 20KHz Sampling Frequency 32 ~ 48KHz Max.Input voltage 1 Vrms (Normal 300mVrms) Max.Output voltage 1 Vrms Input Impedance 12KOhm Analog Input Mono/Stereo Analog Output Stereo Power Supply DC 5V Power Consumption 160mA ( DC IN = 9V,VDD =3.6V Fs = 48Khz ) 1. Delay; Delay Time 1 Vibratone 2. Chorus: Speed 2 Delay - 150ms 3. Flange: Speed 3 Delay - 300ms 4. Reverb; Volume 4 Delay - 500ms 5 Reverb – Room 6 Reverb – Hall 7 Reverb – Spring 8 Reverb + Delay2 Dimensions 50 x 45mm *A-1 preliminary rev 1.1 – module specs may change without notice! 9 Fast Chorus 1 0 1 1 1 2 1 3 1 4 1 5 Deep Chorus Chorus + Delay Chorus + Reverb Flange 1 (Fast) Flange 2 (Slow) Flange + Reverb 1 Flange + Chorus + 6 Delay + Reverb QS5100 Digital FX LSI A-1-2. Pin Descriptions Part_Name/ Pin_No J2 J1 J3 PIN NAME MA4 MA16 FUNCTION FUNCTION PIN1 VCC + 5V +5V POWER SUPPLY PIN2 AGND ANALOG GROUND PIN3 AUX IN1 AUDIO INPUT,SINGLE ENDED MODE PIN4 AUX IN2 AUDIO INPUT,SINGLE ENDED MODE PIN5 AGND ANALOG GROUND PIN6 AUX OUT1 AUDIO OUTPUT,SINGLE ENDED MODE PIN7 AUX OUT1 AUDIO OUTPUT,SINGLE ENDED MODE PIN8 3.6VREF CONTROL PORT REFERENCE VOLTAGE OUT, 3.6V PIN9 FX MODE FX MODE CONTROL PIN10 FX LEVEL FX VOLUME PIN11 REV LEVEL REVERB LEVEL PIN12 N.C PIN1 SCK SPI BUS MASTER CLOCK INPUT PIN2 MISO SPI BUS MASTER INPUT PIN3 MOSI SPI BUS MASTER OUTPUT PIN4 NC PIN5 RESETB PIN6 GND PIN1 GPIO5/RXD Reserve Control Port/USART INPUT PIN2 GPIO6/TXD Reserve Control Port/USART OUTPUT PIN3 GPIO7/ADC_IN6 Reserve Control Port/ADC IN PIN4 GPIO8/ADC_IN7 Reserve Control Port/ADC IN PIN5 GPIO9/ADC_IN8 Reserve Control Port/ADC IN PIN6 GND N.C ( Control Port /ADC IN ) SPI RESET Ground Ground *A-1-2 preliminary rev 1.1 – module specs may change without notice! QS5100 A-1-3 DFX Module Application Schematic (DFX MA4 Type) *A-1-3 preliminary rev 1.1 – module specs may change without notice! Digital FX LSI QS5100 A-1-4 DFX Module Application Schematic (DFX MA16 Type) *A-1-4 preliminary rev 1.1 – module specs may change without notice! Digital FX LSI QS5100 Digital FX LSI A-1-5 MA16 Module Dimension A-2. Revision History Date Description 2005/8/15 First edition 2006/3/6 Rev 1.1: Appendix A-1 2006/4/13 Changed 6-3 and Added to A-1-5 MA16 module dimension (Ver 1.2)