TPS3420 TPS3421 TPS3422 www.ti.com SBVS211A – AUGUST 2012 – REVISED MARCH 2013 Low-Power, Push-Button Controllers with Configurable Delay Check for Samples: TPS3420, TPS3421, TPS3422 FEATURES DESCRIPTION • • • The TPS3420, TPS3421, and TPS3422 (TPS342x) are low-current, ultrasmall, push-button reset timers. These devices use a long timing setup delay to provide the intended system reset, and avoid resets from short push-button closures or key presses. This reset configuration also allows for differentiation between software interrupts and hard system resets. 1 Very Small Package: 1.45-mm × 1-mm SON Operating Range: 1.6 V to 6.5 V Single (TPS3422) or Dual (TPS3420 and TPS3421) Push-Button Inputs Low Supply Current: 250 nA Two-State Logic, User-Selectable Input Delay: – For Example: 7.5 s and 0 s – Multiple Timing Options Available Fixed Timeout Pulse at RST (TPS3421 and TPS3422): 400 ms – Other Timing Options Available on Request Active Low, Open-Drain Output 23 • • • • APPLICATIONS • • • • • • • Smart Phones Tablets, Ultrabooks™ Gaming Consoles Portable Consumer Navigation Devices Consumer Medical Toys The TPS3420 and TPS3421 monitor two inputs (PB1 and PB2) and output an active-low reset pulse signal (RST) when both inputs are low for the selected time delay. For the TPS3421, RST remains low for a factory-programmed fixed time. For the TPS3420, RST remains low until one of the PBx inputs is released. The need for a dedicated reset button is eliminated because two inputs are used to ensure reset. The TPS3422 monitors one input (PB1) and outputs an active-low reset pulse signal (RST) when PB1 is low for the selected time delay. The TPS342x have an open-drain output that can be wire ORed with other open-drain devices. The TPS342x operate from 1.6 V to 6.5 V over the –40°C to +125°C temperature range, and provide a precise, space-conscious micropower solution for system resetting needs. VIN = 1.6 V to 6.5 V TPS3420, TPS3421 DRY PACKAGE 1,45-mm x 1-mm SON (TOP VIEW) RST 1 6 PB2 RST 1 6 TST VDD VCC TPS3422 DRY PACKAGE 1,45-mm x 1-mm SON (TOP VIEW) PB1 RST PushButton Switch Microprocessor, PMU TPS3421 GND 2 5 TS PB1 3 4 VCC GND 2 5 TS PB1 3 4 VCC Reset PB2 TS PushButton Switch GND GND NOTE: Connect TS to VCC or ground for different PB time delays. Connect one PB input to ground for use as a single channel. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Ultrabooks is a trademark of Intel Corporation. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012–2013, Texas Instruments Incorporated TPS3420 TPS3421 TPS3422 SBVS211A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION PRODUCT DESCRIPTION TPS3420xzzza TPS3421xyzzza TPS3422xyzzza x is the push-button timer option. y is the different reset timeout pulse option. zzz is the package designator. a is the tape or reel quantity. DEVICE FAMILY OPTIONS DEVICE CHANNELS INPUT RESET BEHAVIOR (DEASSERTION) TPS3420 2 NMOS-based threshold Input (PBx) dependent TPS3421 2 External pull-up to VCC Fixed pulse TPS3422 1 Internal pull-up Fixed pulse ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. Voltage VALUE UNIT VCC –0.3 to +7 V RST –0.3 to +7 V PB1, PB2 –0.3 to +7 V –0.3 to VCC + 0.3 V TS Current RST pin Temperature (2) Electrostatic discharge (ESD) ratings (1) (2) ±20 mA Operating junction, TJ –40 to +125 °C Storage, Tstg –65 to +150 °C 2 kV 500 V Human body model (HBM) Charge device model (CDM) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute maximum- rated conditions for extended periods may affect device reliability. As a result of the low dissipated power in this device, it is assumed that TJ = TA. THERMAL INFORMATION TPS3420 TPS3421 TPS3422 THERMAL METRIC (1) UNITS DRY (µSON) 6 PINS θJA Junction-to-ambient thermal resistance 322.0 θJCtop Junction-to-case (top) thermal resistance 1185.2 θJB Junction-to-board thermal resistance 184.7 ψJT Junction-to-top characterization parameter 34.9 ψJB Junction-to-board characterization parameter 182.6 θJCbot Junction-to-case (bottom) thermal resistance 69.6 (1) 2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS3420 TPS3421 TPS3422 TPS3420 TPS3421 TPS3422 www.ti.com SBVS211A – AUGUST 2012 – REVISED MARCH 2013 ELECTRICAL CHARACTERISTICS All specifications are over the operating temperature range of –40°C < TJ < +125°C and 1.6 V ≤ VCC ≤ 6.5 V, unless otherwise noted. Typical values are at TJ = +25°C and VCC = 3.3 V. PARAMETER VCC TEST CONDITIONS Input supply range MIN VCC = 3.3 V TPS3421, TPS3422 VCC = 6.5 V VCC = 3.3 V TPS3420 Supply current (active timer) (1) High-level input voltage VIH 1 µA 3.3 µA nA 350 nA VCC = 6.5 V, –40°C < TJ < +85°C 1.2 µA VCC = 6.5 V 3.4 µA 6 12 µA TPS3422 PB1, PB2 = 0 V, VCC = 6.5 V 106 136 µA TPS3421, TPS3422 PB1, PB2 0.7 VCC V TPS3420 PB1, PB2 0.85 V TPS3421, TPS3422 PB1, PB2 0 0.3 VCC V TPS3420 PB1, PB2 0 0.3 V RPB1 PB1 internal pull-up resistance (TPS3422) IPB Input current (PB1, PB2) (1) V PB1, PB2 = 0 V, VCC = 6.5 V Low-level input voltage 65 TPS3420 TPS3421 PB1, PB2 = 0 V or VCC –50 TPS3422 PB1, PB2 = VCC -50 Low-level output voltage Ilkg(OD) UNIT 6.5 TPS3420, TPS3421 VIL VOL MAX 250 VCC = 6.5 V, –40°C < TJ < +85°C Supply current (standby) ICC TYP 1.6 Open-drain output leakage current kΩ 50 nA 50 nA VCC ≥ 4.5 V, ISINK = 8 mA 0.4 V VCC ≥ 3.3 V, ISINK = 5 mA 0.3 V VCC ≥ 1.6 V, ISINK = 3 mA 0.3 V 0.35 µA High impedance, V RST = 6.5 V –0.35 Includes current through pull-up resistor between input pin (PB1) and supply pin (VCC) for TPS3422. TIMING REQUIREMENTS All specifications are over the operating temperature range of –40°C < TJ < +125°C and 1.6 V ≤ VCC ≤ 6.5 V, unless otherwise noted. Typical values are at TJ = +25°C and VCC = 3.3 V. PARAMETER TEST CONDITIONS MIN TYP –20% ttimer Push button timer (1) 6 7.5 9 s TPS3420D: TS = VCC 10 12.5 15 s 6 7.5 9 s TPS3421Ey, TPS3422Ey: TS = VCC 0 –20% s 20% TPS3421xC 64 80 96 ms TPS3421xG 320 400 480 ms TPS3422xG 320 400 480 ms trst Reset pulse duration tdd Detection delay (from input to RST) (2) For 0-s ttimer condition Start-up time (2) VCC rising (2) UNIT 20% TPS3420D: TS = GND TPS3421Ey, TPS3422Ey: TS = GND (1) MAX 150 µs 300 µs For devices with a 0-second delay while TS = VCC, this option is only for factory testing and is not intended for normal operation. In normal operation, the TS pin should be tied to GND. For devices with a 0-second delay when TS = VCC, reset asserts in tdd time when both PB inputs go low in this configuration. During start up, if the PB inputs are low, reset asserts after a start-up time delay. This value is specified by design. Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS3420 TPS3421 TPS3422 Submit Documentation Feedback 3 TPS3420 TPS3421 TPS3422 SBVS211A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com TIMING DIAGRAMS TIMING DIAGRAM: TPS3420 PB1 ttimer = 7.5 s PB2 ttimer = 7.5 s trst(1) RST (1) For the TPS3420, trst is not a fixed time, but instead depends on one of the PB pins going high. Figure 1. TPS3420 Timing Diagram TIMING DIAGRAM: TPS3421 PB1 ttimer = 7.5 s PB2 ttimer = 7.5 s RST trst = 400 ms Figure 2. TPS3421 Timing Diagram TIMING DIAGRAM: TPS3422 Timer End PB1 ttimer = 7.5 s RST trst = 400 ms Figure 3. TPS3422 Timing Diagram 4 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS3420 TPS3421 TPS3422 TPS3420 TPS3421 TPS3422 www.ti.com SBVS211A – AUGUST 2012 – REVISED MARCH 2013 PIN CONFIGURATION TPS3420, TPS3421: DRY PACKAGE 1.45-mm × 1-mm SON (TOP VIEW) TPS3422: DRY PACKAGE 1.45-mm × 1-mm SON (TOP VIEW) RST 1 6 PB2 RST 1 6 TST GND 2 5 TS GND 2 5 TS PB1 3 4 VCC PB1 3 4 VCC PIN DESCRIPTIONS PIN NO. PIN NAME TPS3420/21 TPS3422 GND 2 2 Ground PB1 3 3 Push-button input. PB1 and PB2 must be held low for greater than ttimer time to assert the reset output. PB2 6 — Second push-button input. PB1 and PB2 must be held low for greater than ttimer time to assert the reset output. RST 1 1 Active low, open-drain output. Reset is asserted (goes low) when both PB1 and PB2 are held low for longer than ttimer time (only PB1 for TPS3422). For TPS3420: Reset is deasserted when either PBx input goes high. For TPS3421,TPS3422: Reset is deasserted after fixed time of trst. TS 5 5 Time delay selection input. Connect to VCC or GND for different ttimer selections. In normal operation, the TS pin state should not be changed because it is intended to be permanently connected to either GND or VCC. If switching the TS pin is required, it should be done during power off, or when either PBx input is high. TST — 6 Connect this pin to GND or VCC during normal device operation. VCC 4 4 Supply voltage input. Connect a 1.6-V to 6.5-V supply to VCC to power the device. It is good analog design practice to place a 0.1-µF ceramic capacitor close to this pin. DESCRIPTION Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS3420 TPS3421 TPS3422 Submit Documentation Feedback 5 TPS3420 TPS3421 TPS3422 SBVS211A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com FUNCTIONAL BLOCK DIAGRAMS VCC RST PB1 Digital Logic and Delay Generator Input Logic PB2 TS Timing Selector (Two-State Logic) GND Oscillator Figure 4. TPS3420 Block Diagram VCC RST PB1 Digital Logic and Delay Generator Input Logic PB2 TS Reset Pulse Generator Timing Selector (Two-State Logic) GND Oscillator Figure 5. TPS3421 Block Diagram VCC RST Digital Logic and Delay Generator PB1 TS Reset Pulse Generator TST Timing Selector (Two-State Logic) GND Oscillator Figure 6. TPS3422 Block Diagram 6 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS3420 TPS3421 TPS3422 TPS3420 TPS3421 TPS3422 www.ti.com SBVS211A – AUGUST 2012 – REVISED MARCH 2013 TYPICAL CHARACTERISTICS At TJ = +25°C and VCC = 3.3 V, unless otherwise noted. 8 1.2 ±40ƒC +0ƒC +25ƒC +85ƒC +105ƒC +125ƒC 7 Active Supply Current (µA) Standby Supply Current (µA) 1.4 1 0.8 0.6 0.4 6 5 4 ±40ƒC +0ƒC 3 +25ƒC 2 +85ƒC 0.2 1 +105ƒC 0 0 0 1 2 3 4 VCC (V) 5 6 +125ƒC 0 7 1 2 3 Figure 7. TPS3421: STANDBY SUPPLY CURRENT vs SUPPLY VOLTAGE 4 5 412 Vcc = 1.6 V Vcc = 1.6 V Reset Pulse Duration (ms) Vcc = 6.5 V Push Button Timer (s) 7 C002 Figure 8. TPS3421: ACTIVE SUPPLY CURRENT vs SUPPLY VOLTAGE (PB1 = PB2 = GND) 7.8 7.7 7.6 7.5 Vcc = 6.5 V 408 404 400 396 7.4 -50 -25 0 25 50 75 100 Temperature (ƒC) 125 -50 -25 0 25 50 75 100 Temperature (ƒC) C003 Figure 9. PUSH BUTTON TIMER vs TEMPERATURE (TS = GND) 125 C004 Figure 10. RESET PULSE DURATION vs TEMPERATURE 0.5 0.8 ±40ƒC 0.7 ±40ƒC +0ƒC 0.6 +25ƒC 0.5 +85ƒC 0.4 +125ƒC +0ƒC 0.4 +25ƒC VOL (V) VOL (V) 6 VCC (V) C001 0.3 0.2 +85ƒC 0.3 +125ƒC 0.2 0.1 0.1 0 0 0 2 4 6 Output Sink Current (mA) 8 10 0 2 Figure 11. OUTPUT VOLTAGE LOW vs OUTPUT SINK CURRENT (VCC = 1.6 V) 4 6 8 Output Sink Current (mA) C005 10 C006 Figure 12. OUTPUT VOLTAGE LOW vs OUTPUT SINK CURRENT (VCC = 3.3 V) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS3420 TPS3421 TPS3422 Submit Documentation Feedback 7 TPS3420 TPS3421 TPS3422 SBVS211A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C and VCC = 3.3 V, unless otherwise noted. 0.5 ±40ƒC +0ƒC 0.4 VOL (V) +25ƒC +85ƒC 0.3 +125ƒC 0.2 0.1 0 0 2 4 6 8 10 Output Sink Current (mA) C007 Figure 13. OUTPUT VOLTAGE LOW vs OUTPUT SINK CURRENT (VCC = 6.5 V) 8 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS3420 TPS3421 TPS3422 TPS3420 TPS3421 TPS3422 www.ti.com SBVS211A – AUGUST 2012 – REVISED MARCH 2013 DETAILED DESCRIPTION OVERVIEW The TPS342x are a family of push-button reset devices with an extended setup period that prevents resets from occurring as a result of short-duration switch closures. See the Device Family Options table for details. The TPS3420 is a dual-channel device with an output that asserts when both inputs (PB1 and PB2) are held low for the push-button timer duration, and deasserts when either input PBx is released. The TPS3421 is a dual-channel device with an output that asserts when both inputs (PB1 and PB2) are held low for the push-button timer duration, and deasserts after the reset timeout duration. TPS3422 is a single-channel device with an output that asserts when the PB1 input is held low for the pushbutton timer duration, and deasserts after the reset timeout duration. The TPS342x family also has a TS pin that selects between two different push-button timing options by connecting the pin to either GND or VCC. DEVICE INPUTS This section describes the input of the TPS342x devices. TPS3420 Inputs (PB1, PB2) The TPS3420 has two NMOS-based threshold inputs (PB1, PB2) with a VIH ≥ 0.85 V, and a VIL ≤ 0.3 V. When input conditions are met (that is, when both inputs are simultaneously held low for the push-button timer period, ttimer), the device asserts a reset low, as shown in Figure 1. Reset deassertion occurs when either input goes high. The reset pulse occurs only one time after each valid input condition. At least one input pin must be released (goes high) and then driven low for the ttimer period before RST asserts again. An application diagram is shown in Figure 14. VIN = 1.6 V to 6.5 V + VDD VCC Microprocessor TS PB1 Device RST PB2 Reset GND GPIO GPIO Push-Button Switch 1 Push-Button Switch 2 NOTE: Connect TS to VCC or ground for different PB time delays. Connect one PB input to ground for use as a single channel. Figure 14. TPS3420 Application Diagram Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS3420 TPS3421 TPS3422 Submit Documentation Feedback 9 TPS3420 TPS3421 TPS3422 SBVS211A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com TPS3421 Inputs (PB1, PB2) The TPS3421 has two inputs: PB1 and PB2. External pull-up resistors to VCC are required to pull the input pins high, as shown in Figure 15. When input conditions are met (that is, when both inputs are held low simultaneously for the push-button timer period, ttimer), the device asserts a single reset pulse of a fixed time (trst); see Figure 2. Reset deassertion is independent of the inputs because trst is a fixed time pulse. A reset pulse occurs only one time after each valid input condition. At least one input pin must be released (go high) and then driven low for the ttimer duration before RST asserts again; see Figure 17. VIN = 1.6 V to 6.5 V + VCC IN RST PB1 ON Load Switch OUT System Power GND Push-Button Switch Device TS PB2 GND NOTE: Connect TS to VCC or ground for different PB time delays. Connect one PB input to ground for use as a single channel. Figure 15. TPS3421 Application Diagram TPS3422 Input (PB1) The TPS3422 has only one input: PB1. This input has an internal pull-up resistor to VCC. When input conditions are met (that is, when the input is held low for the push-button timer period, ttimer), the device asserts a single reset pulse of a fixed time (trst); see Figure 3. Reset deassertion is independent of the input because trst is a fixed time pulse. A reset pulse occurs only one time after each valid input condition. The input pin must be released (go high) and then driven low for the ttimer period before RST asserts again. An application diagram is shown in Figure 16. VIN = 1.6 V to 6.5 V + VCC IN RST PB1 ON Load Switch OUT System Power GND Push-Button Switch Device TS TST GND NOTE: Connect TS to VCC or ground for different PB time delays. Figure 16. TPS3422 Application Diagram 10 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS3420 TPS3421 TPS3422 TPS3420 TPS3421 TPS3422 www.ti.com SBVS211A – AUGUST 2012 – REVISED MARCH 2013 PUSH-BUTTON TIMER SELECTION (TS) The TPS342x offer two different push-button timer options (ttimer) for system flexibility with the use of TS pin. Connect the TS pin to either GND or VCC for two different timing options, as shown in Table 1. Table 1. Push-Button Timer Option Examples PUSH-BUTTON TIMER PRODUCT TS = VCC TS = GND RESET PULSE TPS3420DDRYR/T 12.5 s 7.5 s N/A TPS3421EGDRYR/T 0s 7.5 s 400 ms TPS3422EGDRYR/T 0s 7.5 s 400 ms During normal operation, the TS pin state should not be changed because TS is intended to be permanently connected to either ground or VCC. The state of the TS pin is checked during power-up and when either PBx input is high. Therefore, if a different timing option is desired, the state must be changed during power-off, or when either PBx input is high, in order to avoid false operation. OUTPUT (RST) The TPS342x have an open-drain output. A pull-up resistor must be used to hold the line high when the output is in a high-impedance state (not asserted). By connecting a pull-up resistor to the proper voltage rail, the output can be connected to other devices at correct interface voltage levels. The TPS342x output can be pulled up to 6.5 V, independent of the device supply voltage. To ensure proper voltage levels, make sure to choose the correct pull-up resistor values. The pull-up resistor value is determined by VOL, sink current capability, and output leakage current (Ilkg(OD)). These values are specified in the Electrical Charactersitcs table. The Inputs (PB1, PB2) section describes how the output is asserted or deasserted. See Figure 1 (TPS3420), Figure 2 (TPS3421) , or Figure 3 (TPS3422) for a timing diagram that describes the relationship between the PB1 and PB2 inputs and the output. Figure 17 shows the TPS3421 reset timing. PB1 PB2 ttimer ttimer ttimer RST trst No Second Pulse trst Figure 17. TPS3421 Reset Timing Diagram Any change in input condition is detected after reset is deasserted. If input PB1 or PB2 has a pulse (low-to-highto-low) during the trst period, the change is not recognized by the device. If input PB1 or PB2 go high during the trst period, the change is detected after reset is deasserted. Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS3420 TPS3421 TPS3422 Submit Documentation Feedback 11 TPS3420 TPS3421 TPS3422 SBVS211A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from the page numbers in the current version. Changes from Original (August 2012) to Revision A • 12 Page Changed data sheet from product preview to production data ............................................................................................. 1 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS3420 TPS3421 TPS3422 PACKAGE OPTION ADDENDUM www.ti.com 14-May-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS3420DDRYR ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AD TPS3420DDRYT ACTIVE SON DRY 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AD TPS3421ECDRYR ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AB TPS3421ECDRYT ACTIVE SON DRY 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AB TPS3421EGDRYR ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AC TPS3421EGDRYT ACTIVE SON DRY 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AC TPS3422EGDRYR ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AE TPS3422EGDRYT ACTIVE SON DRY 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 14-May-2013 (4) Multiple Top-Side Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS3420DDRYT SON DRY 6 250 179.0 8.4 1.2 1.65 0.7 4.0 8.0 Q1 TPS3421ECDRYR SON DRY 6 5000 179.0 8.4 1.2 1.65 0.7 4.0 8.0 Q1 TPS3421ECDRYT SON DRY 6 250 179.0 8.4 1.2 1.65 0.7 4.0 8.0 Q1 TPS3421EGDRYR SON DRY 6 5000 179.0 8.4 1.2 1.65 0.7 4.0 8.0 Q1 TPS3421EGDRYT SON DRY 6 250 179.0 8.4 1.2 1.65 0.7 4.0 8.0 Q1 TPS3422EGDRYR SON DRY 6 5000 179.0 8.4 1.2 1.65 0.7 4.0 8.0 Q1 TPS3422EGDRYT SON DRY 6 250 179.0 8.4 1.2 1.65 0.7 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS3420DDRYT SON DRY 6 250 203.0 203.0 35.0 TPS3421ECDRYR SON DRY 6 5000 203.0 203.0 35.0 TPS3421ECDRYT SON DRY 6 250 203.0 203.0 35.0 TPS3421EGDRYR SON DRY 6 5000 203.0 203.0 35.0 TPS3421EGDRYT SON DRY 6 250 203.0 203.0 35.0 TPS3422EGDRYR SON DRY 6 5000 203.0 203.0 35.0 TPS3422EGDRYT SON DRY 6 250 203.0 203.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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