OPA317 OPA2317 OPA4317 www.ti.com SBOS682A – MAY 2013 – REVISED JUNE 2013 Low-Offset, Rail-to-Rail I/O Operational Amplifier Precision Catalog Check for Samples: OPA317, OPA2317, OPA4317 FEATURES DESCRIPTION • • The OPA317 series of CMOS operational amplifiers offer precision performance at a very competitive price. These devices are members of the Zerø-Drift family of amplifiers that use a proprietary autocalibration technique to simultaneously provide low offset voltage (90 μV max) and near-zero drift over time and temperature at only 35 μA (max) of quiescent current. 1 2 • • • • • • Supply Voltage: 1.8 V to 5.5 V microPackages: – Single: SOT23-5, SC-70, SOIC-8 – Dual: MSOP-8, SOIC-8 – Quad: SOIC-14, TSSOP-14 Low Offset Voltage: 20 μV (typ) CMRR: 108 dB (typ) Quiescent Current: 35 μA (max) Gain Bandwidth: 300 kHz Rail-to-Rail Input/Output Internal EMI/RFI Filtering The OPA317 family features rail-to-rail input and output in addition to near flat 1/f noise, making this amplifier ideal for many applications, and much easier to design into a system. These devices are optimized for low-voltage operation as low as +1.8 V (±0.9 V) and up to +5.5 V (±2.75 V). The OPA317 (single version) is available in the SC70-5, SOT23-5, and SOIC-8 packages. The OPA2317 (dual version) is offered in MSOP-8 and SOIC-8 packages. The OPA4317 is offered in the standard SOIC-14 and TSSOP-14 packages, as well as in the space-saving VQFN-14 package. All versions are specified for operation from –40°C to +125°C. APPLICATIONS • • • • • • • Battery-Powered Instruments Temperature Measurements Transducer Applications Electronic Scales Medical Instrumentation Handheld Test Equipment Current Sense PRODUCT FAMILY PACKAGE COMPARISON PACKAGE-LEADS DEVICE NUMBER OF CHANNELS SOIC SOT23 SC70 MSOP TSSOP – OPA317 1 8 5 5 – OPA2317 2 8 – – 8 – OPA4317 4 14 – – – 14 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated OPA317 OPA2317 OPA4317 SBOS682A – MAY 2013 – REVISED JUNE 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE AND ORDERING INFORMATION (1) (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. VALUE UNIT Supply voltage, VS = (V+) – (V–) +7 V Signal input terminals, voltage (2) (V–) –0.3 to (V+) + 0.3 V ±10 mA Signal input terminals, current (2) Output short-circuit (3) Continuous Operating temperature –40 to +150 °C Storage temperature –65 to +150 °C Junction temperature Electrostatic discharge (ESD) ratings: (1) (2) (3) 2 +150 °C Human body model (HBM) 4000 V Charged device model (CDM) 1000 V Machine model (MM) 400 V Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should be current limited to 10 mA or less. Short-circuit to ground, one amplifier per package. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA317 OPA2317 OPA4317 OPA317 OPA2317 OPA4317 www.ti.com SBOS682A – MAY 2013 – REVISED JUNE 2013 THERMAL INFORMATION: OPA317 OPA317 THERMAL METRIC (1) D (SOIC) DBV (SOT23) DCK (SC70) 8 PINS 5 PINS 5 PINS θJA Junction-to-ambient thermal resistance 140.1 220.8 298.4 θJCtop Junction-to-case (top) thermal resistance 89.8 97.5 65.4 θJB Junction-to-board thermal resistance 80.6 61.7 97.1 ψJT Junction-to-top characterization parameter 28.7 7.6 0.8 ψJB Junction-to-board characterization parameter 80.1 61.1 95.5 θJCbot Junction-to-case (bottom) thermal resistance N/A N/A N/A (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. THERMAL INFORMATION: OPA2317 OPA2317 THERMAL METRIC (1) D (SOIC) DGK (MSOP) 8 PINS 8 PINS 180.3 θJA Junction-to-ambient thermal resistance 124.0 θJCtop Junction-to-case (top) thermal resistance 73.7 48.1 θJB Junction-to-board thermal resistance 64.4 100.9 ψJT Junction-to-top characterization parameter 18.0 2.4 ψJB Junction-to-board characterization parameter 63.9 99.3 θJCbot Junction-to-case (bottom) thermal resistance N/A N/A (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. THERMAL INFORMATION: OPA4317 OPA4317 THERMAL METRIC (1) D (SOIC) PW (TSSOP) 14 PINS 14 PINS θJA Junction-to-ambient thermal resistance 83.8 120.8 θJCtop Junction-to-case (top) thermal resistance 70.7 34.3 θJB Junction-to-board thermal resistance 59.5 62.8 ψJT Junction-to-top characterization parameter 11.6 1.0 ψJB Junction-to-board characterization parameter 37.7 56.5 θJCbot Junction-to-case (bottom) thermal resistance N/A N/A (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA317 OPA2317 OPA4317 3 OPA317 OPA2317 OPA4317 SBOS682A – MAY 2013 – REVISED JUNE 2013 www.ti.com ELECTRICAL CHARACTERISTICS: VS = +1.8 V to +5.5 V At TA = +25°C, RL = 10 kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. OPA317, OPA2317, OPA4317 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ±90 μV OFFSET VOLTAGE VS = +5 V VOS Input offset voltage dVOS/dT vs temperature TA = –40°C to +125°C PSRR vs power supply TA = –40°C to +125°C, VS = +1.8 V to +5.5 V 20 TA = –40°C to +125°C, VS = +5 V ±100 1 Long-term stability (1) See Channel separation, dc μV μV/°C 0.05 10 μV/V (1) μV/V 5 INPUT BIAS CURRENT IB Input bias current IOS Input offset current ±275 pA OPA4317 ±155 pA TA = –40°C to +125°C ±300 pA ±400 pA ±140 pA OPA4317 NOISE en Input voltage noise density Input voltage noise in Input current noise f = 1 kHz 55 nV/√Hz f = 0.01 Hz to 1 Hz 0.3 μVPP f = 0.1 Hz to 10 Hz 1.1 μVPP f = 10 Hz 100 fA/√Hz INPUT VOLTAGE RANGE VCM Common-mode voltage range CMRR (V–) – 0.1 (V+) + 0.1 V TA = –40°C to +125°C (V–) – 0.1 V < VCM < (V+) + 0.1 V 95 108 dB OPA4317, TA = –40°C to +125°C (V–) – 0.1 V < VCM < (V+) + 0.1 V, VS = 5.5 V 95 108 dB Differential 2 pF Common-mode 4 pF 110 dB Common-mode rejection ratio INPUT CAPACITANCE OPEN-LOOP GAIN AOL Open-loop voltage gain TA = –40°C to +125°C, (V–) + 100 mV < VO < (V+) – 100 mV, RL = 10 kΩ 100 FREQUENCY RESPONSE GBW Gain-bandwidth product CL = 100 pF 300 kHz SR Slew rate G = +1 0.15 V/μs Voltage output swing from rail TA = –40°C to +125°C OUTPUT ISC Short-circuit current CL Capacitive load drive Open-loop output impedance 30 100 ±5 mV mA See Typical Characteristics f = 350 kHz, IO = 0 2 kΩ POWER SUPPLY VS Specified voltage range IQ Quiescent current per amplifier TA = –40°C to +125°C, IO = 0 1.8 Turn-on time VS = +5 V 21 5.5 V 35 μA μs 100 TEMPERATURE (1) 4 Specified range –40 +125 °C Operating range –40 +150 °C Storage range –65 +150 °C 300-hour life test at +150°C demonstrated randomly distributed variation of approximately 1 μV. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA317 OPA2317 OPA4317 OPA317 OPA2317 OPA4317 www.ti.com SBOS682A – MAY 2013 – REVISED JUNE 2013 PIN CONFIGURATIONS OPA317 SOT23-5 (TOP VIEW) OUT 1 V- 2 +IN 3 OPA317 SC70-5 (TOP VIEW) 5 4 V+ +IN 1 V- 2 -IN 3 -IN OPA317 SOIC-8 (TOP VIEW) (1) NC -IN 2 7 V+ +IN 3 6 OUT V- 4 5 NC OUT A 1 OUT 8 V+ 7 OUT B A -IN A 2 B +IN A 3 6 -IN B V- 4 5 +IN B (1) OPA4317 SOIC-14 (TOP VIEW) OPA4317 TSSOP-14 (TOP VIEW) OUT A 1 14 OUT D -IN A 2 13 -IN D +IN A 3 12 +IN D V+ 4 11 V- +IN B 5 10 +IN C -IN B 6 9 -IN C OUT B 7 8 OUT C B 4 (1) 8 A V+ OPA2317 SOIC-8, MSOP-8 (TOP VIEW) 1 NC 5 D C OUT A 1 14 OUT D -IN A 2 13 -IN D +IN A 3 12 +IN D V+ 4 11 V- +IN B 5 10 +IN C -IN B 6 9 -IN C OUT B 7 8 OUT C Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA317 OPA2317 OPA4317 5 OPA317 OPA2317 OPA4317 SBOS682A – MAY 2013 – REVISED JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, CL = 0 pF, RL = 10 kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. 120 250 100 200 AOL (dB) 150 Phase 60 100 40 50 Phase (°) Population 80 Gain 20 0 0 -50 -100 10 24.00 18.00 21.00 12.00 15.00 6.00 9.00 0 3.00 -3.00 -9.00 -6.00 -15.00 -12.00 -21.00 -18.00 -24.00 -20 100 1k 10k 100k 1M Frequency (Hz) Offset Voltage (mV) Figure 1. OFFSET VOLTAGE PRODUCTION DISTRIBUTION Figure 2. OPEN-LOOP GAIN vs FREQUENCY 140 120 120 100 +PSRR PSRR (dB) CMRR (dB) 100 80 60 -PSRR 80 60 40 40 20 20 0 0 1 10 100 1k 10k 100k 1 1M 10 100 Frequency (Hz) Figure 3. COMMON-MODE REJECTION RATIO vs FREQUENCY 3 100k 1M 210 205 200 -40°C +25°C +125°C 0 -IB 195 1 +25°C IB (pA) Output Swing (V) 10k Figure 4. POWER-SUPPLY REJECTION RATIO vs FREQUENCY VS = ±2.75V VS = ±0.9V 2 -40°C -1 +125°C -195 +IB -200 -205 -40°C -3 190 -190 +25°C -2 -210 0 1 2 3 4 5 6 7 8 9 10 0 1 Output Current (mA) Figure 5. OUTPUT VOLTAGE SWING vs OUTPUT CURRENT 6 1k Frequency (Hz) 2 3 4 5 Common-Mode Voltage (V) Figure 6. INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA317 OPA2317 OPA4317 OPA317 OPA2317 OPA4317 www.ti.com SBOS682A – MAY 2013 – REVISED JUNE 2013 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, CL = 0 pF, RL = 10 kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. 250 25 -IB 200 VS = 5.5V -IB 150 20 100 VS = 1.8V VS = 5.5V VS = 1.8V 0 -50 15 IQ (mA) IB (pA) 50 10 -100 +IB -150 5 -200 +IB -250 -50 0 -25 0 25 50 75 100 125 -50 -25 Figure 7. INPUT BIAS CURRENT vs TEMPERATURE 25 50 100 125 Output Voltage (1V/div) Output Voltage (50mV/div) G = +1 RL = 10kW Time (50ms/div) Time (5ms/div) Figure 9. LARGE-SIGNAL STEP RESPONSE Figure 10. SMALL-SIGNAL STEP RESPONSE 0 2 V/div Input 1 V/div Output 10 kW Input 0 0 10 kW +2.5 V +2.5 V 1 kW 1 kW 1 V/div 75 Figure 8. QUIESCENT CURRENT vs TEMPERATURE G=1 RL = 10kW 2 V/div 0 Temperature (°C) Temperature (°C) Output 0 Device Device -2.5 V -2.5 V Time (50 ms/div) Time (50 ms/div) Figure 11. POSITIVE OVER-VOLTAGE RECOVERY Figure 12. NEGATIVE OVER-VOLTAGE RECOVERY Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA317 OPA2317 OPA4317 7 OPA317 OPA2317 OPA4317 SBOS682A – MAY 2013 – REVISED JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, CL = 0 pF, RL = 10 kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. 40 600 4V Step 35 30 400 Overshoot (%) Settling Time (ms) 500 300 200 0.001% 25 20 15 10 100 5 0.01% 0 0 1 10 10 100 100 1000 Gain (dB) Load Capacitance (pF) Figure 13. SETTLING TIME vs CLOSED-LOOP GAIN Figure 14. SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE 500nV/div 1000 Continues with no 1/f (flicker) noise. Current Noise 100 100 Voltage Noise 10 10 1 1s/div Current Noise (fA/ÖHz) Voltage Noise (nV/ÖHz) 1000 10 100 1k 10k Frequency (Hz) Figure 15. 0.1Hz TO 10Hz NOISE 50 Input Bias Current (mA) 40 30 Figure 16. CURRENT AND VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY Normal Operating Range (see the Input Differential Voltage section in the Applications Information) 20 10 0 -10 -20 -30 Over-Driven Condition Over-Driven Condition -40 -50 -1V -800 -600 -400 -200 0 200 400 600 800 Input Differential Voltage (mV) Figure 17. INPUT BIAS CURRENT vs INPUT DIFFERENTIAL VOLTAGE 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA317 OPA2317 OPA4317 OPA317 OPA2317 OPA4317 www.ti.com SBOS682A – MAY 2013 – REVISED JUNE 2013 APPLICATIONS INFORMATION The OPA317, OPA2317, and OPA4317 are unity-gain stable, precision operational amplifiers free from unexpected output and phase reversal. Proprietary Zerø-Drift circuitry gives the benefit of low input offset voltage over time and temperature, as well as lowering the 1/f noise component. As a result of the high PSRR, these devices work well in applications that run directly from battery power without regulation. The OPA317 family is optimized for low-voltage, single-supply operation. These miniature, high-precision, low quiescent current amplifiers offer high-impedance inputs that have a common-mode range 100 mV beyond the supplies, and a railto-rail output that swings within 100 mV of the supplies under normal test conditions. The OPA317 series are precision amplifiers for cost-sensitive applications. OPERATING VOLTAGE The OPA317 series op amps can be used with single or dual supplies from an operating range of VS = +1.8 V (±0.9 V) up to +5.5 V (±2.75 V). CAUTION Supply voltages greater than +7 V can permanently damage the device. See the Absolute Maximum Ratings table. Key parameters that vary over the supply voltage or temperature range are shown in the Typical Characteristics section of this data sheet. INPUT VOLTAGE The OPA317, OPA2317, and OPA4317 input common-mode voltage range extends 0.1 V beyond the supply rails. The OPA317 is designed to cover the full range without the troublesome transition region found in some other rail-to-rail amplifiers. Typically, input bias current is about 200 pA; however, input voltages exceeding the power supplies can cause excessive current to flow into or out of the input pins. Momentary voltages greater than the power supply can be tolerated if the input current is limited to 10 mA. This limitation is easily accomplished with an input resistor, as shown in Figure 18. Current-limiting resistor required if input voltage exceeds supply rails by ³ 0.3 V. IOVERLOAD 10 mA max +5 V Device VOUT VIN 5 kW Figure 18. Input Current Protection INPUT DIFFERENTIAL VOLTAGE The typical input bias current of the OPA317 during normal operation is approximately 200 pA. In overdriven conditions, the bias current can increase significantly (see Figure 17).The most common cause of an overdriven condition occurs when the op amp is outside of the linear range of operation. When the output of the op amp is driven to one of the supply rails, the feedback loop requirements cannot be satisfied and a differential input voltage develops across the input pins. This differential input voltage results in activation of parasitic diodes inside the front-end input chopping switches that combine with 10-kΩ electromagnetic interference (EMI) filter resistors to create the equivalent circuit shown in Figure 19. Note that the input bias current remains within specification within the linear region. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA317 OPA2317 OPA4317 9 OPA317 OPA2317 OPA4317 SBOS682A – MAY 2013 – REVISED JUNE 2013 www.ti.com 10 kW Clamp +In CORE -In 10 kW Figure 19. Equivalent Input Circuit INTERNAL OFFSET CORRECTION The OPA317, OPA2317, and OPA4317 op amps use an auto-calibration technique with a time-continuous, 125kHz op amp in the signal path. This amplifier is zero-corrected every 8 μs using a proprietary technique. Upon power-up, the amplifier requires approximately 100 μs to achieve specified VOS accuracy. This design has no aliasing or flicker noise. EMI SUSCEPTIBILITY AND INPUT FILTERING Operational amplifiers vary in their susceptibility to EMI. If conducted EMI enters the operational amplifier, the dc offset observed at the amplifier output may shift from its nominal value while the EMI is present. This shift is a result of signal rectification associated with the internal semiconductor junctions. While all operational amplifier pin functions can be affected by EMI, the input pins are likely to be the most susceptible. The OPA317 operational amplifier family incorporates an internal input low-pass filter that reduces the amplifier response to EMI. Both common-mode and differential mode filtering are provided by the input filter. The filter is designed for a cutoff frequency of approximately 8 MHz (–3 dB), with a roll-off of 20 dB per decade. ACHIEVING OUTPUT SWING TO THE OP AMP NEGATIVE RAIL Some applications require output voltage swings from 0 V to a positive full-scale voltage (such as +2.5 V) with excellent accuracy. With most single-supply op amps, problems arise when the output signal approaches 0 V, near the lower output swing limit of a single-supply op amp. A good single-supply op amp may swing close to single-supply ground, but will not reach ground. The output of the OPA317, OPA2317, and OPA4317 can be made to swing to ground, or slightly below, on a single-supply power source. To do so requires the use of another resistor and an additional, more negative power supply than the op amp negative supply. A pull-down resistor can be connected between the output and the additional negative supply to pull the output down below the value that the output would otherwise achieve, as shown in Figure 20. V+ = +5 V VOUT Device VIN RP = 20 kW Op Amp V- = GND -5 V Additional Negative Supply Figure 20. For VOUT Range to Ground The OPA317, OPA2317, and OPA4317 have an output stage that allows the output voltage to be pulled to its negative supply rail, or slightly below, using the technique previously described. This technique only works with some types of output stages. The OPA317, OPA2317, and OPA4317 have been characterized to perform with this technique; the recommended resistor value is approximately 20 kΩ. Note that this configuration increases the current consumption by several hundreds of microamps. Accuracy is excellent down to 0 V and as low as –2 mV. Limiting and nonlinearity occurs below –2 mV, but excellent accuracy returns as the output drives back up above –2 mV. Lowering the resistance of the pull-down resistor allows the op amp to swing even further below the negative rail. Use resistances as low as 10 kΩ to achieve excellent accuracy down to –10 mV. 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA317 OPA2317 OPA4317 OPA317 OPA2317 OPA4317 www.ti.com SBOS682A – MAY 2013 – REVISED JUNE 2013 APPLICATION CIRCUITS Figure 21 shows the basic configuration for a bridge amplifier. A low-side current shunt monitor is shown in Figure 22. VEX R1 +5 V R R R R Device VOUT R1 VREF Figure 21. Single Op Amp Bridge Amplifier 3V +5 V REF3130 Load R2 49.9 kW R1 4.99 kW R6 71.5 kW V ILOAD RSHUNT 1W RN 56 W Device R4 48.7 kW R3 4.99 kW ADS1100 R7 1.18 kW Stray Ground-Loop Resistance RN 56 W 2 IC (PGA Gain = 4) FS = 3.0 V NOTE: 1% resistors provide adequate common-mode rejection at small ground-loop errors. Figure 22. Low-Side Current Monitor RN are operational resistors used to isolate the ADS1100 from the noise of the digital I2C bus. The ADS1100 is a 16-bit converter; therefore, a precise reference is essential for maximum accuracy. If absolute accuracy is not required and the 5-V power supply is sufficiently stable, the REF3130 may be omitted. Figure 23 shows the OPA317 in a typical thermistor circuit. 100 kW 1 MW 3V 1 MW 60 kW NTC Thermistor Device Figure 23. Thermistor Measurement Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA317 OPA2317 OPA4317 11 OPA317 OPA2317 OPA4317 SBOS682A – MAY 2013 – REVISED JUNE 2013 www.ti.com GENERAL LAYOUT GUIDELINES Attention to good layout practice is always recommended. Keep traces short and, when possible, use a printed circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1-μF capacitor closely across the supply pins. Apply these guidelines throughout the analog circuit to improve performance and provide benefits, such as reducing the electromagnetic interference (EMI) susceptibility. Optimize circuit layout and mechanical conditions for lowest offset voltage and precision performance. Avoid temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed from connecting dissimilar conductors. These thermally-generated potentials can be made to cancel by assuring they are equal on both input terminals. Other layout and design considerations include: • Use low thermoelectric-coefficient conditions (avoid dissimilar metals). • Thermally isolate components from power supplies or other heat sources. • Shield op amp and input circuitry from air currents, such as cooling fans. Following these guidelines reduces the likelihood of junctions being at different temperatures, which can cause thermoelectric voltages of 0.1 μV/°C or higher, depending on the materials used. 12 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA317 OPA2317 OPA4317 OPA317 OPA2317 OPA4317 www.ti.com SBOS682A – MAY 2013 – REVISED JUNE 2013 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (May 2013) to Revision A Page • Deleted PSRR Features bullet .............................................................................................................................................. 1 • Changed Quiescent Current Features bullet ........................................................................................................................ 1 • Changed second sentence in Description section ................................................................................................................ 1 • Changed PSSR maximum value .......................................................................................................................................... 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA317 OPA2317 OPA4317 13 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty OPA2317ID ACTIVE SOIC D 8 75 OPA2317IDGKR ACTIVE VSSOP DGK 8 2500 OPA2317IDGKT ACTIVE VSSOP DGK 8 OPA2317IDR ACTIVE SOIC D OPA317ID ACTIVE SOIC OPA317IDBVR ACTIVE OPA317IDBVT Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Device Marking (3) CU NIPDAU (4/5) Level-1-260C-UNLIM -40 to 125 O2317A Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM -40 to 125 OVBQ 250 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM -40 to 125 OVBQ 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 O2317A D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 O317A SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 OVCQ ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 OVCQ OPA317IDCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJP OPA317IDCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJP OPA317IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 O317A OPA4317ID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 O4317A OPA4317IDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 O4317A OPA4317IPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 O4317A OPA4317IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 O4317A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing OPA2317IDR SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA317IDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 OPA317IDCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 OPA317IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA4317IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 OPA4317IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA2317IDR SOIC D 8 2500 367.0 367.0 35.0 OPA317IDBVT SOT-23 DBV 5 250 180.0 180.0 18.0 OPA317IDCKT SC70 DCK 5 250 180.0 180.0 18.0 OPA317IDR SOIC D 8 2500 367.0 367.0 35.0 OPA4317IDR SOIC D 14 2500 367.0 367.0 38.0 OPA4317IPWR TSSOP PW 14 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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