TPL5100 www.ti.com SNAS629B – JULY 2013 – REVISED AUGUST 2013 TPL5100 Nano Power Programmable Timer with MOS driver Check for Samples: TPL5100 FEATURES DESCRIPTION • • • The TPL5100 is a long-term timer IC optimized for low power applications. The TPL5100 can replace a micro controller's (µC) internal timer, allowing the µC to stay completely off instead of running a timer, providing a total power consumption reduction of 60 to 80%.The TPL5100 is designed for use in power cycled applications and provides selectable timing from 16 seconds to 1024 seconds. The TPL5100 can also monitor a battery management IC via a powergood digital input and power on the µC only when a good supply voltage is present. The device is packaged in a 10-pin VSSOP package. 1 Supply Voltage from 1.8V to 5.0V Selectable Timer Intervals, 16s to 1024s Current Consumption 30nA (typ, at 2.5V) APPLICATIONS • • • • • • • • Battery-Powered Systems Energy Harvesting Systems Remote Data-Logger Sensor Node Power-gating applications Building automation Low power wireless Consumer electronics TPL5100 VOUT VBAT_OK VIN D0 µC PGOOD VDD D1 POWER MANAGEMENT D2 GND MOS_DRV VDD TCAL GPIO GND DONE GPIO GND Figure 1. Simplified Application Schematic 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated TPL5100 SNAS629B – JULY 2013 – REVISED AUGUST 2013 www.ti.com Block Diagram VDD PGOOD LOW POWER OSCILLATOR FREQUENCY DIVIDER MOS_DRV CONTROL TCAL DONE D1 D2 DECODER D0 GND Figure 2. Block Diagram 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPL5100 TPL5100 www.ti.com SNAS629B – JULY 2013 – REVISED AUGUST 2013 Connection Diagram TPL5100 D0 PGOOD D1 DNC D2 MOS_DRV VDD TCAL GND DONE Figure 3. Top View 10-Lead VSSOP Pin Descriptions Pin(s) Name 1 D0 Logic Input to set period delay (tDP) Description Connect to GND (low logic value) or to VDD (high logic value) 2 D1 Logic Input to set period delay (tDP) Connect to GND (low logic value) or to VDD (high logic value) 3 D2 Logic Input to set period delay (tDP) Connect to GND (low logic value) or to VDD (high logic value) 4 VDD Supply voltage 5 GND Ground 6 DONE Logic input for Watchdog functionality 7 TCAL Short duration pulse output for estimation of TPL5100 timer delay. 8 MOS_DRV Drives external MOSFET to power cycle the remaining system. 9 DNC 10 PGOOD Do Not Connect Application Information Leave this pin floating Digital power good input Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPL5100 3 TPL5100 SNAS629B – JULY 2013 – REVISED AUGUST 2013 www.ti.com Absolute Maximum Ratings (1) (2) MIN MAX UNIT Supply Voltage (VDD-GND) -0.3 6 V Input voltage -0.3 VDD+0.3 V Voltage between any two pins (3) -0.3 VDD+0.3 V Input Current on any pin -5 +5 mA Operating Temperature, TA -40 105 °C Storage Temperature, Tstg -65 150 °C Junction Temperature, TJ (4) ESD Rating (1) (2) (3) (4) (5) 150 °C Human Body Model (5) 1000 V Charged Device Model 250 V Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics. All voltages referenced to ground unless otherwise noted. When the input voltage (VIN) at any pin exceeds the power supply (VDD), the current on that pin must not exceed 5mA and the voltage must also not exceed 6.0V. The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board. The human body model is a 100pF capacitor discharged through a 1.5k resistor into each pin. Thermal Characteristics UNIT θJA (1) (2) Package thermal impedance (1) (2) 196.8 °C/W The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Ratings MIN MAX UNIT Supply Voltage (VDD-GND) 1.8 5.0 V Temperature Range -40 105 °C 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPL5100 TPL5100 www.ti.com SNAS629B – JULY 2013 – REVISED AUGUST 2013 Electrical Characteristics (1) Specifications with standard typeface are for TA =TJ = 25°C, VDD-GND=2.5V, unless otherwise stated. Symbol Typ (3) Max (2) Units PGOOD=VDD 30 50 nA PGOOD=GND 12 nA 16, 32, 64, 100, 128, 256, 512, 1024 s Parameter Conditions Min (2) POWER SUPPLY IVDD Supply current (4) TIMER tDP tCAL Timer Delay Period Timer Delay Period drift over life time (5) 0.06 % Timer Delay Period drift over temperature 400 ppm/°C Calibration pulse width tDP to tCAL matching error tDONE tMOS_DRV 14.063 (6) 15.625 VDD<=3.0V DONE Pulse width (6) 17.188 0.1 100 MOS_DRV Pulse width ms % ns 31.25 ms DIGITAL LOGIC LEVELS VIH Logic High Threshold PGOOD, DONE VIL Logic Low Threshold PGOOD, DONE VOH VOL Logic output High Level Logic output Low Level 0.7xVDD V 0.3xVDD V MOS_DRV, TCAL Iout = 100uA VDD-0.3 V MOS_DRV, TCAL Iout = 1mA VDD-0.7 V MOS_DRV, TCAL Iout = -100uA 0.3 MOS_DRV, TCAL Iout = -1mA 0.7 V V TIMING TCAL, MOS_DRV, DONE, PGOOD - Refer to Timing Diagram trTCAL Rise Time TCAL Capacitve load 15pF 50 ns tfTCAL Fall Time TCAL Capacitve load 15pF 50 ns trMOS_DRV Rise Time MOS_DRV Capacitve load 50pF 4 ns tfMOS_DRV Fall Time MOS_DRV Capacitve load 50pF 50 ns DONE to MOS_DRV delay Min delay 100 ns Max delay tDP-5*tCAL ms tCAL/2 ms tDDONE tDTCAL (1) (2) (3) (4) (5) (6) TCAL to MOS_DRV delay Electrical Characteristics Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. The supply current doesn’t take in account load and pull-up resistor current. Input pins are at GND or VDD. Operational life time test procedure equivalent to 10 years. Guaranteed by design. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPL5100 5 TPL5100 SNAS629B – JULY 2013 – REVISED AUGUST 2013 www.ti.com Timing Diagram PGOOD tfTCAL trTCAL tCAL TCAL tDTCAL tDTCAL tDONE ttDDONE t5 t DONE ttDPt trMOS_DRV MOS_DRV tfMOS_DRV ttMOS_DRVt ttDPt ttDDONEt Figure 4. Timing characteristics 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPL5100 TPL5100 www.ti.com SNAS629B – JULY 2013 – REVISED AUGUST 2013 Typical Performance Characteristics IDD vs Temperature IDD vs VDD TCAL Pulse Width vs Temperature TCAL Pulse Width vs VDD Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPL5100 7 TPL5100 SNAS629B – JULY 2013 – REVISED AUGUST 2013 www.ti.com APPLICATION INFORMATION The TPL5100 is a long-term timer for low power applications. The TPL5100 is designed for use in power cycled applications and provides selectable timing from 16 seconds to 1024 seconds. An additional supervisor feature is achieved through interfacing the TPL5100 to a power management IC. Configuration and Interface The time interval between 2 adjacent pulses is selectable through 3 digital input pins (D0, D1, D2) that can be strapped to either VDD (1) or GND (0). Eight possible time delays can be selected, as shown in Table 1. Table 1. Timer Delay Period D2 D1 D0 Time (s) Factor N 0 0 0 16 210 0 0 1 32 211 0 1 0 64 212 0 1 1 100 100*26 1 0 0 128 213 1 0 1 256 214 1 1 0 512 215 1 1 1 1024 216 Overview of the Timing Signals MOS_DRV, TCAL and DONE Figure 5 shows the timing of PGOOD, MOS_DRV, and TCAL with respect to DONE. The frame, A, shows a typical sequence after the PGOOD, low to high, transition. As soon as PGOOD is high, the internal oscillator is powered ON. At the end of the delay period (tDP), a MOS enable signal (MOS_DRV), followed by a calibration pulse, TCAL, is sent out. The calibration pulse starts after a half period of the internal oscillator from the falling edge of the MOS_DRV signal, and lasts one internal oscillator period. A "DONE" signal is received before the end of the MOS_DRV pulse. As soon as the TPL5100 receives the DONE signal, the counter resets and MOS_DRV and TCAL return to default conditions (MOS_DRV signal high and TCAL signal low). The frame, B, shows a non-standard sequence. A "DONE" signal has not been received before the end of the MOS_DRV pulse. The MOS_DRV signal stays low for 2 internal oscillator periods. The calibration pulse starts after a half period of the internal oscillator from the falling edge of the MOS_DRV signal, and lasts one internal oscillator period. The external power gating MOS stays ON for 2 internal oscillator periods. The frame, C, shows a standard sequence, but in this case, the TPL5100 receives the DONE signal when MOS_DRV is high and TCAL pulse is still high. As soon as the TPL5100 recognizes the DONE signal, the counter resets and MOS_DRV and TCAL return to default conditions (MOS_DRV signal high and TCAL signal low).The external power gating MOS stays ON for the execution time of the program of the connected µC. The frame, D, shows a typical PGOOD, high to low transition. As soon as PGOOD is low, the internal oscillator is powered OFF and the digital output pins, TCAL and MOS_DRV, are asynchronously reset by the falling edge of the PGOOD signal, such that TCAL resets at low logical values, while MOS_DRV resets at a high logical value. The external power gating MOS stays ON less than the execution time of the program of the connected µC. 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPL5100 TPL5100 www.ti.com SNAS629B – JULY 2013 – REVISED AUGUST 2013 INT. OSC. PGOOD TCAL DONE MOS_DRV A B C D Figure 5. Timing MOS_DRV, TCAL Supervisor Feature A critical event that can corrupt the memory of a µC is a voltage supply drop (supply lower than minimum operating range), and a reset of the µC is mandatory if this occurs. Since the TPL5100 is the right choice in systems which stay most of the time in deep sleep or completely OFF, due to its ultra low power consumption, it is fundamental that it takes into account the voltage drop events. The TPL5100 implements the supervisor feature when working with some power management ICs, which indicate the status of the supply voltage with a power good or battery good output. The supervisory functionality is enabled by simply connecting the Battery management power good output to the TPL5100 PGOOD pin. If this feature is not used connect the PGOOD pin to VDD. In case the power management IC detects a voltage drop while the µC is OFF, consequently lowering the PGOOD line, the TPL5100 resets its internal counter and does not allow the micro to turn ON until the PGOOD is high again. This series of events allows the µC to avoid working in an unsafe voltage supply condition. If the PGOOD signal is lowered while the µC is ON, the TPL51000 turns the µC OFF. The micro will be turned ON when PGOOD is high again and the selected delay is elapsed. Calibration Pulse The TPL5100 is based on an ultra-low power oscillator, which has a relatively low frequency and low accuracy; however, it shows very good cycle to cycle repeatability and very low temperature drift. In most of the applications, the accuracy of the oscillator is enough, but if a more accurate measure of the delay period is required, it is possible to measure the base period of the internal oscillator. A single pulse, which has the same duration as the base period of the internal oscillator, is present at the TCAL pin of the TPL5100. This pulse starts after a half period of the internal oscillator, from the falling edge of the MOS_DRV pulse. A µC connected to the TPL5100 can routinely measure the width of the TCAL pulse, using a counter and an external crystal. Once the base period of the TPL5100 is measured, the actual time delay is calculated by multiplying the measured period by a factor, N (see Table 1), dependent upon the nominal selected time delay. The resolution and the accuracy of the measurement depend upon the external crystal. Since the frequency of the internal oscillator of the TPL5100 is very stable, the measurement of the calibration pulse is suggested only when a high gradient of ambient temperature is observed. The measurement of the TCAL pulse is useful in battery-powered applications that implement a precise battery life counter in the µC. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPL5100 9 PACKAGE OPTION ADDENDUM www.ti.com 20-Aug-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) TPL5100DGSR ACTIVE VSSOP DGS 10 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 105 ASAA TPL5100DGST ACTIVE VSSOP DGS 10 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 105 ASAA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPL5100DGSR VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPL5100DGST VSSOP DGS 10 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPL5100DGSR VSSOP DGS 10 3500 367.0 367.0 35.0 TPL5100DGST VSSOP DGS 10 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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