SDRAM AS4SD4M16 Austin Semiconductor, Inc. 4 Meg x 16 SDRAM PIN ASSIGNMENT (Top View) Synchronous DRAM Memory FEATURES • • • • • • • • • • • • • OPTIONS • • • • 54-Pin TSOP Extended Testing Over -55°C to +125° C and Industrial Temp -40°C to 85° C WRITE Recovery ( tWR/ tDPL) tWR = 2 CLK Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable burst lengths: 1, 2, 4, 8 or full page Auto Precharge and Auto Refresh Modes Self Refresh Mode (Industrial, -40°C to 85° C only) 4,096-cycle refresh LVTTL-compatible inputs and outputs Single +3.3V ±0.3V power supply Longer lead TSOP for improved reliability (OCPL*) Short Flow / Long Flow Test Screening Options MARKING Configurations 4 Meg x 16 (1 Meg x 16 x 4 banks) Plastic Package - OCPL* 54-pin TSOP (400 mil) DG No. 901 Timing (Cycle Time) 8ns; tAC = 6.5ns @ CL = 3 ( tRP - 24ns) 10ns; tAC = 9ns @ CL = 2 -8 -10 Operating Temperature Ranges -Military (-55°C to +125° C) -Industrial Temp (-40°C to 85° C) XT IT 4M16 Note: “\” indicates an active low. 4 Meg x 16 Configuration 1 Meg x 16 x 4 banks Refresh Count 4K Row Addressing 4K (A0-A11) Bank Addressing 4 (BA0, BA1) Column Addressing 256 (A0-A7) KEY TIMING PARAMETERS SPEED GRADE -8 -10 -8 -10 CLOCK ACCESS TIME FREQUENCY CL = 2** CL = 3** 125 MHz – 6.5ns 100 MHz – 7ns 83 MHz 9ns – 66 MHz 9ns – SETUP TIME 2ns 3ns 2ns 3ns HOLD TIME 1ns 1ns 1ns 1ns For more products and information please visit our web site at www.austinsemiconductor.com *Off-center parting line **CL = CAS (READ) latency AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 SDRAM Austin Semiconductor, Inc. AS4SD4M16 GENERAL DESCRIPTION The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 6,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initi- AS4SD4M16 Rev. 1.5 10/01 ated at the end of the burst sequence. The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, randomaccess operation. The 64Mb SDRAM is designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SDRAM Austin Semiconductor, Inc. AS4SD4M16 TABLE OF CONTENTS Functional Block Diagram - 4 Meg x 16 ........................................ 4 Pin Descriptions ............................................................................. 5 Clock Suspend......................................................................... 22 Burst Read/Single Write ...........................................................22 Concurrent Auto Precharge ................................................. 23 Truth Table 2 (CKE) ......................................................................25 Truth Table 3 (Current State, Same Bank) ................................. 26 Truth Table 4 (Current State, Different Bank) ........................... 28 Absolute Maximum Ratings ........................................................ 30 DC Electrical Characteristics and Operating Conditions......... 30 ICC Specifications and Conditions .............................................. 30 Capacitance ..................................................................................... 31 AC Electrical Characteristics (Timing Table) ............................31 Functional Description ................................................................. 6 Initialization ............................................................................. 6 Register Definition ................................................................. 6 Mode Register ................................................................ 6 Burst Length ................................................................... 6 Burst Type ....................................................................... 7 CAS Latency ................................................................... 8 Operating Mode ............................................................. 8 Write Burst Mode .......................................................... 8 Commands ....................................................................................... 9 Truth Table 1 (Commands and DQM Operation) ......................... 9 Command Inhibit .................................................................... 10 No Operation (NOP) .................................................................10 Load Mode Register ............................................................. 10 Active ....................................................................................... 10 Read .......................................................................................... 10 Write ......................................................................................... 10 Precharge ................................................................................. 10 Auto Precharge ...................................................................... 10 Burst Terminate ...................................................................... 11 Auto Refresh .......................................................................... 11 Self Refresh ............................................................................. 11 Operation ..................................................................................... 12 Bank/Row Activation ............................................................ 12 Reads ........................................................................................ 13 Writes ....................................................................................... 19 Precharge................................................................................... 21 Power-Down...............................................................................21 AS4SD4M16 Rev. 1.5 10/01 Timing Waveforms Initialize and Load Mode Register ..................................... 34 Power-Down Mode ................................................................ 35 Clock Suspend Mode ........................................................... 36 Auto Refresh Mode .............................................................. 37 Self Refresh Mode ................................................................. 38 Reads Read - Without Auto Precharge ................................. 39 Read - With Auto Precharge ....................................... 40 Alternating Bank Read Accesses .............................. 41 Read - Full-Page Burst ......................................................... 42 Read - DQM Operation ................................................ 43 Writes Write - Without Auto Precharge ................................ 44 Write - With Auto Precharge ...................................... 45 Alternating Bank Write Accesses .............................. 46 Write - Full-Page Burst ................................................. 47 Write - DQM Operation ............................................... 48 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 SDRAM AS4SD4M16 Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM 4 Meg x 16 SDRAM CONTROL LOGIC BANK2 BANK3 COMMAND DECODE CKE CLK CS\ WE\ CAS\ RAS\ BANK1 MODE REGISTER REFRESH 12 COUNTER 1 2 12 ROW ADDRESS MUX 12 12 BANK0 ROWADDRESS LATCH & DECODER 4096 BANK 0 MEMORY ARRAY (4,096 X 256 X 16) 2 16 DQML, DQMH DATA OUTPUT REGISTER DQ0-DQ15 4096 SENSE AMPLIFIERS 2 16 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 2 A0, A10, BA 14 2 ADDRESS REGISTER BANK CONTROL LOGIC 256 (X16) 16 DATA INPUT REGISTER COLUMN DECODER 8 AS4SD4M16 Rev. 1.5 10/01 COLUMNADDRESS COUNTER/ LATCH 8 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 SDRAM AS4SD4M16 Austin Semiconductor, Inc. PIN DESCRIPTION TSOP PIN NUMBERS 38 SYMBOL CLK TYPE DESCRIPTION Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. 37 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), ACTIVE POWER-DOWN (row ACTIVE in either bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. 19 CS\ Input Chip Select: CS\ enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS\ is registered HIGH. CS\ provides for external bank selection on systems with multiple banks. CS\ is considered part of the command code. 16, 17 18 WE\, CAS\ RAS\ Input Command Inputs: RAS\, CAS\, and WE\ (along with CS\) define the command being entered. 15, 39 DQML, DQMH Input Input/Output Mask: DQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when DQM is sampled HIGH during a READ cycle. DQML corresponds to DQ0-DQ7; DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered same state when referenced as DQM. 20, 21 BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. 23-26, 29-34, 22, 35 A0-A11 Input Address Inputs: A0-A11 are sampled during the ACTIVE command (row address A0-A11) and READ/WRITE command (column address A0-A7, with A10 defining AUTO PRECHARGE) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0,BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. 2, 4, 5, 7, 8 10, 11, 13, 42 44, 45, 47, 48 50, 51, 53 DQ0- DQ15 36, 40 NC — 3, 9, 43, 49 6, 12, 46, 52 1, 14, 27 28, 41, 54 VDDQ VSSQ VDD VSS Supply Supply Supply Supply AS4SD4M16 Rev. 1.5 10/01 Input/ Data I/O: Data bus. Output No Connect: These pins should be left unconnected. DQ Power: Provide isolated power to DQs for improved noise immunity. DQ Ground: Provide isolated ground to DQs for improved noise immunity. Power Supply: +3.3V ±0.3V. Ground. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 SDRAM Austin Semiconductor, Inc. AS4SD4M16 FUNCTIONAL DESCRIPTION REGISTER DEFINITION In general, the 64Mb SDRAM is quad-bank DRAM (1 Meg x 16 x 4 banks) which operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-A11 select the row). The address bits ( x16: A0-A7) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Mode Register The Mode Register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 1. The Mode Register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the WRITE burst mode, and M10 and M11 are reserved for future use. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 (x16) when the burst length is set to two; A2-A7 (x16) when the burst length is set to four; and by A3-A7 (x16) when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Initalization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable, the SDRAM requires a 100µs delay prior to applying an executable command. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for Mode Register programming. Because the Mode Register will power up in an unknown state, it should be loaded prior to applying any operational command. AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 SDRAM AS4SD4M16 Austin Semiconductor, Inc. BURST TYPE Table 1 BURST DEFINITION Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1. Burst Length 2 4 8 Full Page (y) Starting Column Address A0 0 1 A0 A1 0 0 0 1 1 0 1 1 A0 A2 A1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 n = A0 - A9 location 0 - y A11 A10 A9 11 10 Reserved* 9 WB A8 A7 A6 A5 A4 A3 A2 3 BT 2 A1 A0 Order of Access Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1 1-0 0,1,2,3 1,2,3,0 2,3,0,1 3,0,1,2 0,1,2,3 1,0,3,2 2,3,0,1 3,2,1,0 0,1,2,3,4,5,6,7 1,2,3,4,5,6,7,0 2,3,4,5,6,7,0,1 3,4,5,6,7,0,1,2 4,5,6,7,0,1,2,3 5,6,7,0,1,2,3,4 6,7,0,1,2,3,4,5, 7,0,1,2,3,4,5,6 Cn, Cn+1, Cn+2, Cn+3, Cn+4… …Cn-1, Cn… 0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4 4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0 Not Supported Address Bus Mode Register(Mx) 8 7 Op Mode 6 5 4 CAS Latency M2 0 0 0 0 1 1 1 1 * Should program M11, M10=0,0 to ensure compatibility with future devices. 1 0 Burst Length M1 0 0 1 1 0 0 1 1 M3 0 1 M9 0 1 M7 0 - M6 - M0 Defined - Burst Length M3=0 M3=1 1 1 2 2 4 4 8 8 Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved Burst Type Sequential Interleave M6 0 0 0 0 1 1 1 1 M8 0 - M0 0 1 0 1 0 1 0 1 M5 0 0 1 1 0 0 1 1 M4 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved Operating Mode Standard Operation All other states reserved Write Burst Mode Programmed Burst Length Single Location Access FIGURE 1 MODE REGISTER DEFINITION AS4SD4M16 Rev. 1.5 10/01 NOTE: 1. For full-page accesses: y = 256 (x16). 2. For a burst length of two, A1-A7 (x16) select the block-of-two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2-A7 (x16) select the block-of-four burst; A0-A1 select the starting column within the block. 4. For a burst length of eight, A3-A7 (x16) select the clock-of-eight burst; A0-A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0-A7 (x16) select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-A7 (x16) select the unique column to be accessed, and Mode Register bit M3 is ignored. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 SDRAM AS4SD4M16 Austin Semiconductor, Inc. CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n+m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Table 2 below indicates the operating frequencies at which each CAS latency setting can be used. T0 T1 T2 Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. Table 2 T3 CAS LATENCY CLK 123 123 12 123 123 12 123 12 COMMAMD 123 123 123 12 READ 123 123 123 123 NOP tLZ DQ tAC 123 123 123 123 123 123 12 123 12 123 123 12 123 12 123 123 12 123 12 123 123 12 123 12 123 123 12 123 NOP tOH DOUT ALLOWABLE OPERATING FREQUENCY (MHz) 123 123 123 123 SPEED CAS LATENCY = 2 123 123 123 123 123 -8 -10 ≤ 83 ≤ 66 CAS LATENCY = 3 ≤ 125 ≤ 100 CAS Latency = 2 T0 T1 T2 T3 T4 CLK 12 12345 12345 12 12345 COMMAMD 12 12345 READ 12 123 123 123 123 NOP 123 123 123 123 NOP tLZ DQ 123 123 123 123 NOP 123 123 123 123 tOH 1234 12 123 123 11 1234 12 123 123 1234 12 123 11 D 1234 12123 123 123 OUT 1234 12 123 123 1 1234 1234 1234 1234 1234 tAC CAS Latency = 3 123 123 123 UNDEFINED 123 123 123 DON’T CARE Figure 2 CAS LATENCY AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 SDRAM AS4SD4M16 Austin Semiconductor, Inc. COMMANDS Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Two additional Truth Tables appear following the Operation section; these tables provide current state/next state information. TRUTH TABLE 1- Commands and DMQ Operation (Note: 1) NAME (FUNCTION) COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (select bank and activate row) READ (select bank and column and start READ burst) WRITE (select bank and column and start WRITE burst) BURST TERMINATE PRECHARGE (deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z CS\ H L L L L L L RAS\ X H L H H H L CAS\ X H H L L H H L L L H X X X 6,7 L - L - L - L - X L H OpCode - X Active High-Z 2 8 8 WE\ DQM X X H X H X H X L X L X L X ADDR DQs NOTES X X X X Bank/Row X 3 Bank/Col X 4 Bank/Col Valid 4 X Active Code X 5 NOTE: 1. 2. 3. 4. 5. 6. 7. 8. AS4SD4M16 Rev. 1.5 10/01 CKE is HIGH for all commands shown except SELF REFRESH. A0-A11 define the op-code written to the Mode Register. A0-A11 provide row address, and BA0, BA1 determine which bank is made active. A0-A7 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.” This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 SDRAM Austin Semiconductor, Inc. COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS\ is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The Mode Register is loaded via inputs A0-A11. See Mode Register heading in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A7 (x16) selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the READ burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data. AS4SD4M16 Rev. 1.5 10/01 AS4SD4M16 WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A7 (x16) selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the WRITE burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. AUTO PRECHARGE AUTO PRECHARGE is a feature which performs the same individual-bank PRECHARGE function described above, without requiring an explicit command. This is accomplished by using A10 to enable AUTO PRECHARGE in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where AUTO PRECHARGE does not apply. AUTO PRECHARGE is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. AUTO PRECHARGE ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Operation section of this data sheet. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 SDRAM Austin Semiconductor, Inc. BURST TERMINATE The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet. AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analagous to CAS\-BEFORE-RAS\ (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an AUTO REFRESH command. The 64Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms *(tREF), regardless of width option. Providing a distributed AUTO REFRESH command every 15.625µs/3.906µs will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRC), once every 64ms/ 16ms. AS4SD4M16 SELF REFRESH (Industrial -40°C to +85°C Only) The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become “Don’t Care,” with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR, because time is required for the completion of any internal refresh in progress. If during normal operation AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode. The self refresh option is not available for the -55° to +125° screening option. *64ms for -40° to +85° C ( Industrial Temperatures) and 16ms for -55° to +125°C (Military Temperatures) AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 SDRAM AS4SD4M16 Austin Semiconductor, Inc. OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 30ns with a 90 MHz clock (11.11ns period) results in 2.7 clocks, rounded to 3. This is reflected in Figure 4, which covers any case where 2 < tRCD CLK 123456789012 123456789 123456789 1123456789012 12 123456789 123456789012 12 CS\ 1 1123456789012 123456789 11 1123456789012 123456789 123456789012 123456789 1 RAS\ 1 1123456789012345 123456 11 1123456789012345 123456 CAS\ 1 123456789012345 123456 1 1123456789012345 123456 11 1123456789012345 123456 WE\ 123456789012345 123456 1234567890123456 1234 1234567890123456 12 1234 12 1234567890123456 12 ROW ADDRESS 1234 A0-A11 12 11234567890123456 1234 12 11234567890123456 1234 12 1234567890123456 1234 12 BANK ADDRESS BA0, 1 1 (MIN)/ tCK ≤ 3. (The same procedure is used to convert other specification limits from time units to clock cycles). A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD. T0 HIGH CKE 12345 123456789012 12345 123456789012 12 12 12345 12 123456789012 12 12345 123456789012 12 12 12345 123456789012 12 12 123456789012 12345 12 12 123456789 123456789 1 1 123456789 1123456789 123456789 112345678911 123456789 1123456789 1 123456789 1123456789 1234567891 123456789 123 1234567890123 123 1234567890123 12 12 12 1234567890123 12 123 123 1234567890123 1 12 123 11234567890123 12 123 11234567890123 12 Figure 3 ACTIVATING A SPECIFIC ROW IN A SPECIFIC BANK T2 T1 T4 T3 CLK COMMAND 12 1234 1234 12 1234 12 1234 12 1234 12 ACTIVE 12345 12345 12345 12345 12345 NOP 12345 12345 12345 12345 12345 t RCD NOP 12345 12345 12345 12345 12345 12345 12345 READ or 12345 12345 12345 WRITE 1234 1234 1234 DON’T CARE Figure 4 EXAMPLE: MEETING tRCD (MIN) WHEN 2<tRCD (MIN)/tCK<3 AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12 SDRAM AS4SD4M16 Austin Semiconductor, Inc. READs READ bursts are initiated with a READ command, as shown in Figure 5. The starting column and bank addresses are provided with the READ command, and AUTO PRECHARGE is either enabled or disabled for that burst access. If AUTO PRECHARGE is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, AUTO PRECHARGE is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 6 shows general timing for each possible CAS latency setting. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of alonger burst which is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. T0 CLK CKE CLK HIGH 1 12345678901 12345678 1 123456 1234567890 1 12345678901 12345678 1 123456 123456789011 1 CS\ 1 1234567890123 1 12345 1 12345678 112345678 11 1234567890123 1 12345 1 12345678 112345678 1234567890123 12345 1 12345678 1123456781 RAS\ 1 12345678901 1 12345678 1 123456 1234567890 1 1 12345678901 1 12345678 1 123456 1234567890 1 CAS\ 1 12345678901 123456789011 12345678 1 123456 1 1234567890123 1 123456 1 12345678 112345678 1 1234567890123 1 123456 1 12345678 112345678 1234567890123 123456 1 12345678 11234567811 WE\ 1 12345678901234 1 123 12 12 12345678901234 1 123 COLUMN ADDRESS1234 12 1234 1212345678901 1234567890111 A0-A7: x16 12345678901234 1 123 12 1234 12 123456789011 12345678901234 1 123123 12 12345678 1 123 11234 12123456789011 12345678901234 123123 12 12345678 1 123 11234 12123456789011 A8, A9, A11: x16 1 12345678901234 1 123 12 1234 12 12345678901 ENABLE AUTO PRECHARGE 12345678901234 1 123 12 1234 12 1234567890111 1 123 12 1234 12 123456789011 A10 12345678901234 DISABLE AUTO PRECHARGE 12345678901234 1 123 12 1234 12123456789011 12345678901234 1 123 12 12 123456789011 BA0, 1 12345678901234 123 BANK ADDRESS 1234 1234 12345678901 Figure 5 READ COMMAND AS4SD4M16 Rev. 1.5 10/01 T2 T1 12 123 123 12 123 COMMAND12 123 READ 12 123 123 123 123 NOP tLZ 123 123 123 123 NOP T3 123 123 123 123 tOH 1234 1234567 1234567 1234 1234567 1234 D OUT 1234567 1234 tAC DQ CAS Latency = 2 T0 T2 T1 T3 T4 CLK COMMAND 12 123 1234 123 123 12 123 READ1234 12 1234 NOP 123 123 tLZ NOP 123 123 123 NOP t OH 1234567 1234 1234567 1234 1234567 1234 D OUT 1234567 1234 tAC DQ 123 123 123 CAS Latency = 3 Figure 6 CAS LATENCY 123 123 123 123DON’T CARE 1234 1234 1234 1234UNDEFINED Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13 SDRAM AS4SD4M16 Austin Semiconductor, Inc. This is shown in Figure 7 for CAS latencies of two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can T0 T1 be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Figure 8, or each subsequent READ may be performed to a different bank. T2 T3 T4 T6 T5 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DOUT n+3 ○ ○ ○ ○ ○ ○ ○ ○ ○ T5 DOUT b ○ ○ ○ ○ DOUT n+2 ○ T4 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ T3 123456 1234567 123 1234567 1234567123456 123 123 123 123456 1234567 1234567 1234567 123456 1234567 123 1234567 123 1234567123456 123456 123 123 123456 1234567 1234567 1234567123456 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ T2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ T1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ T0 DOUT n+1 NOP X=1 cycle 123456 12345671234567 123 1234567123456 123 BANK, COL b DOUT n CAS Latency = 2 NOP READ 1234567 1234567 123 1234567 1234 1234567 1234567 123 1234567 1234567 123 1234 12345671234567 1234567 1234567 123 123 1234567 1234 123 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 123 1234567 1234 1234567 1234567 1234567 123 123 1234567 1234 123 1234567 1234567 12345671234567 1234567 ○ DQ NOP ○ ○ ○ ○ ○ ○ ○ ○ BANK, COL n ADDRESS NOP ○ NOP READ COMMAND ○ ○ ○ ○ ○ ○ ○ CLK T7 T6 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DOUT b ○ ○ ○ ○ ○ NOTE: Each READ command may be to either bank. DQM is LOW. ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DOUT n+3 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DOUT n+2 ○ ○ NOP X=21234 cycle 1234567 1234567 1234567 1234567 123 1234567 123456 123 1234567 1234567 1234567 1234 1234567 1234567 123 123456 123 1234567 1234567 1234567 1234 1234567 12345671234567 123 1234567 123456 123 1234567 123 1234567 1234567 1234 1234567 1234567 123 1234567 123456 1234567 1234567 1234567 1234 1234567 1234567 123 1234567 123456 123 1234567 12345671234567 12345671234567 1234561234567 1234567 ○ ○ NOP ○ ○ ○ ○ ○ ○ CAS Latency = 3 NOP ○ ○ ○ ○ ○ DOUT n+1 ○ ○ BANK, COL b ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DOUT n ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ READ ○ ○ ○ ○ ○ ○ ○ ○ ○ DQ NOP 1234567 1234 123456 1234567 1234 123456 123456 1234 1234567 1234567 1234 123456 1234 123456 1234 1234567 1234567 1234 1234561234567 1234567 1234 123456123456 123456 1234 1234567 1234567 1234 123456 1234567 1234 123456 123456 1234 1234567 1234567 1234 123456 1234567 1234 123456 123456 1234 1234567 1234567 1234561234567 123456123456 1234567 ○ ○ NOP ○ ○ ○ ○ ○ ○ BANK, COL n ○ ADDRESS NOP ○ ○ ○ READ ○ COMMAND ○ ○ ○ ○ CLK 1234 1234 1234 1234DON’T CARE Figure 7 CONSECUTIVE READ BURSTS AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 14 SDRAM AS4SD4M16 Austin Semiconductor, Inc. T0 T1 T2 T3 T4 T5 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DOUT a ○ ○ ○ ○ DOUT n ○ ○ ○ ○ ○ T0 T1 T2 T3 ○ ○ T4 ○ ○ ○ ○ ○ ○ ○ ○ CAS Latency = 2 DOUT m ○ ○ ○ ○ DOUT x ○ ○ ○ ○ ○ ○ ○ ○ ○ DQ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ BANK, COL m ○ ○ ○ ○ ○ ○ BANK, COL x BANK, COL a ○ ○ ○ 123456 1234567 123 123456 1234 123456 123456 123456 1234567 123 123456 1234 123456 123456 1234567 123 123456 1234 123456123456 123456 123 1234 123456 1234567 123456 123456 123 1234 123456 1234567 123456 123456123456 123456 ○ ○ ○ ○ ○ NOP NOP ○ READ ○ ○ ○ ○ READ ○ ○ READ ○ ADDRESS BANK, COL n ○ ○ ○ ○ READ ○ COMMAND ○ ○ ○ ○ ○ CLK T6 T5 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ NOTE: Each READ command may be to either bank. DQM is LOW. ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DOUT x ○ ○ ○ ○ DOUT a ○ ○ ○ NOP ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ CAS Latency = 3 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DOUT n ○ DQ NOP 123456 1234567 1234 1234567 123 1234 123456 123456 12345671234567 1234 1234567 1234567123456 123 123456 1234 123456123456 123456 123456 1234567 1234 1234567 1234567 123 123456 1234 123456 123456 123456 1234567 1234 1234567 1234567 123 123456 1234 123456 123456 1234567 1234 1234567 1234567 123 123456 1234 123456123456 123456 ○ ○ ○ ○ ○ ○ ○ ○ BANK, COL m NOP ○ ○ ○ ○ ○ ○ ○ ○ READ ○ ○ BANK, COL x ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ BANK, COL a READ ○ ○ ○ ADDRESS BANK, COL n READ ○ READ ○ COMMAND ○ ○ ○ ○ CLK DOUT m 1234 1234 1234 1234 DON’T CARE Figure 8 RANDOM READ ACCESSES AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 15 SDRAM AS4SD4M16 Austin Semiconductor, Inc. T0 T1 T2 T0 T1 T2 T3 T4 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ WRITE ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 123456 123456 123456 123456 ○ ○ ○ ○ ○ ○ DOUT n ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ tCK tHZ BANK, COL b ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 123456 123456 123 123456 12345 12 12345 123 123456 123456 123456 123 12345 12 123 123456 123456 123456123456 123456 1234512345 12 12345 123456 123 123 123456 123 123456123456 1234512345 12 123 123456 ○ DQ NOP ○ BANK, COL n NOP ○ ADDRESS NOP ○ READ ○ COMMAND ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 12345 12345 12345 DQM 12345 ○ CLK ○ Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. The DQM input is used to avoid I/O contention, as shown in Figures 9 and 10. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z), regardless of the state of the DQM signal. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 10 shows the case where the additional NOP is needed. DIN b t DS NOTE: A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. If a CAS latency of one is used, the DQM is not required. Figure 9 READ TO WRITE T3 T5 T4 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 123456 123456 123456 123456 ○ ○ ○ ○ DIN b ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ BANK, COL b ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ tHZ DOUT n ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 12345 123456 123 12345 123456 123 12345 123456 123 12345 12345 12 12345 123456 123 12345 123456 123 12345 123456 123 12345 12345 12 12345 123456 123 12345 123456 123 12345 123 123456 12345 12345 12 12345 12345612345 123 12345612345 123 123 12345612345 12345 12 ○ ○ ○ ○ ○ WRITE ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ NOP ○ ○ ○ NOP ○ ○ NOP ○ ○ DQ ○ ADDRESS BANK, COL n NOP ○ ○ READ ○ COMMAND ○ ○ ○ ○ ○ ○ ○ ○ ○ 1234 1234 1234 1234 DQM ○ CLK ○ ○ ○ ○ ○ ○ t DS NOTE: A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. 123 123 123 DON’T CARE Figure 10 READ TO WRITE WITH EXTRA CLOCK CYCLE AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 16 SDRAM AS4SD4M16 Austin Semiconductor, Inc. desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst CLK ○ NOP NOP ACTIVE ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ BANK a, ROW 1234567 1234567 1234567 1234567 1234567 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DOUT n+3 ○ ○ ○ ○ DOUT n+2 ○ ○ ○ ○ ○ DOUT n+1 T0 T1 T2 T3 ○ ○ ○ ○ ○ T4 ○ ○ ○ ○ ○ ○ CAS Latency = 2 ○ ○ ○ ○ DOUT n ○ ○ ○ ○ DQ ○ ○ ○ ○ ○ ○ ○ BANK (a or all) ○ ○ ○ ○ ○ 1234567 1234567 1234567 123 1234567 12345671234567 1234567 1234567 123 123 1234567 1234567 123 1234567 1234567 123 1234567 1234567 123 1234567 1234567 123 123 123 1234567 1234567 1234567 1234567 X = 1 cycles ○ ○ ○ ADDRESS ○ ○ BANK a, COL n ○ ○ ○ ○ ○ ○ 123456 1234567 1234 1234567 1234567 123 1234567 123456 1234567 1234 1234567 12345671234567 123 1234567 1234567 123 123456 1234 1234567 1234567 1234567 123 1234567 1234567 123 123456 1234 1234567 1234567 1234567 123 1234567 1234567 123 1234 123 123456 1234567 1234567 12345671234567 123 1234567 ○ ○ ○ ○ ○ PRECHARGE ○ ○ ○ ○ NOP RP T7 ○ ○ ○ ○ ○ ○ ○ NOP ○ ○ ○ NOP ○ READ ○ ○ ○ ○ ○ ○ t ○ COMMAND T6 T5 ○ T4 ○ T3 ○ T2 ○ T1 ○ T0 ○ A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that AUTO PRECHARGE was not activated), and a full-page burst maybe truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 11 for each possible CAS latency; data element n + 3 is either the last of a burst of four or the last T6 T5 T7 ○ ○ ○ ○ ○ ○ 1234567 1234567 1234567 1234567 1234567 ○ ○ ○ 1234 1234DON’T CARE 1234 ○ DOUT n+3 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DOUT n+2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ACTIVE BANK a, ROW ○ Figure 11 READ TO PRECHARGE NOP 1234567 1234567 123 X 1234 = 123456 2 cycles 123456 1234567 1234 123456 123456 1234567 123 1234567 1234 123456 123456 1234567 123 1234567 1234 123456123456 1234567 123 1234567 123456123456 1234567 ○ NOTE: DQM is LOW. AS4SD4M16 Rev. 1.5 10/01 NOP ○ ○ ○ ○ ○ ○ DOUT n+1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ CAS Latency = 3 BANK (a or all) ○ ○ DOUT n RP ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ PRECHARGE ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DQ NOP 1234567 1234561234567 123 1234 1234561234567 1234567 123 1234567 123456 123 1234567 1234 123456 1234567 1234567 123 1234567 123456 123 1234567 1234 123456 1234567 1234567 123 1234567 1234561234567 123 1234 1234561234567 1234567 123 1234567 1234567 ○ ○ ADDRESS ○ ○ BANK a, COL n NOP ○ ○ ○ NOP ○ ○ READ ○ COMMAND ○ ○ ○ t ○ CLK Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 17 SDRAM AS4SD4M16 Austin Semiconductor, Inc. with AUTO PRECHARGE. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts T0 T1 T2 may be truncated with a BURST TERMINATE command, provided that AUTO PRECHARGE was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 12 for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst. T3 T4 T6 T5 ○ ○ ○ NOP ○ ○ ○ ○ NOP ○ ○ ○ ○ ○ ○ ○ ○ ○ BURST TERMINATE ○ ○ ○ ○ ○ ○ ○ ○ NOP ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ X = 1 cycles 1234567 123456 123 123456 1234567 1234 1234567 1234567 123 123456 123 123456 1234 123456 1234 123456 1234567 123456 123 123456 1234567 1234 1234567 1234567 123 123456 123 123456123456 123456 1234 123456123456 123456 1234 123456123456 123456 123 1234 123 123 1234 1234 1234567 123456 123456 1234567 1234567 1234567 123456 123456 123456 123456 123456 123456 123 1234 123 123 1234 1234 1234567 123456123456 12345671234567 1234567123456 123456123456 123456123456 123456123456 123456 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DOUT n+3 ○ ○ ○ ○ ○ ○ DOUT n+2 ○ ○ DOUT n+1 T0 ○ ○ ○ ○ ○ T3 ○ T2 ○ T1 ○ ○ CAS Latency = 2 ○ ○ ○ ○ DOUT n ○ ○ ○ ○ DQ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ NOP ○ ○ ○ ○ ADDRESS BANK, COL n NOP ○ READ ○ COMMAND ○ ○ ○ CLK T4 T6 T5 T7 ○ ○ NOP NOP ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ NOP ○ ○ ○ ○ ○ ○ ○ ○ ○ BURST TERMINATE ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ NOTE: DQM is LOW. ○ ○ ○ ○ ○ DOUT n+3 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DOUT n+2 ○ DOUT n+1 ○ ○ ○ ○ ○ ○ ○ ○ ○ CAS Latency = 3 ○ ○ ○ ○ DOUT n ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DQ NOP X123 =123456 2 cycles 123456 1234567 1234 123456123456 12345671234567 1234 12345671234567 123 1234567123456 123 12345671234567 123 123456123456 123 1234567 1234 123456 123456 1234567 1234 1234567 1234567 123 1234567 1234567 123 123456 123 123456 123456 1234567 123 1234567 123456 123 123456 1234567 1234 123456 123456 1234567 1234 1234567 1234567 123 1234567 123 1234567 123456 123 123456 123456 1234567 123 1234567 123456 123 1234567 1234 123456123456 12345671234567 1234 12345671234567 123 123 1234567123456 123 123456123456 12345671234567 123 123456123456 123 123456 ○ ○ NOP ○ ○ ○ ○ ADDRESS BANK, COL n NOP ○ READ ○ COMMAND ○ ○ ○ CLK 1234 1234 1234DON’T CARE Figure 12 TERMINATING A READ BURST AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 18 SDRAM AS4SD4M16 Austin Semiconductor, Inc. the last of a burst of two or the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 16, or each subsequent WRITE may be performed to a different bank. T0 T1 T2 T3 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DIN n ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 123456 123456 123 123456 123456 123 123456 123456 123 123456 123456 123456 123 123456 123456 123 123456 123456 123 123 123 123 123456 123456 123456 123456 123456 123456 123456 123456 123456123456 123456123456 123456123456 12345 123456 123 123456 123456 123 12345 123456 123 123456 123 123 123456 123 123456 123456 123456 DIN n+1 12345 12345 123456 123 123456 123456 123 ○ BANK, COL n NOP NOP ○ ADDRESS NOP ○ WRITE ○ COMMAND DQ ○ ○ ○ ○ ○ CLK ○ WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 13. The starting column and bank addresses are provided with the WRITE command, and AUTO PRECHARGE is either enabled or disabled for that access. If AUTO PRECHARGE is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, AUTO PRECHARGE is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see Figure 14). A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 15. Data n + 1 is either NOTE: Burst length = 2. DQM is LOW. Figure 14 WRITE BURST T0 CLK T1 T2 ○ ○ ○ ○ ○ ○ ○ 123456 123456 123456 123456 ○ DIN b ○ DIN n+1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DIN n WRITE BANK, COL b ○ DQ 123456 123456 123 123456 123456 123 123 123456 123456 123456 123456 123 ○ ○ ○ BANK, COL n ○ ADDRESS NOP ○ ○ WRITE ○ COMMAND ○ 1 12345678901 12345678 1 12345 12345678901 12 12345678901 1 12345678 1 12345 1234567890111 12 12345678901 112345678901 12345678 1 12345 12 1 12345678901234 1 12345 12 12345678 12345678 1 1 12345678901234 1 12345 12 12345678 112345678 RAS\ 1 12345678901234 12345 12 12345678 11234567811 12345678901 1 12345678 1 12345 12345678901 12 12345678901 12345678 1 12345 1234567890111 12 CAS\ 1 12345678901 1 12345678 1 123456 12 1234567890 1 12345678901 1 12345678 1 123456 12 1234567890 12345678901 12345678 1 123456 12 123456789011 WE\ 1 123456789012345 1 123 1 123 1234567890121 12 123456789012345 1 123 1 123456789012 12 A0-A7: x16 123456789012345 1 123 1 COLUMN ADDRESS123 123 12 12345678901211 123456789012345 1 123 1 123456789 12 123 12 123456789012 12 123456789012345 123 1123 123 123456789 12 123123 12 123 12345678901211 12 A8, A9, A11: x16 1 123456789012345 123 123 123456789012 ENABLE 123456789012345 1 123 1 AUTO PRECHARGE 123 1234567890121 12 1 123 1 123 12 1234567890121 A10 123456789012345 DISABLE AUTO PRECHARGE 123456789012345 1 123 1 123 123456789012 12 1 123456789012345 1 123 1 123456789012 12 BA0,1 123456789012345 1 123 1 BANK ADDRESS 123 123 12 12345678901211 CS\ ○ ○ HIGH ○ CLK CKE NOTE: DQM is LOW. Each WRITE command may be to any bank. 1234 1234 1234 1234DON’T CARE Figure 15 WRITE TO WRITE Figure 13 WRITE COMMAND AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 19 SDRAM AS4SD4M16 Austin Semiconductor, Inc. Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be immediately followed by a subsequent READ command. Once the READ command is registered, the data inputs will be ignored, and WRITEs will not be executed. An example is shown in Figure 17. Data n+1 is either the last of a burst of two or the last desired of a longer burst. Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that AUTO PRECHARGE was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is registered. The Auto Precharge mode requires a tWR of at least one clock plus time (8ns), regardless of frequency. In addition, when truncating a T0 T1 T2 WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in Figure 18. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with AUTO PRECHARGE. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. T3 T0 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ IN ○ ○ ○ ○ ○ ○ ○ DIN n NOTE: DQM coulc remain LOW in this example if the WRITE burst is a fixed length of 2. 1234 1234 1234 DON’T CARE Figure 18 WRITE TO PRECHARGE T5 ○ ○ NOP ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ OUT ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ NOP ○ DIN n NOP ○ DQ READ ACTIVE 12345 123456 123 123456 12345 12 12345 123 12345 12345 123456 12 12345 12345 123456 123 123456 12345 12 12345 123 12345 12345 123456 12 12345 BANK, 123456 12345 123456 123 12345 12 12345 123 12345 12345 123456 12 12345 123456 COL b 123456 123 1234512345 12 123 1234512345 12345612345 12 12345 12345 123456 123 123456 12345 12 12345 123456 123 123456 12345 12 123456 123 123456 12345 12 DIN n+1 12345 12345 123456 123 123456 12 12345 DOUT b D b+1 ○ ○ ○ ○ ○ ○ BANK, COL n ○ ADDRESS NOP NOP 1234 12345 123 1234 12 1234 12 1234 12 1234 123451234 123 1234 1234 BANK 12345 12 12345 12341234 12 1234 1234 BANK 1234 12 1234 1234 123451234 123 1234 (a or all) 12345 12 12341234 12 1234 a , 1234 12 t WR ROW 1234 12345 12 1234 12 1234 12 123 1234 123 1234 1234 123451234 12 1234 123412345 12 12345 12341234 12 1234 123 12341234 1234 123 1234 123451234 12 123412345 12 12341234 12 123 12341234 123 1234 D n+1 1234 ○ BANK a, COL n ○ T4 NOP ○ T3 PRECHARGE ○ T2 NOP ○ DQ NOP ○ T1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ADDRESS ○ ○ ○ ○ ○ ○ DIN m ○ WRITE ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ COMMAND ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DIN x tRP ○ ○ BANK, COL m ○ DIN a 1234 1234 DQM 12345 12345 12345 ○ DIN n BANK, COL x WR= 2 CLK 1234(“A2 version”) ○ BANK, COL a t WRITE ○ BANK, COL n WRITE CLK WRITE T6 ○ ○ ○ ○ WRITE Figure 16 RANDOM WRITE CYCLES COMMAND T5 ○ ○ ○ WRITE NOTE: Each WRITE command may be to any bank. DQM is LOW. T0 T4 ○ DQ T3 ○ ADDRESS T2 ○ COMMAND T1 CLK CLK NOTE: The WRITE command may be to any bank, and the READ command may be to any bank. DQM is LOW. CAS latency = 2 for illustration. Figure 17 WRITE TO READ AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 20 SDRAM AS4SD4M16 Austin Semiconductor, Inc. Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 19, where data n is the last desired data element of a longer burst. T0 T1 T2 ○ Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in either bank, this mode is referred to as active power-down. Entering powerdown deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms/16ms) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS). ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 12345 12345 123456 12345 12345 123456 12 12345 12345 12 123456 (ADDRESS) 12345 12345 123456 12 12345 123456 123 12345 123456 123 12345 123456 123 12345 123456 (DATA) 123 ○ ○ ○ DIN n ○ DQ ○ ○ ○ ○ ○ ADDRESS BANK, COL n The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. POWER-DOWN ○ ○ NEXT COMMAND ○ ○ BURST TERMINATE WRITE ○ COMMAND ○ CLK PRECHARGE NOTE: DQMs is LOW. Figure 19 TERMINATING A WRITE BURST CLK CKE HIGH 12 123456789012 12345678 1 12345 12345678901 12 12 123456789012 12 12345678 1 12345 12345678901 12 12 123456789012 12345678 1 12345 12 12345678901 12 CS\12 123456789012 12 12345678 1 12345 12345678901 1 12 123456789012 12345678 1 12345 12345678901 1 12 RAS\12 12345678901234 12 12345 12 12345678 123456781 1 12345678901234 12 12345 12 12345678 12345678 1 11 CAS\12 12345678901234 12345 12 12345678 12345678 1 123456789012 12 12345678 1 12345 12345678901 12 12 123456789012 12 12345678 1 12345 12345678901 12 12 12 12345678 1 12345 12 12 12345678901 WE\123456789012 1234567890123456 12 12 123456789012345678901234 12 1234567890123456 12 123456789012345678901234 12 A0-A912 123456789012345 12 123 12 123 123456789012 1 12 ALL BANKS 123456789012345 12 123 12 123 123456789012 1 12 A1012 123456789012345 123 12 123 1123456789012 12 BANK SELECTED 1234567890123456 12 123 12 123 123456789012 12 1234567890123456 12 123 12 123 123456789012 1 12 1234567890123456 12 123 12 123 1123456789012 12 BA CLK t CKS >tCKS CKE COMMAND NOP 12345678 123456789012345678 12345678 12345678 123456789012345678 12345678 12345678 123456789012345678 12345678 12345678 123456789012345678 12345678 12345678 123456789012345678 12345678 12345678 123456789012345678 12345678 NOP 1234 1234 1234 1234 1234 1234 1234 ACTIVE 1234 1234 1234 1234 1234 All banks idle Input buffers gated off BANK ADDRESS Enter power-down mode. Figure 20 PRECHARGE COMMAND Exit power-down mode. Figure 21 POWER-DOWN tRCD t RAS tRC 1234 1234 1234 1234 DON’T CARE 1 AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 21 SDRAM AS4SD4M16 Austin Semiconductor, Inc. CLOCK SUSPEND BURST READ/SINGLE WRITE The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See examples in Figures 22 and 23.) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. The burst read/single write mode is entered by programming the write burst mode bit (M9) in the Mode Register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9=0). T0 T1 T2 T3 T4 T5 T0 CLK T1 T2 T3 T4 T5 T6 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ CKE ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DOUT n+3 ○ ○ ○ ○ ○ DOUT n+2 ○ ○ ○ ○ ○ DOUT n+1 DOUT n ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DQ ○ n+2 12345 12345 12345 BANK, COL n ○ D IN NOP ○ DIN n+1 ○ ○ 12345 123456 123 12 12345 123 12345 12345 123456 123 12 12345 123 12345 12345 123456 123 12 12345 123 12345 1234 12345 1234 12345 12 12 1234 12345 1234 12345 NOP NOP NOP 1234 12345 12 1234 12345 12 1234 12345 12 12345 123 123 1234 1234 12 1234 123451234 12 123451234 12 123451234 12 1234 1234512345 123 12345 123 12341234 1234 12341234 12 1234 1234 12345 12 1234 12345 12 1234 12345 12 1234 123 12345 12345 123 1234 1234 1234 12 1234 123451234 123451234 12 123451234 12 1234512345 12341234 12341234 1234 NOP ○ ○ ○ READ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DQ ○ D IN n ○ 12345 12345 123 12345 12345 123 12345 123 12345 ○ BANK, COL n ○ 12345 12345 123 12345 12345 123 12345 123 12345 12345 123456 1234 123456 123456 123 12345 123456 1234 123456 123456 NOP 123 COMMAND NOP 12345 1234 123456 123456 123 123456 12345 123456 123 123456 123 12345 123456 123456 123 12345 12 12345 123456 123 123456 123 12345 123456 12345612345 123 12345 1234512345 12 12345ADDRESS 12345 123456 123 123456 123 12345 123456 12345612345 123 1234512345 12 ○ ADDRESS WRITE ○ NOP ○ COMMAND INTERNAL CLOCK ○ ○ ○ ○ ○ ○ INTERNAL CLOCK ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ CKE ○ ○ ○ ○ ○ ○ ○ ○ ○ CLK NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and DQM is LOW. 123 123 NOTE: For this example, burst length = 4 or greater, and DQM is LOW. AS4SD4M16 Rev. 1.5 10/01 DON’T CARE Figure 23 CLOCK SUSPEND DURING READ BURST Figure 22 CLOCK SUSPEND DURING WRITE BURST Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 22 SDRAM AS4SD4M16 Austin Semiconductor, Inc. CONCURRENT AUTO PRECHARGE READ with AUTO PRECHARGE 1. Interrupted by a READ (with or without AUTO PRECHARGE): A READ to bank m will interrupt a READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 24). 2. Interrupted by a WRITE (with or without AUTO PRECHARGE): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prir to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25). An access command (READ or WRITE) to another bank while an access command with AUTO PRECHARGE enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. ASI SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below. T0 T1 T2 T3 T4 T5 T6 T7 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DOUT d+1 ○ ○ CAS Latency = 3 (BANK m) ○ NOTE: DQM is LOW. ○ ○ ○ ○ CAS Latency = 3 (BANK n) ○ ○ ○ ○ ○ ○ ○ ○ DOUT d ○ ○ ○ ○ ○ ○ ○ DOUT a+1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ tRP-BANK m ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ NOP Idle ○ ○ ○ ○ ○ DOUT a ○ DQ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ BANK m, COL d NOP Precharge 123456 123456 123 123456 1234567 1234 123456 1234567 123 1234567 1234 123456 1234567 123456 123456 123 123456 1234567 1234 123456 1234567 123 1234567 1234 123456 1234567 123 1234 123 1234 123456 123456 123456 1234567 123456 1234567 1234567 123456 123 1234 123 1234 123456 123456123456 1234567123456 12345671234567 1234561234567 1234567 ○ ○ ○ ○ ○ BANK n, COL a tRP - BANK n READ with burst of 4 ○ ○ ○ 123456 1234567 1234 123456 1234567 1234 1234 123456 1234567 1234 123456 1234567 ○ ○ ○ ○ ○ ○ Interrupt Burst, Precharge ○ ○ ○ Page Active NOP ○ ○ ○ NOP ○ ○ ○ ○ ○ ○ ○ ○ 1234567 123456 123 1234567 123456 123 123 1234567 123456 123 123456 ADDRESS1234567 ○ ○ ○ ○ ○ ○ ○ ○ READ with burst of 4 ○ ○ Page Active BANK m NOP ○ ○ ○ ○ BANK n Internal States READ-AP BANK m ○ READ-AP BANK n NOP ○ COMMAND ○ ○ ○ ○ ○ CLK Figure 24 READ WITH AUTO PRECHARGE INTERRUPTED BY A READ T0 T1 T2 T3 T4 T5 T6 T7 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DIN d+3 ○ DIN d+2 ○ DIN d+1 ○ ○ ○ DIN d ○ ○ ○ ○ ○ tWR-BANKm Write back ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ Idle ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DOUT a ○ ○ CAS Latency = 3 (BANK n) NOP 123456 1234567 123 1234567 123 123 123456 123456 1234567123456 123 123456 12345671234567 123 1234567 123 1234561234567 1234567 123456 1234567 123 123456 1234567 123 1234567 123 123456 123456 1234567123456 123 12345671234567 123 123 1234561234567 1234567 ○ ○ ○ DQ NOP ○ ○ ○ ○ ○ ○ BANK m, COL d ○ ○ ○ ○ ○ BANK n, COL a ○ ○ ○ 1234567 123456 123 1234567 123 123456 123 1234567 123456123456 123 123456 1234567123456 123 123456 123456 123 1234567 123 123456 123456 1234567 123 123456 123456 123 1234567 123 123456123456 1234567123456 123 123 123456 ADDRESS 123456 1234567 123 123456 1234567 123 1234567 123 DQM1 123456 ○ ○ ○ tRP - BANK n WRITE with burst of 4 ○ ○ ○ Page Active ○ ○ NOP Interrupt Burst, Precharge ○ BANK m ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ READ with burst of 4 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ WRITE-AP BANK m NOP ○ Page Active NOP ○ BANK n Internal States NOP ○ ○ READ-AP BANK n ○ COMMAND ○ ○ ○ CLK 1234 1234 1234 1234Don’t Care NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4. Figure 25 READ WITH AUTO PRECHARGE INTERRUPTED BY A WRITE AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 23 SDRAM AS4SD4M16 Austin Semiconductor, Inc. 4 WRITE with AUTO PRECHARGE 3. Interrupted by a WRITE (with or without AUTO PRECHARGE): A WRITE to bank m will interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank 1 (Figure 27). Interrupted by a READ (with or without AUTO PRECHARGE): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 26). T0 T1 T2 T3 T4 T7 T6 T5 ○ ○ ○ ○ ○ ○ ○ ○ ○ NOP ○ ○ ○ NOP ○ ○ NOP ○ ○ WRITE-AP BANK m ○ Precharge ○ ○ ○ ○ ○ ○ tRP-BANK m ○ ○ ○ ○ ○ ○ DOUT d DOUT d+1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ DIN a+1 DIN a ○ ○ ○ ○ ○ DQ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 123456 1234567 1234 1234567 123 1234567 123 123 123456 123456 1234567123456 1234 123456 1234567123456 123 123456 1234567123456 123 123456 123 1234561234567 1234567 123456 1234567 1234 123456 1234567 123 123456 1234567 123 123456 123 123456 123456 1234567 1234 123456 1234567123456 123 1234567123456 123 123 1234561234567 1234567 ○ ○ ○ tRP-BANK n READ with burst of 4 123456 1234567 123 123456 1234567 BANK m, 123 123456 1234567 123 123456 1234567 COL d 123 ○ ○ ○ ○ ○ BANK n, COL a ○ ○ 123456 1234567 1234 123456 1234567 1234 123456 1234567 1234 1234567 1234 ADDRESS 123456 Page Active ○ BANK m ○ ○ ○ ○ tWR - BANK n ○ ○ ○ ○ ○ ○ ○ Interrupt Burst, Write back ○ ○ ○ ○ ○ ○ ○ ○ ○ WRITE with burst of 4 ○ Page Active ○ ○ BANK n Internal States NOP ○ ○ ○ ○ ○ NOP ○ WRITE-AP BANK n ○ ○ ○ ○ ○ NOP ○ COMMAND ○ ○ ○ ○ ○ ○ CLK ○ ○ CAS Latency = 3 (BANK m) NOTE: DQM is LOW. Figure 26 WRITE WITH AUTO PRECHARGE INTERRUPTED BY A READ T0 T1 T2 T3 T4 T6 T5 T7 ○ ○ ○ ○ ○ NOP ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ Precharge ○ Interrupt Burst, Write back ○ ○ tWR-BANK m ○ tRP-BANK n ○ ○ ○ tWR - BANK n ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ NOP ○ ○ ○ DIN d+3 ○ DIN d+2 ○ ○ ○ DIN d+1 ○ ○ DIN d ○ DIN a+2 ○ ○ DIN a+1 ○ ○ DIN a ○ DQ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ WRITE with burst of 4 Write back 1234567 123456123456 123 1234567 1234 1234567 12345671234567 123 123456123456 123 1234567 123 123456 1234567 123456 123 123456 1234567 1234 1234567 1234567 123 1234567 123456 123 123456 1234567 123 123456 1234567 123456 123 123456 1234567 1234 1234567 123 1234567 123456 123 123456 1234567 123 123456 BANK m, 1234567 1234567 123456123456 123 1234567 COL d 1234567 1234 12345671234567 123 123456123456 123 1234567 123 123456 ○ ○ ○ BANK n, COL a ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ Page Active ○ ○ 123456 1234567 123 123456 1234567 123 123456 123 1234567 123 1234567 ADDRESS 123456 NOP ○ ○ WRITE with burst of 4 ○ BANK m WRITE-AP BANK m ○ ○ NOP ○ ○ Page Active ○ NOP ○ ○ BANK n Internal States WRITE-AP BANK n ○ ○ NOP ○ COMMAND ○ ○ ○ ○ ○ CLK 123 123 123 123Don’t Care NOTE: DQM is LOW. Figure 27 WRITE WITH AUTO PRECHARGE INTERRUPTED BY A WRITE AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 24 SDRAM Austin Semiconductor, Inc. AS4SD4M16 TRUTH TABLE 2-CKE1,2,3,4 CKEn-1 CKEn L L L H H L H H NOTE: 1. 2. 3. 4. 5. 6. 7. CURRENT STATE Power-Down Self Refresh Clock Suspend Power-Down Self Refresh Clock Suspend All Banks Idle All Banks Idle Reading or Writing COMMANDn ACTIONn X Maintain Power-Down X Maintain Self Refresh X Maintain Clock Suspend COMMAND INHIBIT or NOP Exit Power-Down COMMAND INHIBIT or NOP Exit Self Refresh X Exit Clock Suspend COMMAND INHIBIT or NOP Power-Down Entry AUTO REFRESH Self Refresh Entry VALID Clock Suspend Entry See Truth Table 3 NOTES 5 6 7 CKE n is the logic state of CKE at clock edge n; CKE n-1 was the state of CKE at the previous clock edge. Current state is the state of the SDRAM immediately prior to clock edge n. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n . All states and sequences not shown are illegal or reserved. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that tCKS is met). Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during tXSR period. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1. AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 25 SDRAM Austin Semiconductor, Inc. AS4SD4M16 TRUTH TABLE 3 - CURRENT STATE BANK n - COMMAND TO BANK n (Notes 1 to 6; notes appear below and on next page) CURRENT STATE CS\ RAS\ CAS\ WE\ COMMAND (ACTION) ANY Idle Row Active Read ( AutoPrecharge Disabled) Write ( AutoPrecharge Disabled) NOTES H L L L L L L L L X H L L L L H H L X H H L L H L L H X H H H L L H L L COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) ACTIVE (Select and activate row) AUTO REFRESH LOAD MODE REGISTER PRECHARGE READ (Select column and start READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Deactivate row in bank or banks) 7 7 11 10 10 8 L L L H H L L L H H L L READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Truncate READ burst, start PRECHARGE) 10 10 8 L L L L L H H H L H H L L H H L H L L L BURST TERMINATE READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE (Truncate WRITE burst, start PRECHARGE) BURST TERMINATE 9 10 10 8 9 NOTE: 1. 2. 3. 4. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth Table 4. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the row active state. Read w/AutoPrecharge Enabled: Starts with registration of a READ command with AUTO PRECHARGE enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/AutoPrecharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 26 SDRAM Austin Semiconductor, Inc. AS4SD4M16 NOTE (continued): 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the SDRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the SDRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.. 10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with AUTO PRECHARGE enabled and READs or WRITEs with AUTO PRECHARGE disabled. 11. Does not affect the state of the bank and acts as a NOP to that bank. AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 27 SDRAM Austin Semiconductor, Inc. AS4SD4M16 TRUTH TABLE 4 - CURRENT STATE BANK n - COMMAND TO BANK m (Notes: 1-6; notes appear below and on next page) CURRENT STATE Any Idle Row Activating, Active or Precharging Read (AutoPrecharge Disabled) Write (AutoPrecharge Disabled) Read (with AutoPrecharge) Write (with AutoPrecharge) CS\ H L X L L L L L L L L L L L L L L L L L L L L RAS\ X H X L H H L L H H L L H H L L H H L L H H L CAS\ X H X H L L H H L L H H L L H H L L H H L L H WE\ X H X H H L L H H L L H H L L H H L L H H L L COMMAND/ACTION COMMAND INHIBIT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) Any command otherwise allowed to bank m ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE NOTES 7 7 7, 10 7, 11 9 7, 1 7, 13 9 7, 8 ,14 7, 8 15 9 7, 8 16 7, 8 17 9 NOTE: 1. 2. 3. 4. 5. 6. 7. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/ accesses and no register accesses are in progress. Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. Read w/AutoPrecharge Enabled: Starts with registration of a READ command with AUTO PRECHARGE enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/AutoPrecharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. All states and sequences not shown are illegal or reserved. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with AUTO PRECHARGE enabled and READs or WRITEs with AUTO PRECHARGE disabled. AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 28 SDRAM Austin Semiconductor, Inc. AS4SD4M16 NOTE (continued): 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been interrupted by bank m’s burst. Burst in bank n continues as initiated. For a READ without AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will interrupt the READ on bank n, CAS latency later (Figure 7). For a READ without AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the WRITE command to prevent bus contention. For a WRITE without AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. For a WRITE without AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. For a READ with AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 24). For a READ with AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25). For a WRITE with AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 26). For a WRITE with AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Figure 27). AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 29 SDRAM AS4SD4M16 Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Voltage on VDD/VDDQ Supply Relative to VSS ........................................ -1V to +4.6V Voltage on Inputs, NC or I/O Pins Relative to VSS ........................................ -1V to +4.6V Operating Temperature, TA (ambient)........-55°C to +125°C Storage Temperature (plastic) ................-55°C to +150°C Power Dissipation ................................................. 1W *Stresses greater than those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 6) (-55° ≤ ΤΑ ≤ +125 °C ; VDD/VDDQ =+3.3 V +0.3V) PARAMETER/CONDITION Supply Voltage Input High (Logic 1) Voltage, all inputs Input Low (Logic 0) Voltage, all inputs SYMBOL VDD/VDDQ VIH VIL MIN 3 2.2 -0.5 MAX 3.6 VDD +0.3 0.7 UNITS V V V II -5 5 µΑ IOZ -5 5 µΑ VOH 2.4 -- V VOL -- 0.4 V INPUT LEAKAGE CURRENT Any input 0V<VIN<VDD (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V<VOUT<VDDQ) OUTPUT LEVELS Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) NOTES 23 23 IDD SPECIFICATIONS AND CONDITIONS1, 6, 11, 13 (-55°C<TA <+125 °C; VDD/VDDQ =+3.3 V +0.3V) +3 , 012 ! 3&45/%0&4( &65 )) 78(9 :6)5 "+; ( ( .&/ % 012 -, , 0 &/ ; ( ( .&/ % ", -, ( ( .&/ % ! 1@/ &65 &(:(@&@ 7@/ )) 78(9 8<:=5 )85(<* + µ ! "#$ % & ' &()* AS4SD4M16 Rev. 1.5 10/01 <:=5 &65 ", ( ( .&/ % )) 78(9 8<:=5 8.5/ 5 & 8<<55 :( >/&?/5 +3 <:=5 &65 1@/ )85(<* ( ( .&/ % 0 &/ ; Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 30 SDRAM AS4SD4M16 Austin Semiconductor, Inc. CAPACITANCE PARAMETER SYMBOL CI1 MAX 4.0 UNITS pF NOTES 2 Input Capacitance: All other input-only pins CI2 5.0 pF 2 Input/Output Capacitance: DQs CIO 6.5 pF 2 Input Capacitance: CLK ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 5, 6, 8, 9, 11) (-55oC<TA<+125oC) PARAMETER Access time from CLK (pos. edge) SYM -8 MIN -10 MAX MIN MAX UNITS NOTES CL = 3 tAC 6.5 7 ns CL = 2 tAC 9 9 ns 22 Address hold time tAH 1 1 ns Address setup time tAS 2 3 ns CLK high-level width tCH 3 3.5 ns CLK low-level width tCL 3 3.5 ns CL = 3 tCK 8 10 ns 24 CL = 2 tCK 12 15 ns 22, 24 CKE hold time tCKH 1 1 ns CKE setup time tCKS 2 3 ns CS#, RAS#, CAS#, WE#, DQM hold time tCMH 1 1 ns CS#, RAS#, CAS#, WE#, DQM setup time tCMS 2 3 ns Data-in hold time tDH 1 1 ns Data-in setup time tDS 2 3 ns Clock cycle time Data-out high-impedance time CL = 3 tHZ 6 8 ns 10 CL = 2 tHZ 7 10 ns 10 Data-out low-impedance time tLZ 1 1 ns Data-out hold time tOH 2.5 2.5 ns ACTIVE to PRECHARGE command tRAS 50 AUTO REFRESH, ACTIVE command period tRC 80 90 ns 22 ACTIVE to READ or WRITE delay Refresh period (4,096 rows) -40 to +85 degrees C tRCD 20 30 ns 22 tREF 64 64 ms Refresh period (4,096 rows) -55 to +125 degrees C tREF 16 16 ms PRECHARGE command period tRP 24 30 ns tRRD 20 20 ns tT 0.3 1 CLK + 8ns 15 ACTIVE bank A to ACTIVE bank B command Transition time WRITE recovery time Exit SELF REFRESH to ACTIVE command AS4SD4M16 Rev. 1.5 10/01 A2 version tWR tXSR 80 80,000 1.2 60 1 1 CLK + 8ns 15 90 80,000 1.2 - ns 22 ns 7 25 ns 26 ns 20 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 31 SDRAM AS4SD4M16 Austin Semiconductor, Inc. AC FUNCTIONAL CHARACTERISTICS5, 6, 7, 8, 9, 11 (-55oC<TA<+125oC) PARAMETER SYMBOL -8 -10 READ/WRITE command to READ/WRITE command tCCD 1 1 UNITS NOTES tCK 17 CKE to clock disable or power-down entry mode tCKED 1 1 tCK 14 CKE to clock enable or power-down exit setup mode tPED 1 1 tCK 14 DQM to input data delay tDQD 0 0 tCK 17 DQM to data mask during WRITEs tDQM 0 0 tCK 17 DQM to data high-impedance during READs tDQZ 2 2 tCK 17 WRITE command to input data delay tDWD 0 0 tCK 17 Data-in to ACTIVE command A2 version tDAL 5 4 tCK 15, 21 Data-in to PRECHARGE command A1 version A2 version tDPL 2 2 tCK 16, 21 Last data-in to burst STOP command tBDL 1 1 tCK 17 Last data-in to new READ/WRITE command tCDL 1 tCK 17 16, 21 Last data-in to PRECHARGE command 2 2 tCK tMRD 2 2 tCK 27 CL = 3 tROH 3 3 tCK 17 CL = 2 tROH 2 2 tCK 17 LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command 1 tRDL A2 version ELECTRICAL TIMING CHARACTERISTICS for -8 SPEED5, 6, 7, 8, 9, 11, 24 (-55oC<TA<+125oC) -8 SYM MIN MAX UNITS NOTES CL = 3 tAC --- 6 ns 22 CL = 2 tAC --- 9 ns 22 CL = 3 tCK 8 --- ns 22 CL = 2 tCK 12 --- ns 22 tRCD 20 --- ns 22 tRP 24 --- ns 22 AUTO REFRESH, ACTIVE command period tRCD 80 --- tCK 21 WRITE recovery time tWR 2 --- --- --- CLKs --- PARAMETER Access times from CLK (pos. edge) Clock cycle time ACTIVE to READ or WRITE delay PRECHARGE command period A2 Version 3-2-3 100 MHz Speed Reference (CL -tRCD-tRP) AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 32 SDRAM Austin Semiconductor, Inc. AS4SD4M16 NOTES 12. Other input signals are allowed to transition no more than once in any 30ns period (20ns on -8) and are otherwise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The ICC current will decrease as the CAS latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS latency is reduced. 19. Address transitions average one transition every 30ns (20ns on -8). 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 100 MHz for -8 and 66 MHz for -10. 22. These five parameters vary between speed grades and define the differences between the -8 SDRAM speeds: -8. 23. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of the cycle rate. 24. The clock frequency must remain constant during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 25. Auto precharge mode only. The precharge timing budget ( tRP) begins 8ns after the first clock delay, after the last WRITE is executed. 26. Precharge mode only. 27. JEDEC and PC100 specify three clocks. 1. 2. All voltages referenced to VSS. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25°C; pin under test biased at 1.4V. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-55°C ≤ TA ≤ +125°C) is ensured. 6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured at 1.5V with equivalent load: 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and ICC tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. Q 50pF AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 33 SDRAM AS4SD4M16 Austin Semiconductor, Inc. INITIALIZE AND LOAD MODE REGISTER2 T0 t CK CLK T1 To+1 tCL 123 12 1234 123 12 12 123 123 12 121234 123 1234 123 12 121234 123 123 12 12 1234 12 12 1234 12 12 1234 12 1234 12 12 12 1234 12 1234123 123 12 1234 1234123 12 123 123 12 123412 123 12 123 121234 123412 12 123 12123412 t CMH t CMS t CMH t CMS t CMH tCMS 123 12345 1 12345 123 1 12345 123 1 COMMAND 12345 123 1 DQM / DQML, DQMH NOP Tp+1 Tp+2 Tp+3 tCH tCKS tCKH 12345 123 1 12345 123 1 12345 123 1 123 1 CKE 12345 Tn+1 123 123 123 123 AUTO 123 123PRECHARGE123 123 REFRESH 123NOP 123 123 123 12 1234123 12 121234 1234123 123 121234123 123 123412 123 1231234 123412 12 123123412 123 123 123 AUTO 123 123 REFRESH 123 NOP 123 123 NOP 12 1234123 12 121234 1234123 123 121234123 123 123 123 123 LOAD MODE 123 123 123 REGISTER 123 123 12 1234 123 12 12 123 123 12 121234 123 1234 123 12 121234 123 123 12 123 123 123 123 NOP NOP 12 1234 12 123412 12 121234 12 12123412 ACTIVE 123 123 123 123 123456789012345678901234567890121234567890123456789012345678901212345678901234567890 123456789012345678901234567890121234567890123456789012345678901212345678901234567890 123456789012345678901234567890121234567890123456789012345678901212345678901234567890 123456789012345678901234567890121234567890123456789012345678901212345678901234567890 tAS tAH 12345678901234567890123456789012123456789012345678901 12345 12 12345 11234 12345 11 12345678901234567890123456789012123456789012345678901 12345 12 12345 11234 12345 12345678901234567890123456789012123456789012345678901 1234 12345 12 12345 1 12345 11 CODE A0-A9, A11 12345678901234567890123456789012123456789012345678901 12345 12 12345 11234 12345 tAS tAH 12345678901 12345 12 123456789012345678901234567890121 12 12345 12 12345 11234 12345 11 12345678901 12345 12 ALL BANKS12345 12345 123456789012345678901234567890121 12 12345 12 12345 11234 12345 12345678901 12345 12 12345 123456789012345678901234567890121 12 12345 12 12345 1234 1 12345 11 CODE 12345 12345 12 12345 123456789012345678901234567890121 12 12345 12 11234 12345 A10 12345678901 12345678901 12345 12 12345 123456789012345678901234567890121 12 12345 12 12345 11234 12345 1 SINGLE BANK 12345678901 1234 12 12345678901 1234 12 12345678901 1234 12 1234 12 BA0, BA1 12345678901 12345678901 1234 ALL BANKS 12345 123456789012345678901234567890121234567890123456 12 12345 11 12345 123456789012345678901234567890121234567890123456 12 12345 123456789012345678901234567890121234567890123456 12345 12 12345 11 12345 123456789012345678901234567890121234567890123456 12 12345 123456789012345678901234567890121234567890123456 12345 12345 ROW ROW BANK 12345 1234 12 12345 1234 12 1234 12345 12 1234 12345 12 12345 1234 12 12345 1234 12 12345 1234 12 12345 1234 12 12345 1234 12 12345 1234 12 12345 1234 12 1234 12345 12 12345 1234 12 1234 12345 High-Z DQ tRC tRC AUTO REFRESH AUTO REFRESH tRP T=100s Power-up: VDD and CLK stable Precharge all banks tMRD Program Mode Register 1,3,4 1234 1234 1234Don’t Care 1234 1234 1234Undefined 1234 TIMING PARAMETERS -8 SYMBOL* MIN -8 -10 MAX MIN MAX SYMBOL* UNITS MIN -10 MAX MIN MAX UNITS tAH 1 1 ns tCKS 2 3 ns tAS 2 3 ns tCMH 1 1 ns tCH 3 3.5 ns tCMS 2 3 ns tCL 3 3.5 ns tMRD (3) 2 2 tCK tCK (3) 8 10 ns tRC 80 90 ns tCK (2) 12 15 ns tRP 24 30 ns tCKH 1 1 ns * CAS latency indicated in parentheses. NOTE: 1. 2. 3. 4. AS4SD4M16 Rev. 1.5 10/01 The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired. If CS is HIGH at clock high time, all commands applied are NOP, with CKE a “Don’t Care”. JEDEC and PC100 specify three clocks. Outputs are guaranteed High-Z after command is issued. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 34 SDRAM AS4SD4M16 Austin Semiconductor, Inc. POWER-DOWN MODE1 T0 T1 1234567890123 1234567890123 1234567890123 1234567890123 1234567890123 1234567890123 T2 tCK t CL CLK t CH 123 123 12 123 123 12 123 12 CKE123 123 123 12 tCKS tCMS Tn +1 t t 123 1234 12 123 1234 12 1234 123 12 1234 123 12 CK 12345 12345 12345 12345 Tn +2 12 1234 12 123412 12 121234 12 12123412 CK 123 1234 123 123412 12 1231234 12 123123412 tCKH tCMH 12345 123 123 123456 123456789012345678901234567 12 12345 12 123 123 12345 123 123 123456 123456789012345678901234567 12 12345 12 123 123 12345 123 123 123456 123456789012345678901234567 12 12345 12 123 123 NOP ACTIVE 123 COMMAND 123456789012345678901234567 12345PRECHARGE123 NOP 123 NOP 123456 12 12345 12 123 123456789012345678901234567 12345 123 123 123456 12 12345 12 123 123 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901 DQM / 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901 DQML, 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901 DQMH 1234567890123456789012345678901212345678901234567890123456789012123456 12345 12 1234567890123456789012345678901212345678901234567890123456789012123456 12345 12 1234567890123456789012345678901212345678901234567890123456789012123456 12345 12 A0-A9, A11 1234567890123456789012345678901212345678901234567890123456789012123456 12345 12 12345 12345 123456 1234567890123456789012345678901212345678901234567890123456 12 123456 12 123456 1234567890123456789012345678901212345678901234567890123456 12 123456 12 1234567890123456789012345678901212345678901234567890123456 123456 12 123456 12 123456 1234567890123456789012345678901212345678901234567890123456 12 123456 12 ROW ALL BANKS 12345 A10 12345 ROW 123456 1123 123456 1123 123456 123 11 123456 123 123456 1123 123456 1123 123 123456 11 123456 123 SINGLE BANK t t AS AH 123456 12345 1234567890123456789012345678901212345678901234567890123456 12 123456 12 12345 123456 1234567890123456789012345678901212345678901234567890123456 12 123456 12 1234567890123456789012345678901212345678901234567890123456 12345 123456 12 123456 12 BANK(S) BA0, BA1 12345 123456 1234567890123456789012345678901212345678901234567890123456 12 123456 12 DQ BANK 123456 1123 123456 1123 123 123456 11 123456 123 High-Z Two clock cycles Precharge all active banks Input bufferd gated off while in power-down mode All banks idle, enter power-down mode All banks idle Exit power-down mode 123 123 Don’t Care 123 1234 1234 1234 1234Undefined TIMING PARAMETERS -8 SYMBOL* MIN -8 -10 MAX MIN MAX SYMBOL* UNITS MIN -10 MAX MIN MAX UNITS tAH 1 1 ns tCK (2) 12 15 ns tAS 2 3 ns tCKH 1 1 ns tCH 3 3.5 ns tCKS 2 3 ns ns tCMH 1 1 ns ns tCMS 2 3 ns tCL 3 tCK (3) 8 3.5 10 * CAS latency indicated in parentheses. NOTE: 1. Violating refresh requirements during power-down may result in a loss of data. AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 35 SDRAM AS4SD4M16 Austin Semiconductor, Inc. CLOCK SUSPEND MODE1 T0 t CK T1 T2 CLK 12 1234 12 12 1234 12 tCH tCKS tCKH 12 1234 12 12 1234 12 12345 12345 12345 12345 12 1234 12 12 1234 12 CKE 12 1234 12 12 1234 12 tCKS t CKH tCMS tCMH 12345 12345 12345 READ 12345 COMMAND 123 123 123 123 T3 T4 T5 T6 T7 NOP 123 123 123 123 123456 123456 123456 123456 NOP 123 12 1234 123 12 12 123 123 12 121234 123 1234 123 12 121234 123 123 12 12345 12 12345 123456 12 12345 12 12345 123456 12 12345 12 123456 12 12345 12345 12 12345 123456 12 123 123412 123 1231234 123412 12 123123412 NOP 123 123 123 123 12 1234123 12 121234 1234123 123 121234123 NOP 123 123 123 123 12345 12345 12345 12345 NOP 123456 123456 123456 123456 T9 123 12 1234 123 12 12 123 123 12 121234 123 1234 123 12 121234 123 123 12 123 123456 11234567 12345 11 123 11234567 123 WRITE 123456 123456 1 12345 12345 1 1234567 123 123456 1234567 1 12345 1 tCMS tCMH 12345 12 123 12 1234567890123456789012345678901212345 DQM / 1234567890 1234567890 12345 12 12 121234 1234 123 123 123 12 1234567890123456789012345678901212345123 123 12345 12 12 1234 123 123 12 1234567890123456789012345678901212345 DQML,1234567890 1234567890 12345 12 121234 123 123 12 1234567890123456789012345678901212345123 123 DQMH tAS t 12345 AH 12345 123456789012345678901234567890121234567890123456 1 12345 12 12345 T8 tCL 12 1234 12 12 1234 12 123412 12 12 123412 NOP 12 121234567890123 123456789012312 12 12 1234567890123 12123456789012312 12 12345 12345 12345 12345 12 1234 12 123412 12 12 1234 12 123412 12 12345 1123456789012345678 12345 112345678901234567811 12345 123456789012345678901234567890121234567890123456 1 12345 12 123456789012345678901234567890121234567890123456 123456789012345678 12345 1 12345 12 11 11 A0-A9, 12345COLUMN m2 12345 12345 123456789012345678901234567890121234567890123456 1 12345 12 COLUMN e212345 12345 123456789012345678 A11 123456789012345678901234567890121234567890123456 123456789012345678 12345 12345 1 12345 12 12345 1 1 tAS t AH 12 12 12 1234567890123456789012345678901212345678901234567890 123 12 123456789012345678901 12 12 12 1234567890123456789012345678901212345678901234567890 12123456789012345678901 123456789012345678901 1234567890123456789012345678901212345678901234567890123 12 12 12 123 12 12 121234567890123456789012345678901212345678901234567890123 12123456789012345678901 A10 12 12 1234567890123456789012345678901212345678901234567890123 12123456789012345678901 tAS t AH 12345 12345 123456789012345678901234567890121234567890123456 1 12345 12 12345 1123456789012345678 12345 12345 123456789012345678901234567890121234567890123456 1 12345 12 12345 112345678901234567811 BA0, 12345 12345 123456789012345678901234567890121234567890123456 1 12345 12 12345 123456789012345678 11 11 BANK BANK 12345 12345 123456789012345678901234567890121234567890123456 1 12345 12 12345 123456789012345678 BA1 tAC 1234567 1234567 12345 12 1 1234567 1234567 12345 12 1 12345 1234567 1234567 12 1 12345 1234567 1234567 12 1 12345 1234567 1234567 12 1 DQ DOUT m tAC tHZ tOH 1234567 1234567 12 1234 12 1234567 1234567 12 1234 12 1234 1234567 1234567 12 12 1234 1234567 1234567 12 12 DOUTm+1 1234 1234567 1234567 12 12 t t DS DH 12345 12345 11234 12 123456 1234567 12 12345 11 12345 12345 12345 11234 12 123456 1234567 12 12345 12345 12345 12345 1 1234 12 1234567 12 12345 1 DOUT a 123456 DOUT a-1 12345 1234 1234567 12345 112345 12 123456 12 12345 1 12345 tLZ 1234 1234 1234 Don’t Care 1234 1234 1234 Undefined 1234 TIMING PARAMETERS -8 SYMBOL* MIN -10 MAX MIN -8 MAX UNITS SYMBOL* MIN -10 MAX MIN MAX UNITS tAC(3) 6.5 7 ns tCKS 2 3 ns tAC(2) 9 9 ns tCMH 1 1 ns tAH 1 1 ns tCMS 2 3 ns tAS 2 3 ns tDH 1 1 ns tCH 3 3.5 ns tDS 2 3 ns tCL 3 3.5 ns tHZ(3) 6 8 ns tCK(3) 8 10 ns tHZ(2) 7 10 ns tCK(2) 12 15 ns tLZ 1 1 ns tCKH 1 1 ns tOH 2.5 2.5 ns * CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and AUTO PRECHARGE is disabled. 2. x16: A8, A9 and A11 = “Don’t Care.” AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 36 SDRAM AS4SD4M16 Austin Semiconductor, Inc. AUTO REFRESH MODE1 T0 T1 T2 Tn +1 tCK CLK t 123 12 123 12 123 12 1234 123 12 12 123 123 12 121234 123 1234 123 12 121234 123 123 12 12 CKE123 123 12 tCKS tCMS To +1 t CL 12 1234 123 12 1234 123 12 1234 123 1234 12 123 CH 123 123412 123 1231234 123412 12 123123412 12 1234 12 1234123 123 121234 123 121234123 12 123412 123 12 123 12 121234 1234 123 12 12123412 123 123 123412 123 1231234 123412 12 123123412 123 12 1234 12 12 123 1234123 123 12 121234 123 123 12 121234123 123 12 tCKH tCMH 12345 123 123 123 123 12 12 123 123 12345 123 123 123 123 12 12 123 123 12345 123 123 123 123 12 12 123 123 AUTO AUTO NOP NOP NOP 123 NOP COMMAND PRECHARGE NOP 123 ACTIVE 123 12345 123 123 123 12 12 12345 123 123 REFRESH 123 123 REFRESH 12 123 123 123456789012345678901234567890121234567890123456789012345678901212345678901234567 DQM /123456789012345678901234567890121234567890123456789012345678901212345678901234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567 DQML,123456789012345678901234567890121234567890123456789012345678901212345678901234567 DQMH 1234567890123456789012345678901212345678901234567890123456789012 12345 12 1234567890123456789012345678901212345678901234567890123456789012 12345 12 A0-A9,1234567890123456789012345678901212345678901234567890123456789012 12345 12 12345 12 A111234567890123456789012345678901212345678901234567890123456789012 12345 12345 123456 1234567890123456789012345678901212345678901234567890 12 123456 12 123456 1234567890123456789012345678901212345678901234567890 12 123456 12 1234567890123456789012345678901212345678901234567890 123456 12 123456 12 123456 12 1234567890123456789012345678901212345678901234567890 123456 12 123456 12 1234 123456 121234 1234 123456 12 123456 121234 ROW 123456 11234 123456 11234 1234 123456 11 123456 1234 ALL BANKS 12345 A10 12345 ROW SINGLE BANK t t AS AH 12345 12345 12345 BA0, BA1 12345 BANK(S) DQ 123456 1234567890123456789012345678901212345678901234567890 12 123456 12 123456 1234567890123456789012345678901212345678901234567890 12 123456 12 1234567890123456789012345678901212345678901234567890 123456 12 123456 12 123456 12 1234567890123456789012345678901212345678901234567890 123456 12 123456 112345 123456 112345 12345 123456 11 123456 12345 BANK High-Z t RP t RC t RC 123 123 123Don’t Care 12345 12345 12345 12345Undefined TIMING PARAMETERS -8 SYMBOL* MIN -8 -10 MAX MIN MAX SYMBOL* UNITS MIN -10 MAX MIN MAX UNITS tAH 1 1 ns tCKH tAS 2 3 ns tCKS 2 3 ns tCH 3 3.5 ns tCMH 1 1 ns tCL 3 3.5 ns tCMS 2 3 ns tCK (3) 8 10 ns tRC 80 90 ns tCK (2) 12 15 ns tRP 24 30 ns 1 1 ns * CAS latency indicated in parentheses. NOTE: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required. AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 37 SDRAM AS4SD4M16 Austin Semiconductor, Inc. SELF REFRESH MODE1 T tCK T T t CL CLK t 123 12 123 12 123 12 CKE123 12 123 12 CH 1234567890123 1234567890123 1234567890123 1234567890123 1234567890123 1234567890123 1234567890123 t 12 1234 123 12 1234 123 12 1234 123 12 1234 123 1234 12 123 t CKS 123456 123456 123456 123456 123456 tCKS tCKH tCMS tCMH T T T 12 123412 12 121234 123412 12 12 123412 121234 12 RAS 12 1234123 12 121234 1234123 123 12 1234123 121234 123 t CKS 12345 123 123 12345 1123456789012345 123456 12 123 123 12345 123 123 1123456789012345 123456 12 123 123 AUTO 12345 12345 123456789012345 1 123456 12 123 AUTO 123 123 NOP 123456789012345 12345 123 NOP 123 REFRESH 12345 1 123456 12 123 REFRESH 123 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012 DQM / 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012 DQML, 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012 DQMH 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012 A0-A9, A1112345678901234567890123456789012123456789012345678901234567890121234567890123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012 12345 12345678901234567890123456789012123456789012345678901234567890121234567890 1 12345 ALL BANKS12345 12345 12345678901234567890123456789012123456789012345678901234567890121234567890 1 12345 12345 12345678901234567890123456789012123456789012345678901234567890121234567890 1 A10 12345 12345 1 12345678901234567890123456789012123456789012345678901234567890121234567890 12345PRECHARGE123 COMMAND SINGLE BANK tAS tAH 12345 12345 12345 12345 BANK(S) BA0, BA1 12345 12345 12345678901234567890123456789012123456789012345678901234567890121234567890 1 12345 12345678901234567890123456789012123456789012345678901234567890121234567890 1 12345 12345678901234567890123456789012123456789012345678901234567890121234567890 1 12345 1 12345678901234567890123456789012123456789012345678901234567890121234567890 12345 12345678901234567890123456789012123456789012345678901234567890121234567890 1 High-Z DQ tRP Precharge all active banks tXSR Exit self refresh mode (Restart refresh time base) Enter self refresh mode 1234 1234 1234 Don’t Care 1234 1234 1234 1234 Undefined CLK stable prior to exiting self refresh mode TIMING PARAMETERS -8 SYMBOL* MIN -10 MAX MIN -8 MAX UNITS SYMBOL* MIN -10 MAX MIN MAX UNITS tAH 1 1 ns tCKS 2 3 ns tAS 2 3 ns tCMH 1 1 ns tCH 3 4 ns tCMS 2 3 ns tCL 3 4 ns tRAS 50 tCK(3) 8 10 ns tRP 24 30 ns tCK(2) 12 15 ns tXSR 80 90 ns tCKH 1 1 ns 80,000 60 80,000 ns * CAS latency indicated in parentheseses. NOTE: 1. Self Refresh Mode available on Industrial Temperature Range option only. AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 38 SDRAM AS4SD4M16 Austin Semiconductor, Inc. READ -- WITHOUT AUTO PRECHARGE1 T0 T1 CLK t t CKS t T2 T3 t CK 123456 1234 123 12 1234 123 12 123412 123 123456 123 123 1234 123 12 123 123 1234 123 12 12 12 123 12 121234 1234 123 123412 12 123 123456 123 1234 123 123 1234 123 12123412 12 123456 123 1234 123 12 123 1234 123 12 CKE 1234 1234 123456 123 123 12 123 123 12 t CMS t CMH 123 123 123 123 123 NOP 12 12 12 12 12 READ t CMS 12345 1234567890123456789 12345 1234567890123456789 12345 1234567890123456789 DQM / 12345 1234567890123456789 1234567890123456789 DQML, DQMH 12345 t t 1234 1234 A0-A9,1234 1234 A111234 AS ROW t AS 1234 1234 A101234 1234 1234t AH T6 T7 T8 12 12 12 12 12 123 12 12345 123 12 12 123 123 12 1212345 123 12345 123 12 12345 12 123 123 12 123 12345 123 NOP 123 12 123 121234 123 1234 1234123 12 123 121234123 123 123 121234123 123 t CMH 12 12 12 12 12 123 12 12345 123 12 12 123 123 12 1212345 123 12345 123 12 12345 12 123 123 12 123 12345 123 NOP 123 12 123 12 121234 123 1234 123 12 1234 12 123 123 12 121234 123 123 12 121234 123 123 12 123 123 123 123 123 123 12 123 12 121234 123 1234 123 12 1234 12 123 123 12 121234 123 123 12 121234 123 123 12 123 1234 123 12 123 123 12 1231234 1234 123 12 1234 123 123 12 1231234 123 NOP 12 123412 123 12 123 12 121234 1234 123 123412 12 123 12123412 12 123 12 123 123PRECHARGE 12 12 123 12 123 12 12 123412 123 12 123 12 121234 1234 123 123412 12 123 12123412 12 NOP 123 12 12345 123 12 12 123 123 12 1212345 123 12345 123 12 12345 12 123 123 12 123 12345 123 12 1234567 12 12 ACTIVE 1234567 1234567 12 1234567 12 1234567 1234 123 1 123123456789012345678901234567890 1234 123456789012345678901234567890 12345678901234567890123456789011 123 1234 1231234567890123456789012345678901 1234 1231234567890123456789012345678901 1234 123456 12345678 1234567 1234567 12345678901234567890123456789012 123456 123456 12345678 1234567 1234567 12345678901234567890123456789012 123456 12345678 12345678901234567890123456789012 123456 1234567 1234567 123456 123456 12345678 1234567 12345678901234567890123456789012 123456 COLUMN m 1234567 12345678 12345678901234567890123456789012 123456 1234567 1234567 123456 2 ROW 123456 12345 123456 12345 12345 123456 123456 12345 12345 123456 t AH ROW AS T5 CH t CKH 1234 1234 1234 ACTIVE 1234 COMMAND 1234 T4 CL t AH 1234567 12345678 1 1234 123 1234567 12345678 1 1234 123 1234567 12345678 1 1234 123 1234567 12345678 1 1234 123 1234567 12345678 123 12345 12345678901234567890 1234567890123456789 1234567 12345 12345678901234567890 1234567890123456789 1234567 12345 12345678901234567890 1234567890123456789 1234567 12345 12345678901234567890 1234567890123456789 1234567 12345 1234567890123456789 1234567 DISABLE AUTO PRECHARGE 1234 1234 123456 1234567 123456 123456 1234567 123456 1234 123456 1234567 123456 1234567 1234 123456 BA0, BA1 1234 BANK 123456 123456 1234567 123456 BANK tAC t OH 12345678 12345678 12345678 12345678 D m 12345678 12345678 OUT 12345678 t AC BANK 1234567 123456 12345 1234567 123456 12345 12345 1234567 123456 1234567 12345 123456 1234567 12345 123456 tAC tAC t OH t OH 1234 123 1234 123 1234 123 1234 123 1234 1234DOUT m+1 123 123 DOUT m+2 1234 123 t LZ t RCD ROW SINGLE BANK 1234567 12345678901234567 1234567 1234567 12345678901234567 1234567 12345678901234567 1234567 1234567 1234567 12345678901234567 1234567 1234567 12345678901234567 1234567 DQ 1234567 123456 12345 1234567 123456 12345 1234567 12345 123456 1234567 12345 123456 1234567 12345 123456 ALL BANKS BANK 123456 12345 123456 12345 123456 12345 123456 12345 123456 12345 123456 12345 123456 12345 12345 123456 123456 12345 123456 12345 t OH 123 123 12 12 123 123 12 12 123 D m+3 123 OUT 12 12 123 tHZ t RP CAS Latency t RAS 1234 1234 1234 12345Don’t Care t RC 12345 12345 Undefined 12345 12345 TIMING PARAMETERS -8 SYMBOL* MIN -10 MAX MIN -8 MAX UNITS SYMBOL* MIN -10 MAX MIN MAX UNITS tAC(3) 6.5 7 ns tCMH 1 1 ns tAC(2) 9 9 ns tCMS 2 3 ns 6 8 ns 7 10 ns tAH 1 1 ns tHZ(3) tAS 2 3 ns tHZ(2) tCH 3 3.5 ns tLZ 1 1 tCL 3 3.5 ns tOH 2.5 2.5 tCK(3) 8 10 ns tRAS 50 80,000 60 ns ns 80,000 ns tCK(2) 12 15 ns tRC 80 90 ns tCKH 1 1 ns tRCD 20 30 ns tCKS 2 3 ns tRP 24 30 ns * CAS latency indicated in parentheseses. NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE. 2. x16: A8, A9 and A11 = “Don’t Care.” AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 39 SDRAM AS4SD4M16 Austin Semiconductor, Inc. READ -- WITH AUTO PRECHARGE1 T0 T1 CLK t t CKS 123456 123456 123456 123456 CKE 123456 12 1234 123 12 12 1234 123 12 12 123 12 1234 1234 12 123 12 12 1234 123 12 t CMS t CMH 123 123 123ACTIVE 123 COMMAND 123 12 12 12 12 12 t 123 12 12345 123 12 12 123 12345 123 12 12 123 123 12 12345 12345 12 123 123 12 12 123 12345 123 12 NOP T4 T5 T6 T7 T8 CL CK t CKH T3 T2 t 12 12 12 12 12 CH 123 1234 123 12 123 123 12 1231234 123 12 1234 1234 123 123 12 1231234 123 12 123 123 123 123 123 READ 12 1234123 12 123 121234 1234 1234123 12 121234123 123 NOP 12 12 12 12 12 12 1234123 12 12 123 12 121234 123 12 1234 1234123 12 12 121234123 12 123 123 123 123 123 NOP 123 12 1234 123 12 12 123 123 12 121234 123 123 12 1234 1234 12 123 123 12 121234 123 123 12 NOP 123 123 123 123 123 12 123412 123 12 123 12 121234 123 1234 123412 12 123 12123412 123 12 12 12 12 12 12 NOP 123 12 1234123 12 12 123 123 12 121234 123 123 12 1234 1234123 12 123 12 121234123 123 12 NOP 123 12 1234 123 12 12 123 1234 123 12 121234 123 123 12 1234 12 123 123 12 121234 123 123 12 123 123456 123 123ACTIVE 123456 123456 123 123456 123 123456 t CMS t CMH 12345678 123456 1234567890123456789 123 12 12 12 123 12 12345678 123456 1234567890123456789 123 121234 123412 12 123 123 121234 1234123 123 123 1212345 123 12345 123 12 123 123123456789012345678901234567890 12345678901234567890123456789011 12345678 12345678 DQM / 123456 1234567890123456789 123 12 1234 12 123 12 1234 123 12 123 12345 123 12 123 12345678 123456 1234567890123456789 123 12123412 123 121234123 123 1212345 123 12 123123456789012345678901234567890 12345678901234567890123456789011 12345678 12345678 DQML, DQMH 123456 1234567890123456789 123 12123412 123 121234123 123 1212345 123 12 1231234567890123456789012345678901 t AS t AH 123 123456 123456 123456 123456 1234567 123 123456 123456 123456 123456 1234567 12345678 12345678901234567890123456789012 12345 123 123456 12345678 123456 123456 12345678901234567890123456789012 123456 12345 A0-A9, 123 ROW 123456 12345678 123456 COLUMN m 123456 12345678901234567890123456789012 123456 ROW 1234567 1234567 12345 123456 12345678 123456 123456 12345678901234567890123456789012 123456 1234567 12345 A11123 2 123 123 123 123 A10 123 t AS t AH 123456 12345678 12 123456 1 123456 12345678901234567890123456789012123456 12 123456 12 ENABLE 123456 12345678 12 123456 1 AUTO PRECHARGE 123456 12345678901234567890123456789012123456 12 123456 12 123456 12345678 12 123456 1 123456 12 12345678901234567890123456789012123456 123456 12 123456 12345678 12 123456 1 123456 12 12345678901234567890123456789012123456 123456 12 123456 12345678 12 123456 1 123456 12 12345678901234567890123456789012123456 123456 12 ROW t AS t AH 123 123 123456 12345678 123456 123456 12345678 123456 1234567 1234567890123456789012345678901212 123456 1234567 1234567890123456789012345678901212 123456 123 123456123456 1234567 1234567890123456789012345678901212 123456 12345678 1234567890123456789012345678901212 123456 123456 BA0, BA1123 123 BANK 123456 123456 12345678 123456 BANK 1234567 1234567 1234567890123456789012345678901212 123456 AC t AC t OH 12345678 12345678 12345678 12345678 D m 12345678 12345678 OUT DQ t LZ t RCD tAC AC ROW BANK 123456 12345 123456 12345 123456 12345 123456 12345 123456 12345 1234567 12345 1234567 12345 12345 1234567 1234567 12345 1234567 12345 t OH t OH 1234 123 1234 12 1234 123 1234 12 1234 1234D m+1 123 123 D m+21234 1234D m+3 12 12 12 1234 123 1234 OUT OUT OUT 1234 123 1234 12 tHZ t OH t RP CAS Latency t RAS t RC 123 123 123 Don’t Care 123 12345 12345 12345 12345Undefined TIMING PARAMETERS -8 -8 SYMBOL* MIN tAC(3) tAS tCH tCL MIN 9 1 2 MAX UNITS 7 ns 9 ns 1 3 3 3.5 3 3.5 8 10 ns 12 15 ns tCKS SYMBOL* ns ns ns ns tCK(3) tCK(2) tCKH -10 -8 -10 -10 MAX 6.5 tAC(2) tAH 1 1 ns 2 3 ns MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN tAC(3) 6.5 7 ns tCMH 1 1 tAC(2) 9 9 ns tCMS 2 3 MAX UNITS ns ns tAH 1 1 ns tHZ(3) 6 8 ns tAS 2 3 ns tHZ(2) 7 10 ns tCH 3 3.5 ns tLZ 1 1 ns tCL 3 3.5 ns tOH 2.5 2.5 ns tCK(3) 8 10 ns tRAS 50 tCK(2) 12 15 ns tRC 80 90 ns tCKH 1 1 ns tRCD 20 30 ns tCKS 2 3 ns tRP 24 30 ns 80,000 60 80,000 ns * CAS latency indicated in parentheseses. NOTE: 1. For this example, the burst length = 4, the CAS latency = 2. 2. x16: A8, A9 and A11 = “Don’t Care.” AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 40 SDRAM AS4SD4M16 Austin Semiconductor, Inc. ALTERNATING BANK READ ACCESSES1 T0 T1 T2 t CLK t 123456 123456 123456 123456 CKE 123456 12 1234 123 12 12 1234 123 12 12 1234 123 12 1234 12 123 12 12 1234 123 12 12 1234 123 12 12 1234 123 12 12 1234 123 12 1234 12 123 12 12 1234 123 12 t CMS t CMH 123 123 123 COMMAND 123 123 123 123 123 ACTIVE 123 123 t CK t CKS t CKH NOP 12 12 12 12 12 t AS t AH 123 123 t AS 123 123 123 123 123 123 12 1234 12 123 123412 12 1234 12 123 12 123 123412 12 12 123 123412 t CMH 12 1234 123 12 12 123 12 121234 1234 123 12 1234 12 123 12 121234 123 12 t AH T5 T6 T7 NOP 123 1234 123 12 123 123 12 1231234 1234 123 12 1234 123 123 12 1231234 123 12 123 1234 123 12 123 123 12 1231234 1234 123 12 1234 123 123 12 1231234 123 12 123 1234 123 12 123 123 12 1231234 1234 123 12 1234 123 123 12 1231234 123 12 123 123 123 123ACTIVE 123 123 123 123 123 123 123 123 123 123 123 123 123 123 READ 123 123 123 12 12 123 121234 1234 123412 123 12 123 12123412 12 123 12123412 123 12 123 12 123 121234 1234 123 12 1234 123 12 123 12 123 121234 123 12 123 121234 123 12 123 12 123 12 123 121234 1234 123 12 1234 123 12 123 12 123 121234 123 12 123 121234 123 12 1234567 1234567 12345 123456 12345 123456 1234567 1234567 12345 123456 12345 123456 12345 12345 1234567 1234567 123456 123456 COLUMN m 123456 1234567 1234567 12345 12345 123456 12345 12345 1234567 1234567 123456 123456 123 A10 123 ROW 123 12 1234 123 12 12 1234 123 12 12 1234 123 12 1234 12 123 12 12 1234 123 12 t AH ROW t AS T4 T8 CH READ t CMS 12345 123456789012345678 12345 123456789012345678 12345 123456789012345678 DQM / 12345 123456789012345678 123456789012345678 DQML, DQMH 12345 123 123 A0-A9, 123 123 A11 123 T3 CL 2 123456 12345678 12 12345 12 1234567 12 12345 ENABLE 123456 12345678 12 12345 12AUTO PRECHARGE 1234567 12123456 12345 123456 123456 12345678 12 12345 12 1234567 12 12345 123456 12 12345 12 1234567 12123456 123456 12345678 12345 123456 12345678 12 12345 12 1234567 12123456 12345 123 12 1234 12 123 12 1234 123412 123 12 123 12123412 12 123 12123412 ROW ROW NOP 123 1234 123 12 123 1234 123 12 1231234 123 12 1234 123 123 12 1231234 123 12 NOP 123 123456 123 123ACTIVE123456 123456 123 123456 123 123456 123 12 1234 123 12 121234 123 1234 123 12 12 123 123 12 121234 123 123 12 121234 123 123 12 123456 12345 123456 123456 12345 123456 123456 12345 123456 123456 12345 123456 12345 12345 123456 123456 123456 123456 COLUMN b 123456 123456 12345 123456 12345 123456 12345 12345 123456 123456 123456 123456 2 1234567 123456 12345678 12 12345 12 12345678 12 123456 12 ENABLE 1234567 123456 12345678 12 12345 12 AUTO PRECHARGE 12345678 121234 1234 123456 12 1234567 1234567 123456 12 12345678 12345 12 12345678 12 1234 123456 12 1234567 123456 12 12345 12 12345678 12 123456 12 12345678 1234567 1234 1234567 12345 123456 12 12345678 12 12345678 121234 123456 123 12 12345 123 12 12 123 123 12 1212345 123 12345 123 12 12345 12 123 123 12 1212345 123 123 12 ROW ROW 123 12 12 123 121234 1234 123412 123 12 123 12123412 12 123 12123412 123456 12345 123456 12345 12345 123456 123456 12345 12345 123456 123456 12345 123456 12345 123456 12345 123456 12345 123456 12345 12345 1234 1234567 1234 123 1234567890123 123 1234 12345 1234 1234567 1234 12345678901234 123 12345678901234 1234 12341234567 12345671234 1234 1234567890123 12312345 1234 12345 12345 1234 1234567 1234 123 12345678901234 1234 1234567 1234 1234567890123 123 1234 BANK 0 12345 BANK 0 BANK 0 BA0, BA1 12345 1234 1234567 1234 12345678901234 123 1234 12345671234 123 1234 BANK 1234567890123 4 BANK 4 12345 1234 1234567 1234 12345678901234 123412345671234 1234567890123 12312345 1234 12345 t t t t AC t AC t OH 12345678 12345678 12345678 12345678 DOUT m 12345678 12345678 DQ t AC AC AC AC t OH t OH t OH t OH 123 123 1234 1234 123 123 1234 1234 123 123 DOUT m+1123 123 DOUT m+21234 1234D m+31234 1234 DOUT b 123 123 1234 1234 OUT 123 123 1234 1234 123 123 123 123 123 123 t LZ t RCD - BANK 0 t RCD - BANK 0 t RP - BANK 0 CAS Latency - BANK 0 t RAS - BANK 0 t RC - BANK 0 t RRD RCD - BANK 1 CAS Latency - BANK 1 TIMING PARAMETERS -8 SYMBOL* MIN -8 -10 MAX MIN MAX UNITS SYMBOL* MIN 123 123 123 Don’t Care 123 1234 1234 1234 Undefined 1234 1234 -10 MAX MIN MAX UNITS tAC(3) 6.5 7 ns tCMH 1 1 ns tAC(2) 9 9 ns tCMS ns 2 3 tAH 1 1 ns tLZ 1 1 ns tAS 2 3 ns tOH 2.5 2.5 ns tCH 3 3.5 ns tRAS 50 tCL 3 3.5 ns tRC 80 90 ns tCK(3) 8 10 ns tRCD 20 30 ns tCK(2) 12 15 ns tRP 24 30 ns tCKH 1 1 ns tRRD 20 20 ns tCKS 2 3 ns 80,000 60 80,000 ns * CAS latency indicated in parentheseses. NOTE: 1. For this example, the burst length = 4, the CAS latency = 2. 2. x16: A8, A9 and A11 = “Don’t Care.” AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 41 SDRAM AS4SD4M16 Austin Semiconductor, Inc. READ -- FULL-PAGE BURST1 T0 T1 t CLK T2 t CL t T3 T4 T5 T6 Tn+1 Tn+2 Tn+3 CH t CKS t CKH 12345 123 123 12 1234 123 12 123 12 123 12 123 12 123 12 123 12 123 12 123 12345 12 12123 123 123 12 12 123 12 1234 123 12 12 121234 123 1234 12 123 1231234 1234 123 12 12 121234 1234 123 12 12 121234 1234 123 12 123 1231234 1234 123 12 12 121234 1234 123 12 12 121234 123 123412 12 12345 12 123 123 12 12 123 12 12 123 12 1231234 123 12 121234 123 12 121234 123 12 1231234 123 12 121234 123 12 12 123 1234 1234 CKE 123 1234 1234 123412 12345 123 12123 12 12 123 123 12 123 12 12 1231234 123 12 121234 123 12 121234 123 12 1231234 123 12 121234 123 12 123 121234 12 t CMS t CMH Tn+4 CK 12 1234 123 12 12 123 12 121234 123 12 1234 121234 123 12 123 123 12 12 12 12 123 123 12 12 123 123 12 12 123 123 12 12 12 12 123 123 123 12 12 123 12 123 12 123 12 12 123 12 123 121234 1234 123 12 1234 12 12 123 121234 123 12 12 121234 123 12 12 121234 1234 123412 12 12123412 12 12123412 123 ACTIVE 12 NOP 12 READ 123 NOP 12 NOP 123 NOP 12 NOP 123 NOP 12 BURST 12 NOP 123NOP COMMAND 123 12 12 123 12 123 12 123 12 TERM 12 123 t CMS 123 12345 12345678901234567 1234 12 t CMH 123456 12 123 1234 12 12 1234 123 12 12 123 1234 12 12 123 1234 12 12345678901234567 123456 DQM / 12345 123456 12345 12345678901234567 123456 12345 12345678901234567 123456 DQML, 12345 123456 12345678901234567 123456 DQMH t AS t AH 123 123456 1234567 12345 123 123456 1234567 12345 A0-A9, 1234567 123 12345 123 ROW 123456 123456 1234567 12345 A11 t AS COLUMN m2 123 12 12 123 121234 123412 123 12 12 123 12 121234 123 123412 12 123 123 121234 123 12 123 1234 12 12 123 123 12 1234 123 12 123 12 121234 123 12 123 121234 123 12 1234 12 12 123 121234 123 12 12 121234 123 1234 123 1234 1231234567890123 123456789012311 1234 123 1234 1234567890123 123123456789012311 1234 123456 12345678901234567890123456789012123456789012345678901 123456 12345678901234567890123456789012123456789012345678901 12345678901234567890123456789012123456789012345678901 123456 123456 12345678901234567890123456789012123456789012345678901 t AH 123 123456 12 1234567890123456789012345678901212345678901234567890123456789012123456 12 123 123456 12 1234567890123456789012345678901212345678901234567890123456789012123456 12 123 123456 12 1234567890123456789012345678901212345678901234567890123456789012123456 12 ROW A10 123 123456 12 12 1234567890123456789012345678901212345678901234567890123456789012123456 123 123456 12 1234567890123456789012345678901212345678901234567890123456789012123456 12 t AS t AH 123 123456 1234567 123456 123456 12345678901234567890123456789012123456789012345678901 123 123456 1234567 123456 123456 12345678901234567890123456789012123456789012345678901 123 123456 1234567 123456 123456 12345678901234567890123456789012123456789012345678901 123 BANK 123456 1234567 123456 BANK 123456 12345678901234567890123456789012123456789012345678901 BA0, BA1 123 123456 1234567 123456 123456 12345678901234567890123456789012123456789012345678901 t AC t t AC OH 12345678 12345678 12345678 12345678 DOUT m 12345678 12345678 DQ t AC t AC t t OH OH 123 123 123 123 123 123 123 DOUT m+1 123 DOUTm+2 123 123 123 123 t AC t AC t OH 123 123 123 123 DOUT m-1 123 123 123 123 123 123 123 123 t OH DOUT m t LZ t RCD t OH 123 12 123 12 123 1 123 D m+1 12 12 1 12 123 OUT 123 12 t HZ 123 123 256 (x16) locations within same row. CAS Latency 123Don’t Care 12345 12345 12345 12345Undefined Full page completed. Full-page burst does not self-terminate. 3 Can use BURST TERMINATE command. TIMING PARAMETERS -8 SYMBOL* MIN -10 MAX MIN -8 MAX UNITS SYMBOL* MIN -10 MAX MIN tAC(3) 6.5 7 ns tCMH 1 1 tAC(2) 9 9 ns tCMS 2 3 ns tHZ(3) MAX UNITS ns ns tAH 1 tAS 2 3 ns tHZ(2) tCH 3 3.5 ns tLZ 1 1 tCL 3 3.5 ns tOH 2.5 2.5 ns tCK(3) 8 10 ns tRCD 20 30 ns 1 tCK(2) 12 15 ns tCKH 1 1 ns tCKS 2 3 ns 6 7 8 ns 10 ns ns * CAS latency indicated in parentheseses. NOTE: 1. For this example, the CAS latency = 2. 2. x16: A8, A9 and A11 = “Don’t Care.” 3. Page left open, no tRP. AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 42 SDRAM AS4SD4M16 Austin Semiconductor, Inc. READ -- DQM OPERATION1 T0 T1 T2 t CLK t t CKS 123456 123456 123456 123456 CKE 123456 t CK t CKH 123 1234 123 12 123 1234 123 12 123 1234 123 12 123 1234 123 12 1234 123 123 12 T3 T4 T5 T6 T7 T8 CL 12 1234 123 12 12 1234 123 12 12 1234 123 12 12 1234 123 12 1234 12 123 12 CH 123 12 12345 123 12 12 123 12345 123 12 12 123 12345 123 12 12 123 12345 123 12 12345 12 123 123 12 123 1234 123 12 123 123 12 1231234 1234 123 12 123 1234 123 12 1231234 123 12 123 1234 123 12 123 123 12 1231234 1234 123 12 123 1234 123 12 1231234 123 12 12 123412 123 12 123 121234 123412 123 12 12 1234 123 12123412 123 12 123 12 12345 123 12 12 123 123 12 1212345 123 12345 123 12 12 123 12345 123 12 1212345 123 123 12 123 12 12345 123 12 12 123 12345 123 12 1212345 123 123 12 12 123 12345 123 12 1212345 123 123 12 123 1234 123 12 123 123 12 1231234 1234 123 12 123 1234 123 12 1231234 123 12 t CMS t CMH 123 123 12 12 123 123 123 123 123 123 12 12 123 12 123 123 123 12 12 123 123 123 12 COMMAND123 123ACTIVE 12 NOP 123 READ 123 NOP 123 NOP 12 t CMS t CMH 12345 123456 1234567890123456789 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 12345 1234567890123456789 DQM / 123456 12345 123456 1234567890123456789 12345 1234567890123456789 DQML, 123456 12345 123456 1234567890123456789 DQMH t AS t AH 123 123 1234567 12345678 123456 1234567 12345678 123456 123 12 1234 123 12 123412 12 123 12 123 121234 123412 12 123 12123412 123 123 123 123 123 NOP NOP 123 123 123 123 123 NOP 12 12 12 12 12 NOP 123456 123456 123456 123456 123456 1234 12 1234123456789012345678901234567890 123456789012345678901234567890 12 1234 123456789012345678901234567890 12 1234123456789012345678901234567890 12 1234123456789012345678901234567890 12 1234567 12345678901234567890123456789012123456789012345678 1234567 12345678901234567890123456789012123456789012345678 12345678 12345678901234567890123456789012123456789012345678 123 123456 A0-A9, 123 ROW 1234567 1234567 12345678 123456COLUMN m1234567 1234567 12345678901234567890123456789012123456789012345678 12345678 12345678901234567890123456789012123456789012345678 1234567 123456 1234567 A11123 2 123 123 123 A10123 123 t AS ROW t AS 123 123 123 123 BA0, BA1 123 t AH t AH BANK 1234567 12345678 1 123456 12 123456 11234567890123456789012345678901212345678901234567 12 ENABLE 1234567 12345678 1 123456 12 AUTO PRECHARGE 123456 11234567890123456789012345678901212345678901234567 12 12345678 1234567890123456789012345678901212345678901234567 1234567 1 123456 12 123456 1 12 1234567 12345678 1 123456 12 123456 1234567890123456789012345678901212345678901234567 1 12 12345678 1234567890123456789012345678901212345678901234567 1234567 1 123456 12 123456 1 12 DISABLE AUTO PRECHARGE 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 BANK 123456 123456 12345678901234567890123456789012123456789012345678 123456 12345678901234567890123456789012123456789012345678 123456 12345678901234567890123456789012123456789012345678 123456 12345678901234567890123456789012123456789012345678 t AC DQ t LZ t RCD t OH 12345678 12345678 12345678 12345678 D m 12345678 12345678 OUT 12345678 t AC t AC 12 12 12 12 12 12 t OH t OH 123456789 1234 12 123456789 1234 12 123456789 123456789 D m+21234 1234D m+3 12 12 123456789 1234 12 OUT OUT 123456789 1234 12 123456789 1234 t HZ t LZ t HZ CAS Latency 123 123 123 1234Don’t Care 1234 1234 Undefined 1234 1234 TIMING PARAMETERS -8 SYMBOL* MIN -8 -10 MAX MIN MAX UNITS SYMBOL* MIN -10 MAX MIN tAC(3) 6.5 7 ns tCMH 1 1 tAC(2) 9 9 ns tCMS 2 3 MAX UNITS ns ns tAH 1 1 ns tHZ(3) 6 8 ns tAS 2 3 ns tHZ(2) 7 10 ns tCH 3 3.5 ns tLZ 1 1 ns tCL 3 3.5 ns tOH 2.5 2.5 ns tCK(3) 8 10 ns tRCD 20 30 ns tCK(2) 12 15 ns tCKH 1 1 ns tCKS 2 3 ns * CAS latency indicated in parentheseses. NOTE: 1. For this example, the burst length = 4 , the CAS latency = 2. 2. x16: A8, A9 and A11 = “Don’t Care.” AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 43 SDRAM AS4SD4M16 Austin Semiconductor, Inc. WRITE -- WITHOUT AUTO PRECHARGE1 T0 T1 T2 t CLK t 123456 123456 123456 CKE 123456 123456 123 12 1234 123 12 12 123 123 12 121234 123 123 12 1234 12 123 1234 123 12 121234 123 123 12 t CMS t CMH 1234 123 1234 1234ACTIVE 123 123 1234 123 COMMAND 1234 123 t CK t CKS t CKH T3 123 1234 123 12 123 1234 123 12 123 123 12 1234 123 1234 123 12 123 1234 123 12 NOP 12 12 12 12 12 123 1234 123 12 123 123 12 1231234 123 12 1234 123 1234 123 12 1231234 123 12 WRITE 123 123 123 123 123 12 1234 123 12 12 123 12 121234 123 12 1234 12 1234 123 12 121234 123 12 NOP t CMS t CMH 12345 1234567890123456789 123 12 123 121234 123412 12 123 12 123 121234 123412 12 123 12123412 AS ROW t AS 123 123 123 A10123 123 t AH ROW t AS 1234 1234 1234 1234 BA0, BA1 1234 AH t AH T5 T6 12 12 12 12 12 123 1234 123 12 123 123 12 1231234 123 12 1234 123 1234 123 12 1231234 123 12 NOP 12 12 12 12 12 123 1234 123 12 123 123 12 1231234 123 12 1234 123 1234 123 12 1231234 123 12 123 12 12 121234 123 1234123 123123 123 121234 123412 12 12 123 1234 123 123 12 121234123123 123 121234 123412 12 121234123123 123 12123412 12 123412 123 12 123 12 121234 123 12 1234 12 1234 123 12123412 123 12 12 123 12 12 PRECHARGE 123 123 12 123 12 123 NOP T8 12 1234 123 12 123412 123 12 12 123 12 1234 12 1234 123 12123412 123 12 NOP 123456 12345678 1234567 123456 12345678 1234567 123456 12345678 1234567 123456 12345678 1234567 COLUMN 123456 12345678 1234567 m 2 123456 12345678901234567890123456789012 123456 123456 12345678901234567890123456789012 123456 123456 12345678901234567890123456789012 123456 123456 12345678901234567890123456789012 123456 123456 12345678901234567890123456789012 123456 123456 1234567 1 1234 123456 1234567 1 1234 1234567 123456 1 1234 123456 1234567 1 1234 123456 1234567 1 1234 12345 1234567890123456789 123456 123456 12345 12345 1234567890123456789 123456ALL BANKS1234567 1234567 123456 12345 1234567890123456789 12345 12345 123456 1234567 123456 12345 1234567890123456789 123456 1234567 123456 12345 12345 1234567890123456789 123456 1234567 123456 12345 123456 1234567 123456 123456 1234567 123456 1234567 123456 123456 123456 1234567 123456 1234567 123456 123456 t BANK DS 12345678901234567 123456 12345678901234567 123456 12345678901234567 123456 123456 DQ 12345678901234567 12345678901234567 123456 t DH DIN m DS 123 123456 123 123ACTIVE 123456 123456 123 123456 123 123456 ROW ROW 123456 12345 123456 12345 123456 12345 123456 12345 123456 12345 123456 12345 123456 12345 12345 123456 123456 12345 123456 12345 SINGLE BANK 123456 12345678901234567 123456 123456 12345678901234567 123456 12345678901234567 123456 123456 123456 12345678901234567 123456 12345678901234567 123456 123456 t 12 123412 123 12 123 12 121234 123 12 1234 12 1234 123 12123412 123 12 1234 123 12312345678901234567890123456789 1234 1234567890123456789012345678911 123 1234 12345678901234567890123456789 1231234567890123456789012345678911 1234 123123456789012345678901234567891 1234 DISABLE AUTO PRECHARGE BANK T7 CH DQM / 12345 1234567890123456789 12345 1234567890123456789 DQML, 12345 1234567890123456789 12345 1234567890123456789 DQMH t t 123 123 A0-A9,123 123 A11123 T4 CL t DH 123 123 123 123 DIN m+1 123 t DS t t DH DS t BANK 1234567 123456 12345 1234567 123456 12345 12345 1234567 123456 1234567 123456 12345 12345 1234567 123456 BANK 123456 12345 123456 12345 12345 123456 123456 12345 12345 123456 DH 12 123 12345 123456789012345678901234567 12 12 123 12345 12345678901234567890123456711 12 12 123 12345 123456789012345678901234567 12 11 12 DIN m+2 123DIN m+3 12345 12 123456789012345678901234567 12 123 12345 123456789012345678901234567 12 1 t WR2 t RCD t RP t RAS t RC 123 123 123 Don’t Care 123 1234 1234 1234 1234 Undefined TIMING PARAMETERS -8 SYMBOL* NOTE: MIN -8 -10 MAX MIN MAX UNITS SYMBOL* MIN -10 MAX MIN MAX UNITS tAC(3) 6.5 7 ns tCMH 1 1 ns tAC(2) 9 9 ns tCMS 2 3 ns ns tAH 1 1 ns tDH 1 1 tAS 2 3 ns tDS 2 3 tCH 3 3.5 ns tRAS 50 tCL 3 3.5 ns tRC 80 90 ns tCK(3) 8 10 ns tRCD 20 30 ns tCK(2) 12 15 ns tRP 24 30 ns tCKH 1 1 ns tWR 15 15 ns tCKS 2 3 ns 80,000 60 ns 80,000 ns * CAS latency indicated in parentheseses. 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE. 2. 15ns are required between <DINm+3> and the PRECHARGE command, regardless of frequency. 3. x16: A8, A9 and A11 = “Don’t Care.” AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 44 SDRAM AS4SD4M16 Austin Semiconductor, Inc. WRITE -- WITH AUTO PRECHARGE1 T0 CLK T2 T1 t t T3 t CK 123456 1234 123 12 123 12 1231234 123456 12 12 1234 123 12 123 123 1234 123 12 12 121234 123412 12 12 1234 123 12 12 123 12 121234 1234 123 12 1234 12 123 12 121234 123 12 123 123 12 1234 123 12 123 1234 123 12 12 1234 CKE123456 123 1234 1234 123412 123456 12 123 12 123 123 12 12 12 123 123 123456 12 1234 123 12 123 1234 123 12 12 123412 t CMS t CMH 123 123 NOP 123 WRITE 123 123 CMS 12345 123456789012345678 12345 123456789012345678 12345 123456789012345678 12345 123456789012345678 t DQM / DQML, DQMH t AS 1234 1234 A0-A9,1234 1234 A111234 ROW t AS 1234 1234 A101234 1234 t AH t AH T8 T7 T9 123456 1234567 123456 123456 1234567 123456 123456 1234567 123456 123456 1234567 123456 123456 1234567 123456 12 12 12 12 12 NOP t CMH 123 123 1234 123 123 123412 12 123 123 1234 123 12 123 123 1234 12 123 123 123 123 123 123 123 12 123412 12 12 121234 1234 123412 12 12123412 12 NOP 123 12 12 121234 123 1234 123412 12 123 12123412 123 12 12 12 12 12 12 123 1234 123 12 123 123 12 1231234 1234 123 12 1234 123 123 12 1231234 123 12 NOP 123 123 12 1234 123 12 123 1234 123 1234123 12 121234123 123 123 123 123 123 123 123 123 12 123123 12 12 123 123 12 12123 123 123 123 12 123123 12 123 12 12123123 123 12 123 123 NOP 123 123 123 12 1234 123 12 12 123 12 121234 1234 123 12 1234 12 123 12 121234 123 12 123 123123 12 123 123 12 123123 123 123 12 123123 123 12 123123123 12 12 12 12 12 12 12 12 12 12 12 NOP NOP 123456 1234567890123456789012345678901212345678 123456 123456 1234567890123456789012345678901212345678 123456 123456 1234567890123456789012345678901212345678 123456 123456 1234567890123456789012345678901212345678 123456 123456 1234567890123456789012345678901212345678 123456 COLUMN m2 t AH 1234 123456 123456 123456 1234 123456 123456 123456 1234 123456 123456 123456 BANK BA0, BA11234 123456 123456 123456 1234 123456 123456 123456 t DS 12345 123456789012345678901234567890121234567 123456 12345 123456789012345678901234567890121234567 123456 12345 123456789012345678901234567890121234567 123456 12345 123456789012345678901234567890121234567 123456 12345 123456789012345678901234567890121234567 123456 BANK t DH 1234567890123456 123456 1234567890123456 123456 1234567890123456 123456 123456DIN m DQ 1234567890123456 t DS t DH 12 12 12 12 DIN m+1 t DS t DH t DS 12 1234 123 12 12 1234 123 12 121234 123 12 1234 12 123 12 121234 123 12 1234567 1234567 ACTIVE 1234567 1234567 1234567 1234 123 1 12312345678901234567890123456789012123 1234 12345678901234567890123456789012123 1234567890123456789012345678901212311 123 1234 123123456789012345678901234567890121231 1234 ENABLE AUTO PRECHARGE 123456 1234567 1 12345 1 12345 1234567890123456789012345678901212345678901 123456 123456 1234567 1 12345 1 12345 1234567890123456789012345678901212345678901 123456 1234567 1234567890123456789012345678901212345678901 123456 1 12345 1 12345 123456 123456 1234567 1 12345 1 12345 1234567890123456789012345678901212345678901 123456 ROW t AS T6 CH t CKS t CKH 123 123 123 123 123 COMMAND 123ACTIVE 123 123 123 123 T5 T4 CL t ROW ROW BANK 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 DH 12 123 12345 112345678901234567890123456789012 11 12 123 12345 112345678901234567890123456789012 12345678901234567890123456789012 12 123 12345 1 12 DIN m+2123DIN m+3 12345 11234567890123456789012345678901211 t WR2 t RCD t RAS t RP t RC 123 123 Don’t Care 123 1234 1234 1234 1234 Undefined TIMING PARAMETERS -8 SYMBOL* MIN -10 MAX MIN -8 MAX UNITS MIN SYMBOL* -10 MAX MIN MAX UNITS tAH 1 1 ns tDH 1 1 ns tAS 2 3 ns tDS 2 3 ns tCH 3 3.5 ns tRAS 50 tCL 3 3.5 ns tRC 80 90 ns tCK(3) 8 10 ns tRCD 20 30 ns tCK(2) 12 15 ns tRP 24 30 ns tCKH 1 1 ns tCKS 2 3 ns tWR 1 CLK+ 8ns 1 CLK+ 8ns ns tCMH 1 1 ns tCMS 2 3 ns 80,000 60 80,000 ns * CAS latency indicated in parentheseses. NOTE: 1. For this example, the burst length = 4, i.e., two-clock minimum for tWR. 2. x16: A8, A9 and A11 = “Don’t Care.” AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 45 SDRAM AS4SD4M16 Austin Semiconductor, Inc. ALTERNATING BANK WRITE ACCESSES1 T0 T1 T2 t CLK t 12345 12345 12345 12345 t CK t CKS t CKH T3 T4 T5 T6 T7 T8 T9 CL CH 123 1234 123 12 123 1234 123 12 1234 123 123 12 123 1234 123 123 12 1234 123 12 12 123 1234 123 12 1234 12 123 123 12 123 1234 12 12 123 12 121234 1234 123 12 1234 12 123 12 12 1234 123 123 123 12 1231234 1234 123 12 1234 123 123 12 1231234 123 12 123 12 121234 1234 123 12 1234 12 123 12 121234 123 123 123 12 1231234 1234 123 12 1234 123 123 12 1231234 123 123 123 12 1231234 1234 123 12 1234 123 123 12 1231234 123 12 121234 123412 12 123412 12 12123412 123 123 12 1231234 1234 123 12 1234 123 123 12 1231234 123 12 12 123 123 123 123 12 12 123 123 12 12 123 123 123 123 12 12 123 1234 123 123412 12 12 12 123 1234 123 123412 12 12 12 123 123412 123 1234 123 1234123 123 12 12 123 1234 123 1234123 123 12 121234123 123 123 1234 123 123412 12 12 12 123 1234 123 123412 12 12 12123412 123 12 121234 123412 12 121234 123412 12 12 12123412 123 123 12 123 123123 123 12 12 12 123 123 123 12 123123123 12 12 12123123 123 12 123 1234 123 123412 12 12 12 123 1234 123 123412 12 12 12123412 123 123 1234 123 123412 12 12 12 123 1234 123 123412 12 12 12123412 123 123 12 123 121234 123 123412 123 12 123412 12 123 123 1234123 12 CKE 12345 123 1234 123 12 123 12 1234 123 12 12 1234 123 12 1231234 123 12 121234 123 12 1231234 123 12 1231234 123 12 12123412 1231234 123 12 123 12123412 123 t CMS t CMH 123 123 12 123 123 12 123 12 123 123 12 COMMAND 123 123 ACTIVE 12 NOP 123WRITE 123 NOP 12ACTIVE123 NOP 12 WRITE 123 NOP 123 NOP 12 DQM / DQML, DQMH t CMS 123456 1234 123456789012345678 123456 1234 123456789012345678 123456 1234 123456789012345678 123456 1234 123456789012345678 123456 1234 123456789012345678 t AS 123 123 A0-A9,123 123 A11123 123 123 A10 123 123 t AH ROW t AS t AH ROW t AS t CMH 123456 123456 1234 123456 123456 COLUMN 1234 123456 123456 1234 123456 123456 m 3 1234 123456 123456 1234 123456 12345 123456 123456 12345 123456 123456 12345 123456 123456 12345 123456 ENABLE AUTO PRECHARGE 123456 12 1234567 12345 12 1234567 12 12345 123456 123456 12 1234567 12345 12 1234567 12 12345 123456 1234567 12345 123456 12 12345 12 1234567 12 123456 12 1234567 12345 12 1234567 12123456 12345 123456 ACTIVE 123456 123456 1234 123456 12345678901234 123456 123456 123456 123456 12345678901234 123456 1234 123456 123456 1234 123456 12345678901234 123456 COLUMN b 123456 123456 1234 123456 12345678901234 123456 123456 123456 123456 123456 ROW ENABLE 123456 12345 11234567 12345 11 AUTO PRECHARGE 12345678901234567 112345 12345 123456 12345 11234567 12345 12345678901234567 1123456 123456 12345 1234567 12345 123456 1 12345 1 12345678901234567 11123456 123456 12345 11234567 12345 1 12345678901234567 12345 123456 ROW 123 12 121234 123 1234123 123 12 123 1234 121234123 123 123 121234123 123 ROW 3 1234567 1234567 1234567 1234567 ROW 123456 123456 123456 123456 123456 123456 123456 123456 123456 t AH 1234 123 1234567 1234 123 123 12345678901234567890 1234 1234 123 1234567 1234 12345678901234 12345678901234 1234 1234 1231234567 12345671234 1234 123 12345678901234567890 123412345 12345 1234 123 1234567 1234 12345678901234 1234 123 1234567 1234 123 12345678901234567890 1234 BANK 0 12345 BANK 0 BANK 0 123 1234567 1234 12345678901234 1234 123 1234567 1234 123 12345678901234567890 1234 12345 BA0, BA11234 BANK 1 1234567 1 1234 123 1234567 1234 12345678901234 1234 123 1234 123BANK 12345678901234567890 123412345 t 12345678901234567 123456 12345678901234567 123456 12345678901234567 123456 DQ 12345678901234567 123456 12345678901234567 123456 t DS DH DIN m t DS t DH t DS t DH t DS t t RCD - BANK 0 t RAS - BANK 0 1234 1234 1234 Don’t Care 12345 DH DIN b t 12 12 12 12 DS tDH DIN b+1 t DS t DH 12 12 12 12 DIN b+2 t RP - BANK 0 t WR - BANK 0 t RC - BANK 0 t RRD 12345 12345 12345Undefined t t DS DH 12 123 123 123 12 123 123 123 12 123 123 12 DIN m+1123 DIN m+2123DIN m+3 123 123 12 123 123 123 t t DH DS 12 123 12 123 12 12 DIN b+3 123 123 tRCD - BANK 0 t t RCD - BANK 1 WR - BANK 1 TIMING PARAMETERS -8 SYMBOL* MIN -10 MAX MIN -8 MAX UNITS SYMBOL* MIN -10 MAX MIN MAX UNITS tAH 1 1 ns tDH 1 1 tAS 2 3 ns tDS 2 2 tCH 3 3.5 ns tRAS 50 tCL 3 3.5 ns tRC 80 90 ns tCK(3) 8 10 ns tRCD 20 30 ns tCK(2) 12 15 ns 24 30 ns tCKH 1 1 ns tRP 20 20 ns tCKS 2 3 ns tRRD tCMH 1 1 ns tWR 1 CLK+ 8ns 1 CLK+ 8ns ns tCMS 2 3 ns 80,000 60 ns ns 80,000 ns * CAS latency indicated in parentheseses. NOTES: 1. For this example, the burst length = 4, i.e., two-clock minimum for tWR. 2. Requires once clock plus time (8ns) with AUTO PRECHARGE or 15ns with PRECHARGE. 3. x16: A8, A9 and A11 = “Don’t Care.” AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 46 SDRAM AS4SD4M16 Austin Semiconductor, Inc. WRITE -- FULL-PAGE BURST T0 t CLK T1 t CL t t CKS 123456 123456 123456 CKE123456 123456 123456 t CKH 123 1234 123 1234 123 123 12 123 123 1234 12 123 1234 123 12 1234 123 123 12 123 1234 12 t CMS t CMH 1234 1234 1234 COMMAND1234 ACTIVE 1234 123 123 123 123 123 T2 123 1234 12 1234 12 123 123 12 123 1234 123 123 1234 123 12 1234 12 123 123 123 1234 123 NOP 123 123 123 123 123 12 1234512 12 12 123 123 1212345 12 123 12345 123 12 123 12345 123 12 1212345 12 123 123 123 12345 123 WRITE CMS 123456 1234567890123456789 12345678 12345678 123456 1234567890123456789 12345678 123456 1234567890123456789 12345678 12345678 1234567890123456789 123456 12345678 123456 1234567890123456789 12345678 t AS 1234 1234 t AH 12 12 12 12 12 123 12 123 12 1212345 123 12345 123 12 12 123 12345 123 12 1212345 123 123 12 1212345 123 123 12 1234567 123456789 1234567 1234567 123456789 1234567 1234 1234 1234 A101234 1234 1234 1234 1234 BA0, BA11234 1234 T5 Tn+1 Tn+2 Tn+3 12 12 12 12 12 123 12 12 121234 123 1234123 123 12 12 123 1234 123 12 121234123 123 12 121234123 123 12 12 1234512 12 12 123 123 1212345 12 123 12345 123 12 123 12345 123 12 1212345 12 123 123 123 12345 123 121234 1234123 12 123 12 123 121234 1234 1234123 12 121234123 123 123 123 123 123 123 123 123 123 123 123 NOP NOP 123 12 121234 123 123412 12 12 123 12 121234 123 12 1234 12123412 123 1231234 1234123 123 123 12 123 123 12 1231234 1234 123 123412 123 123 123123412 12 NOP 123 12 123 12 1212345 123 12345 123 12 12 123 12345 123 12 1212345 123 123 12 1212345 123 123 12 12 12 12 12 12 123 123 1234 123 123 1234123 123 123 123 1234123 123 123 123 1234 123 123 1234123 12 12345 12 12 12345 12 123 123 1212345 12 123 123 12 123 12345 123 12 1212345 12 123 123 123 12345 123 BURST TERM 12 12 12 12 12 NOP 1234 123412345678 1234567812 12 1234 12345678 12341234567812 12 12341234567812 123456 1234567890123456789012345678901212345678901234 123456 1234567890123456789012345678901212345678901234 123456 1234567890123456789012345678901212345678901234 123456 1234567890123456789012345678901212345678901234 123456 1234567890123456789012345678901212345678901234 123456 1234567890123456789012345678901212345678901234 t AH 123456 1234567890123456789012345678901212345678901234567890123456789012123 12 123456 123456789012345678901234567890121234567890123456789012345678901212311 12 1234567890123456789012345678901212345678901234567890123456789012123 123456 12 11 123456 1234567890123456789012345678901212345678901234567890123456789012123 12 1234567890123456789012345678901212345678901234567890123456789012123 123456 12 1 ROW t AS 121234 1234123 12 123 12 123 121234 1234 1234123 12 121234123 123 NOP t CMH 123456789 1234567 A0-A9,1234 1234 ROW 1234567 1234567 123456789 1234567 COLUMN 1234 1234567 123456789 1234567 A111234 1234567 123456789 1234567 m 1 t AS T4 CH t DQM / DQML, DQMH T3 CK t AH BANK 1234567 12345678 123456 1234567 12345678 123456 1234567 12345678 123456 1234567 12345678 123456 1234567 12345678 123456 t BANK t DS 123456789012345678 123456 123456789012345678 123456 123456789012345678 123456 123456789012345678 123456 DQ 123456789012345678 123456 123456789012345678 123456 123456 1234567890123456789012345678901212345678901234 123456 1234567890123456789012345678901212345678901234 123456 1234567890123456789012345678901212345678901234 123456 1234567890123456789012345678901212345678901234 123456 1234567890123456789012345678901212345678901234 DH DIN m t DS 123 123 123 123 123 123 t t DH DS t DH 123 123 123 DIN m+1 123 D m+2 123 123 IN t DS t t DS DH 123 123 123 123DIN m+3 123 123 t DH 123 123 123 123 DIN m-1 123 123 t RCD 256 (x16) locations within same row. t DS t DH 12 1234567 123456 1234 123456789 12 1234567 123456 1234 1234 123456789 12 1234567 123456 123456789 12 1234567 123456 1234 1234 123456789 12 1234567 123456 12 1234567 123456123456789 123456789 Full-page burst does not self-terminate. Can use BURST TERMINATE command.2,3 1234 1234 1234 Don’t Care 1234 1234 1234 -8 SYMBOL* MIN -8 -10 MAX MIN MAX 1234 1234 Undefined Full page completed. TIMING PARAMETERS SYMBOL* UNITS MIN -10 MAX MIN MAX UNITS tAH 1 1 ns tCKS 2 3 ns tAS 2 3 ns tCMH 1 1 ns tCH 3 3.5 ns tCMS 2 3 ns ns tDH 1 1 ns ns tDS 2 3 ns tRCD 20 30 ns tCL tCK(3) 3 8 3.5 10 tCK(2) 12 15 ns tCKH 1 1 ns * CAS latency indicated in parentheseses. NOTES: 1. x16: A8, A9 and A11 = “Don’t Care.” 2. tWR must be satisfied prior to PRECHARGE command. 3. Page left open, no t RP. AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 47 SDRAM AS4SD4M16 Austin Semiconductor, Inc. WRITE -- DQM OPERATION1 T0 T1 T2 t CLK t t CKS 1234567 1234567 CKE1234567 1234567 1234567 t CKH t CK 123 12 12345 123 12 12 123 12345 123 12 12 123 123 12 12345 12345 12 123 123 12 12 123 12345 123 12 T3 T4 T5 T6 T7 CL 123 12 1234 123 12 12 123 1234 123 12 121234 123 123 12 1234 12 123 123 12 121234 123 123 12 CH 123 12 12345 123 12 12 123 123 12 1212345 123 123 12 12345 12345 12 123 123 12 1212345 123 123 12 123 12 12345 123 12 12 123 123 12 1212345 123 123 12 12345 12345 12 123 123 12 1212345 123 123 12 123 1234 123 123 123 123 123 1231234 123 123 1234 1234 123 123 123 1231234 123 123 123 12 12345 123 12 12 123 123 12 1212345 123 123 12 12345 12345 12 123 123 12 1212345 123 123 12 12 12 12 12 12 12 12 12 12 12 123 12 1234 123 12 12 123 123 12 121234 123 123 12 1234 1234 12 123 123 12 121234 123 123 12 123 12 12345 123 12 12 123 12345 123 12 12 123 123 12 12345 12345 12 123 123 12 12 123 12345 123 12 t CMS t CMH 123 123 123 COMMAND 123 ACTIVE 123 DQM / DQML, DQMH 123 123 123 123 123 NOP 123 123 123 123 123 WRITE t CMS 123456 123456789012345678901 123456 123456789012345678901 123456 123456789012345678901 123456 123456789012345678901 123456 123456789012345678901 t AS ROW t AS 1234 1234 1234 A101234 1234 t CMH 123456 123456 123456 123456 123456 NOP 123456 123456 123456 123456 123456 NOP 123 12 1212345 123 1234512 12 12 123 12345 12 1212345 123 12 121234512 123 NOP 123 123 123 123 123 NOP 123456 123456 123456 123456 123456 1234 12 12341234567890123456789012 1234567890123456789012 12 1234 1234567890123456789012 12 12341234567890123456789012 12 12341234567890123456789012 12 1234567 123456789 1234567 1234567 123456789 1234567 1234567 123456789 1234567 1234567 123456789 1234567 123456789 1234567 1234567 COLUMN m2 1234567 1234567890123456789012345678901212345678901 1234567 1234567890123456789012345678901212345678901 1234567 1234567890123456789012345678901212345678901 1234567 1234567890123456789012345678901212345678901 1234567890123456789012345678901212345678901 1234567 t AH ROW t AS NOP 123 123 123 123 123 t AH 1234 A0-A9,1234 1234 1234 A111234 123 123 123 123 123 ENABLE AUTO PRECHARGE 1234567 12345678 1 1234567 1 1234567 1123456789012345678901234567890121234567890 12 1234567 12345678 1 1234567 1 1234567 1123456789012345678901234567890121234567890 12 1234567 12345678 1 1234567 1 1234567 123456789012345678901234567890121234567890 1 12 1234567 12345678 1 1234567 1 1234567 123456789012345678901234567890121234567890 1 12 1234567 12345678 1 1234567 1 1234567 123456789012345678901234567890121234567890 1 12 t AH 1234 1234 DISABLE AUTO PRECHARGE 1234567 12345678 123456 1234567 12345678 123456 12345678 123456 BA0, BA11234 1234 BANK 1234567 1234567 123456 12345678 1234 BANK 1234567 12345678 123456 t t DS 1234567890123456789 1234567 1234567890123456789 1234567 1234567890123456789 1234567 1234567 DQ 1234567890123456789 1234567890123456789 1234567 1234567 12345678901234567890123456789012123456789012 1234567 12345678901234567890123456789012123456789012 1234567 12345678901234567890123456789012123456789012 1234567 12345678901234567890123456789012123456789012 1234567 12345678901234567890123456789012123456789012 t DH t DS DH 123456 12345 1234567 123456 12345 1234567 12345 123456 1234567 D m+2 123456 12345 1234567 123456 12345 1234567 IN DIN m t DS t DH 123 123 123 D m+3 123 123 IN t RCD 12345678 112345678901234567 12345678 112345678901234567 12345678901234567 12345678 11 12345678 12345678901234567 12345678 12345678901234567 1 123 123 Don’t Care 123 1234 1234 1234 1234 Undefined TIMING PARAMETERS -8 SYMBOL* MIN tAH 1 tAS tCH tCL -10 MAX MIN -8 MAX UNITS SYMBOL* MIN -10 MAX MIN MAX UNITS 1 ns tCKS 2 3 ns 2 3 ns tCMH 1 1 ns 3 3.5 ns tCMS 2 3 ns 3 3.5 ns tDH 1 1 ns tCK(3) 8 10 ns tDS 2 3 ns tCK(2) 12 15 ns tRCD 20 30 ns tCKH 1 1 ns * CAS latency indicated in parentheseses. NOTES: 1. For this example, the burst length = 4. 2. x16: A8, A9 and A11 = “Don’t Care.” AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 48 SDRAM Austin Semiconductor, Inc. AS4SD4M16 MECHANICAL DEFINITIONS ASI Case #901 (Package Designator DG) NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side. AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 49 SDRAM AS4SD4M16 Austin Semiconductor, Inc. ORDERING INFORMATION EXAMPLE: AS4SD4M16DG-10/IT Device Number Package Type Speed ns Process AS4SD4M16 DG -8 /* AS4SD4M16 DG -10 /* *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range AS4SD4M16 Rev. 1.5 10/01 -40oC to +85oC -55oC to +125oC Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 50