SN54AHC05, SN74AHC05 HEX INVERTERS WITH OPEN-DRAIN OUTPUTS SCLS357H – MAY 1997 – REVISED JULY 2003 D D D SN54AHC05 . . . J OR W PACKAGE SN74AHC05 . . . D, DB, DGV, N, OR PW PACKAGE (TOP VIEW) Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 1A 1Y 2A 2Y 3A 3Y GND description/ordering information The ’AHC05 devices contain six independent inverters. These devices perform the Boolean function Y = A. 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 6A 6Y 5A 5Y 4A 4Y SN54AHC05 . . . FK PACKAGE (TOP VIEW) 1Y 1A NC VCC 6A The open-drain outputs require pullup resistors to perform correctly. They can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 6Y NC 5A NC 5Y 3Y GND NC 4Y 4A 2A NC 2Y NC 3A NC – No internal connection ORDERING INFORMATION PDIP – N SN74AHC05N Tube SN74AHC05D Tape and reel SN74AHC05DR Tape and reel SN74AHC05DBR Tube SN74AHC05PW Tape and reel SN74AHC05PWR TVSOP – DGV Tape and reel SN74AHC05DGVR HA05 CDIP – J Tube SNJ54AHC05J SNJ54AHC05J CFP – W Tube SNJ54AHC05W SNJ54AHC05W LCCC – FK Tube SNJ54AHC05FK SNJ54AHC05FK SSOP – DB TSSOP – PW –55°C to 125°C TOP-SIDE MARKING Tube SOIC – D –40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA SN74AHC05N AHC05 HA05 HA05 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AHC05, SN74AHC05 HEX INVERTERS WITH OPEN-DRAIN OUTPUTS SCLS357H – MAY 1997 – REVISED JULY 2003 FUNCTION TABLE (each inverter) INPUT A OUTPUT Y H L L H logic diagram, each inverter (positive logic) A Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AHC05, SN74AHC05 HEX INVERTERS WITH OPEN-DRAIN OUTPUTS SCLS357H – MAY 1997 – REVISED JULY 2003 recommended operating conditions (see Note 3) SN54AHC05 VCC Supply voltage VIH VCC = 2 V VCC = 3 V High-level input voltage Low-level input voltage VI VO 5.5 2 5.5 UNIT V 1.5 2.1 3.85 V 0.5 0.9 0.9 1.65 1.65 V 0 5.5 0 5.5 V 0 VCC 50 0 VCC 50 mA VCC = 5 V ± 0.5 V VCC = 3.3 V ± 0.3 V Input transition rise or fall rate MAX 2.1 VCC = 2 V VCC = 3.3 V ± 0.3 V Low-level output current MIN 3.85 VCC = 3 V VCC = 5.5 V Output voltage ∆t/∆v 2 SN74AHC05 0.5 Input voltage IOL MAX 1.5 VCC = 5.5 V VCC = 2 V VIL MIN VCC = 5 V ± 0.5 V 4 4 8 8 100 100 20 20 V mA ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOL = 50 mA VOL IOL = 4 mA II ICC IOL = 8 mA VI = 5.5 V or GND VI = VCC or GND, VI = VCC or GND IO = 0 MIN TA = 25°C TYP MAX SN54AHC05 MIN MAX SN74AHC05 MIN MAX 2V 0.1 0.1 0.1 3V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 UNIT V 3V 0.36 0.5 0.44 4.5 V 0.36 0.5 0.44 0 V to 5.5 V ±0.1 ±1* ±1 mA 2 20 20 mA 10 pF 5.5 V Ci 5V 2.5 10 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLZ tPZL A Y CL = 15 pF tPLZ tPZL A Y CL = 50 pF MIN TA = 25°C TYP MAX SN54AHC05 SN74AHC05 MIN MAX MIN MAX 2.9** 7.1** 1** 8.5** 1 8.5 4** 7.1** 1** 8.5** 1 8.5 4.7 10.6 1 12 1 12 5.8 10.6 1 12 1 12 UNIT ns ns ** On products compliant to MIL-PRF-38535, this parameter is not production tested. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54AHC05, SN74AHC05 HEX INVERTERS WITH OPEN-DRAIN OUTPUTS SCLS357H – MAY 1997 – REVISED JULY 2003 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLZ tPZL A Y CL = 15 pF tPLZ tPZL A Y CL = 50 pF MIN TA = 25°C TYP MAX SN54AHC05 SN74AHC05 MIN MAX MIN MAX 2.2* 5.5* 1* 6.5* 1 6.5 2.9* 5.5* 1* 6.5* 1 6.5 3.4 7.5 1 8.5 1 8.5 4.2 7.5 1 8.5 1 8.5 UNIT ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP 3 UNIT pF SN54AHC05, SN74AHC05 HEX INVERTERS WITH OPEN-DRAIN OUTPUTS SCLS357H – MAY 1997 – REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 50% VCC 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74AHC05D ACTIVE SOIC D 14 SN74AHC05DBR ACTIVE SSOP DB SN74AHC05DBRE4 ACTIVE SSOP SN74AHC05DBRG4 ACTIVE SN74AHC05DE4 50 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC05DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC05DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC05DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC05DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC05N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74AHC05NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74AHC05PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC05PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC05PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC05PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC05PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC05PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74AHC05DBR Package Package Pins Type Drawing SSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74AHC05DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74AHC05PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AHC05DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74AHC05DR SOIC D 14 2500 367.0 367.0 38.0 SN74AHC05PWR TSSOP PW 14 2000 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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