SBOS230A – MARCH 2002 – REVISED JUNE 2002 FEATURES D DIGITALLY-CONTROLLED ANALOG VOLUME D D D D D D APPLICATIONS D AUDIO AMPLIFIERS D MIXING CONSOLES D MULTI–TRACK RECORDERS D BROADCAST STUDIO EQUIPMENT D MUSICAL INSTRUMENTS D EFFECTS PROCESSORS D A/V RECEIVERS D CAR AUDIO SYSTEMS CONTROL: Four Independent Audio Channels Serial Control Interface Zero Crossing Detection Mute Function WIDE GAIN AND ATTENUATION RANGE: +31.5dB to –95.5dB with 0.5dB Steps LOW NOISE AND DISTORTION: 120dB Dynamic Range 0.0004% THD+N at 1kHz (U–Grade) 0.0002% THD+N at 1kHz (A–Grade) NOISE-FREE LEVEL TRANSITIONS LOW INTERCHANNEL CROSSTALK: –130dBFS POWER SUPPLIES: ±5V Analog, +5V Digital AVAILABLE IN AN SOP-28 PACKAGE DESCRIPTION The PGA4311 is a high–performance, 4-channel audio volume control designed for professional and high-end consumer audio systems. Using high performance operational amplifier stages internal to the PGA4311 yields low noise and distortion, while providing the capability to drive 600Ω loads directly without buffering. The 3-wire serial control interface allows for connection to a wide variety of host controllers, in addition to support for daisy-chaining of multiple PGA4311 devices. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. !" # ! ! $ %&# ! ' & ' !# 1 www.ti.com Copyright 2002, Texas Instruments Incorporated www.ti.com SBOS230A – MARCH 2002 – REVISED JUNE 2002 ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage, VA+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V VA– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5.5V VD+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V VA+ to VD+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . < ± 0.3V Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . 0V to VA+, VA– Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to VD+ Operating Temperature Range . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . +300°C Package Temperature (IR reflow, 10s) . . . . . . . . . . . . . . . . . +235°C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PACKAGE–LEAD PACKAGE DESIGNATOR(1) OPERATING TEMPERATURE RANGE (U Grade) PGA4311 (U–Grade) SOP 28 SOP–28 DW 40°C to +85°C –40°C PGA4311 (A–Grade) (A Grade) SOP 28 SOP–28 DW –40°C 40°C to +85°C PRODUCT PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY PGA4311U PGA4311U Rails PGA4311U PGA4311U/1K Tape and Reel, 1000 PGA4311UA PGA4311UA Rails PGA4311UA PGA4311UA/1K Tape and Reel, 1000 (1) For the most current specifications and package information, refer to our web site at www. ti.com. ELECTRICAL CHARACTERISTICS At TA = +25°C, VA+ = +5V, VA– = –5V, VD+ = +5V, RL = 100kΩ, CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted. PGA4311U (U–Grade) PARAMETER CONDITIONS MIN TYP MAX PGA4311UA (A–Grade) MIN TYP MAX UNITS DC CHARACTERISTICS Step Size 0.5 0.5 dB ±0.05 ±0.05 dB ±0.05 ±0.05 dB Input Resistance 10 10 kΩ Input Capacitance 3 3 pF Gain Error Gain Setting = 31.5dB Gain Matching AC CHARACTERISTICS THD+N Dynamic Range VIN = 2Vrms, f = 1kHz VIN = AGND, Gain = 0dB Voltage Range, Input (without clipping) Interchannel Crosstalk 0.001 120 (VA–) + 1.25 Voltage Range, Output Output Noise 0.0004 116 (VA+) – 1.25 2.5 VIN = AGND, Gain = 0dB f = 1kHz 2.5 –130 VIN = AGND, Gain = 0dB 0.25 0.0002 116 0.0004 120 (VA–) + 1.25 (VA+) – 1.25 V 4 µVrms 2.5 4 2.5 % dB Vrms –130 dBFS OUTPUT BUFFER Offset Voltage 0.5 0.25 0.5 mV Load Capacitance Stability 100 100 pF Short–Circuit Current 50 50 mA Unity–Gain Bandwidth, Small Signal 10 10 MHz 2 www.ti.com SBOS230A – MARCH 2002 – REVISED JUNE 2002 ELECTRICAL CHARACTERISTICS (Cont.) At TA = +25°C, VA+ = +5V, VA– = –5V, VD+ = +5V, RL = 100kΩ, CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted. PGA4311U (U–Grade) PARAMETER CONDITIONS MIN TYP PGA4311UA (A–Grade) MAX MIN VD+ 0.8 +2.0 TYP MAX UNITS DIGITAL CHARACTERISTICS High–Level Input Voltage, VIH +2.0 Low–Level Input Voltage, VIL –0.3 High–Level Output Voltage, VOH IO = 200µA Low–Level Output Voltage, VOL IO = –3.2mA (VA+) – 1.0 VD+ 0.8 –0.3 (VD+) – 1.0 1 10 V V 0.4 Input Leakage Current V 1 0.4 V 10 µA 6.25 MHz SWITCHING CHARACTERISTICS Serial Clock (SCLK) Frequency Serial Clock (SCLK) Pulse Width LOW Serial Clock (SCLK) Pulse Width HIGH MUTE Pulse Width LOW fSCLK tPH 0 6.25 0 80 80 80 80 ns 2.0 2.0 ms tSDS tSDH 20 20 ns 20 20 ns tCSCR tCFCS 90 90 ns 35 35 ns tPL tMI ns Input Timing SDI Setup Time SDI Hold Time CS Falling to SCLK Rising SCLK Falling to CS Rising Output Timing CS LOW to SDO Active SCLK Falling to SDO Data Valid CS HIGH to SDO High Impedance tCSO tCFDO tCSZ 35 35 ns 60 60 ns 100 100 ns POWER SUPPLY Operating Voltage VA+ VA– +4.75 +5 +5.25 +4.75 +5 +5.25 V –4.75 –5 –5.25 –4.75 –5 –5.25 V +4.75 +5 +5.25 +4.75 +5 +5.25 V VA+ = +5V VA– = –5V 17 22 17 22 mA 19 24 19 24 mA VD+ = +5V 0.5 1.0 0.5 1.0 mA VD+ Quiescent Current IA+ IA– ID+ Power–Supply Rejection Ratio PSRR (250Hz) 100 100 dB TEMPERATURE RANGE Operating Range –40 +85 –40 +85 °C Storage Range –65 +150 –65 +150 °C 3 www.ti.com SBOS230A – MARCH 2002 – REVISED JUNE 2002 PIN CONFIGURATION Top View PIN ASSIGNMENTS SO PIN NAME FUNCTION 1 MUTE Mute Control Input (Active LOW) 2 AGND_1 Analog Ground, Channel 1 3 AIN_1 AGND_1 Analog Input, Channel 1 AOUT_1 VA– Analog Output, Channel 1 Analog Power Supply, +5V 8 VA+ AOUT_3 9 AGND_3 Analog Ground, Channel 3 10 AIN_3 AGND_3 Analog Input, Channel 3 4 5 6 7 11 12 Analog Power Supply, –5V Analog Output, Channel 3 Analog Ground, Channel 3 Digital Power Supply, +5V 13 VD+ SDI 14 CS Chip Select Input 15 SCLK Serial Clock Input 16 SDO Serial Data Output 17 DGND 18 AGND_4 Analog Ground, Channel 4 19 AIN_4 AGND_4 Analog Input, Channel 4 AOUT_4 VA+ Analog Output, Channel 4 Analog Power Supply, –5V 24 VA– AOUT_2 25 AGND_2 Analog Ground, Channel 2 26 Analog Input, Channel 2 27 AIN_2 AGND_2 28 ZCEN 20 21 22 23 4 Analog Ground, Channel 1 Serial Data Input Digital Ground Analog Ground, Channel 4 Analog Power Supply, +5V Analog Output, Channel 2 Analog Ground, Channel 2 Zero Crossing Enable (Active HIGH) www.ti.com SBOS230A – MARCH 2002 – REVISED JUNE 2002 TYPICAL CHARACTERISTICS At TA = +25°C, VA+ = +5V, VA– = –5V, VD+ = +5V, RL = 100kΩ, CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted. (NOTE: All plots taken with PGA4311 A–Grade.) 5 www.ti.com SBOS230A – MARCH 2002 – REVISED JUNE 2002 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VA+ = +5V, VA– = –5V, VD+ = +5V, RL = 100kΩ, CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted. (NOTE: All plots taken with PGA4311 A–Grade.) GENERAL DESCRIPTION POWER–UP STATE The PGA4311 is a four-channel audio volume control. It may be used in a wide array of professional and consumer audio equipment. The PGA4311 is fabricated in a sub-micron CMOS process. The heart of the PGA4311 is a resistor network, an analog switch array, and a high-performance op amp stage. The switches are used to select taps in the resistor network that, in turn, determine the gain of the amplifier stage. Switch selections are programmed using a serial control port. The serial port allows connection to a wide variety of host controllers. See Figure 1 for a functional block diagram of the PGA4311. On power up, “power-up reset” is activated for about 100ms during which the circuit is in hardware MUTE state and all internal flip-flops are reset. At the end of this period, the offset calibration is initiated without any external signals. Once this has been completed, the gain byte value for all channels are set to 00HEX, or the software MUTE condition. The gain will remain at this setting until the host controller programs new settings for for each channel via the serial control port. 6 www.ti.com SBOS230A – MARCH 2002 – REVISED JUNE 2002 Figure 1. PGA4311 Block Diagram. If during normal operation the power supply voltage drops below ±3.2V, the circuit enters a hardware MUTE state. A power-up sequence will be initiated if the power-supply voltage returns to greater than ±3.2V. ANALOG INPUTS AND OUTPUTS The PGA4311 includes four independent channels. Each channel has a corresponding input and output pin. The input and output pins are unbalanced, and referenced to analog ground. The input and output pins may swing within 1.25V of the analog power supplies, VA+ and VA–. Given VA+ = +5V and VA– = –5V, the maximum input or output voltage range is 7.5Vp-p. For optimal performance, it is best to drive the PGA4311 with a low source impedance. A source impedance of 600Ω or less is recommended. Source impedances up to 2kΩ will cause minimal degradation of THD+N. Please refer to the “THD+N vs Source Impedance” plot in the Typical Characteristics section of the datasheet. 7 www.ti.com SBOS230A – MARCH 2002 – REVISED JUNE 2002 SERIAL CONTROL PORT The serial control port is utilized to program the gain settings for the PGA4311. The serial control port includes three input pins and one output pin. The inputs include CS (pin 14), SDI (pin 13), and SCLK (pin 15). The sole output pin is SDO (pin 16). The CS pin functions as the chip select input. Data may be written to the PGA4311 only when CS is LOW. SDI is the serial data input pin. Control data is provided as a 32-bit word at the SDI pin, 8 bits each for each channel gain setting. Data is formatted as MSB first, straight binary code. SCLK is the serial clock input. Data is clocked into SDI on the rising edge of SCLK. SDO is the serial data output pin, and is used when daisy-chaining multiple PGA4311 devices. Daisy-chain operation is described in detail later in this section. SDO is a tri-state output, and assumes a high impedance state when CS is HIGH. Data appears at SDO on the falling edge of SCLK. The protocol for the serial control port is shown in Figure 2. See Figure 3 for detailed timing specifications for the serial control port. Gain Byte Format is MSB First, Straight Binary 0 is the Least Significant Bit of the Channel Gain Byte 7 is the Most Significant Bit of the Channel Gain Byte SDI is latched on the rising edge of SCLK. SDO transitions on the falling edge of SCLK. Figure 2. Serial Interface Protocol. 8 www.ti.com SBOS230A – MARCH 2002 – REVISED JUNE 2002 Figure 3. Serial Interface Timing Requirements. GAIN SETTINGS For N = 1 to 255: The gain for each channel is set by its corresponding 8-bit code, [7:0] (see Figure 2). The gain code data is straight binary format. If we let N equal the decimal equivalent of [7:0], then the following relationships exist for the gain settings: For N = 0: Mute Condition. The input multiplexer is connected to analog ground. Gain (dB) = 31.5 – [0.5 w (255 – N)] This results in a gain range of +31.5dB (with N = 255) to –95.5dB (with N = 1). Changes in gain setting may be made with or without zero crossing detection. The operation of the zero crossing detector and timeout circuitry is discussed later in this data sheet. 9 www.ti.com SBOS230A – MARCH 2002 – REVISED JUNE 2002 DAISY-CHAINING MULTIPLE PGA4311 DEVICES In order to reduce the number of control signals required to support multiple PGA4311 devices on a printed circuit board, the serial control port supports daisy-chaining of multiple PGA4311 devices. Figure 4 shows the connection requirements for daisy-chain operation. This arrangement allows a 3-wire serial interface to control many PGA4311 devices. As shown in Figure 4, the SDO pin from device #1 is connected to the SDI input of device #2, and is repeated for additional devices. This in turn forms a large shift register, in which gain data may be written for all PGA4311s connected to the serial bus. The length of the shift register is 32 • N bits, where N is equal to the number of PGA4311 devices included in the chain. The CS input must remain LOW for 32 • N SCLK periods, where N is the number of devices connected in the chain, in order to allow enough SCLK cycles to load all devices. Figure 4. Daisy-Chaining Multiple PGA4311 Devices. 10 ZERO CROSSING DETECTION The PGA4311 includes a zero crossing detection function that can provide for noise-free level transitions. The concept is to change gain settings on a zero crossing of the input signal, thus minimizing audible glitches. This function is enabled or disabled using the ZCEN input. When ZCEN is LOW, zero crossing detection is disabled. When ZCEN is HIGH, zero crossing detection will be enabled. The zero crossing detection takes effect with a change in gain setting for a corresponding channel. The new gain setting will not be implemented until either positive slope zero crossing is detected or a time-out period of 16ms has elapsed. In the case of a time-out, the new gain setting takes effect with no attempt to minimize audible artifacts. www.ti.com SBOS230A – MARCH 2002 – REVISED JUNE 2002 MUTE FUNCTION APPLICATIONS INFORMATION Muting can be achieved by either hardware or software control. Hardware muting is accomplished via the MUTE input, and software muting by loading all zeroes into the volume control register. MUTE disconnects the internal buffer amplifiers from the output pins and terminates the outputs with 10kΩ resistors to ground. The mute is activated with a zero crossing detection (independent of the zero cross enable status) or an 16ms time-out to eliminate any audible “clicks” or “pops”. MUTE also initiates an internal offset calibration. A software mute is implemented by loading all zeroes into the volume control register. The internal amplifier is set to unity gain with the amplifier input connected to AGND. This section includes additional information that is pertinent to designing the PGA4311 into an end application. RECOMMENDED CONNECTION DIAGRAM Figure 5 depicts the recommended connections for the PGA4311. Power-supply bypass capacitors should be placed as close to the PGA4311 package as physically possible. PRINTED CIRCUIT BOARD (PCB) LAYOUT GUIDELINES It is recommended that the ground planes for the digital and analog sections of the PCB be separate from one another. The planes should be connected at a single point. See Figure 6 for the recommended PCB floor plan for the PGA4311. Figure 5. Recommended Connection Diagram. 11 www.ti.com SBOS230A – MARCH 2002 – REVISED JUNE 2002 Figure 6. Typical PCB Layout Floor Plan. 12 www.ti.com SBOS230A – MARCH 2002 – REVISED JUNE 2002 PACKAGE DRAWING 13 PACKAGE OPTION ADDENDUM www.ti.com 8-Jan-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty PGA4311U ACTIVE SOIC DW 28 PGA4311U/1K ACTIVE SOIC DW PGA4311U/1KG4 ACTIVE SOIC 28 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PGA4311U2 PREVIEW SOIC DW 28 1 TBD Call TI PGA4311UA ACTIVE SOIC DW 28 28 Green (RoHS & no Sb/Br) CU NIPDAU Call TI Level-2-260C-1 YEAR PGA4311UA/1K ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PGA4311UA/1KG4 ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PGA4311UA1 PREVIEW SOIC DW 28 1 TBD Call TI PGA4311UAG4 ACTIVE SOIC DW 28 28 Green (RoHS & no Sb/Br) CU NIPDAU Call TI Level-2-260C-1 YEAR PGA4311UG4 ACTIVE SOIC DW 28 28 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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