SWRS023B − MAY 2004 − REVISED MARCH 2005 D Single-Chip RF Transmitter for 315-MHz, D D D D D D D Programmable Brownout Detector D Integrated Data Bit Synchronizer and Baud 433-MHz, 868-MHz, and 915-MHz Industrial, Scientific, and Medical (ISM) Bands 2.2-V to 3.6-V Operation Low Power Consumption FSK/OOK Operation Integer-N Synthesizer With Fully Integrated Voltage Controlled Oscillator (VCO) On-Chip Reference Oscillator and Phase-Locked Loop (PLL) Power Amplifier With 8-dBm Typical Output Power Rate Selection D Flexible 3-Wire Serial Interface D Minimal Number of External Components D D D D Required 24-Pin Plastic Thin-Shrink Small Outline Package (TSSOP) Programmable XTAL Trimming Lock Detect Indicator Companion Transmitter to the TRF6903 Transceiver PW PACKAGE (TOP VIEW) TX_DATA MODE STDBY PA_OUT PA_GND1 PA_VCC PA_GND2 VCO_PRE_VCC VCO_GND VCO_CORE_VCC VCO_BYPASS VCO_TUNE 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CLOCK DATA STROBE GND XTAL_SW XTAL DGND DVDD DET_LD_DCLK CP_GND CP_OUT CP_VCC These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the gates. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2005, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SWRS023B − MAY 2004 − REVISED MARCH 2005 description The TRF4903 single-chip solution is an integrated circuit intended for use as a low-cost multiband FSK or OOK transmitter to establish a frequency-programmable, half-duplex RF link. The multichannel transmitter is intended for digital (FSK, OOK) modulated applications in the North American and European 315-MHz, 433-MHz, 868-MHz, and 915-MHz ISM bands. The single-chip operates down to 2.2 V and is designed for low power consumption. The synthesizer has a typical channel spacing of better than 200 kHz and features a fully-integrated VCO. Only the PLL loop filter is external to the device. Two fully-programmable operation modes, Mode0 and Mode1, allow extremely fast switching between two preprogrammed settings (for example, TX_frequency_0/TX_frequency_1; …) without reprogramming the device. ISM band standards Europe has assigned an unlicensed frequency band of 868 MHz to 870 MHz. This band is specifically defined for short range devices with duty cycles from 0.1% to 100% in several subbands. The new European frequency band, due to the duty cycle assignment, allows a reliable RF link and makes many new applications possible. The North American unlicensed ISM band covers 902 MHz to 928 MHz (center frequency of 915 MHz) and is suitable for short range RF links. transmitter The transmitter consists of an integrated VCO and tank circuit, a complete integer-N synthesizer, and a power amplifier. The dividers, prescaler, and reference oscillator require only the addition of an external crystal and a loop filter to provide a complete PLL with a typical frequency resolution of better than 200 kHz. Since the typical RF output power is approximately 8 dBm, no additional external RF power amplifier is necessary in most applications. Four attenuation setting for the power amplifier are offered. This feature allows the user to fine tune the amplifier for optimal output power. baseband interface The TRF4903 can easily be interfaced to a baseband processor such as the Texas Instruments MSP430 ultralow-power microcontroller (see Figure 1). The TRF4903 serial control registers are programmed by the MSP430 and the MSP430 performs baseband operations in the software. A synchronized data clock, programmable for most common data rates, is provided by the TRF4903. During transmit, the data clock can be used to clock the transmit data from the microcontroller to the TRF4903 at predefined data rates. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SWRS023B − MAY 2004 − REVISED MARCH 2005 Antenna Microcontroller Section RF Section Transmit Data TX_DATA Brownout Detector, Lock Detect, Data Clock DET_LD_DCLK PA_OUT RF Out TRF4903 Transmitter + Discretes Mode Select Standby MODE STDBY MSP430 Family µC Serial Control Data DATA Serial Control Clock CLOCK Serial Control Strobe STROBE Figure 1. System Block Diagram for Interfacing to the MSP430 Microcontroller functional block diagram 16 DET_LD_DCLK Bit Synchronizer and Data Clock MUX Band-gap 8 /ACounter Brownout Detector 24 23 /Div. CTRL 6 /N Prescaler Serial Interface 22 3 2 /BCounter 32/33 CLOCK DATA STROBE STDBY MODE Lock Detect PA Output Divider 1, 2, 3 PFD CPs VCO VCO_TUNE 12 14 CP_OUT /Ref 2...255 1 XTAL Switch 19 XTAL_SW 4 XTAL PA_OUT TX_DATA 20 Loop Filter POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SWRS023B − MAY 2004 − REVISED MARCH 2005 Terminal Functions TERMINAL NAME NO. I/O I DESCRIPTION CLOCK 24 Serial interface clock signal input CP_GND 15 CP_OUT 14 CP_VCC 13 DATA 23 I Serial interface data signal input DET_LD_DCLK 16 O Brownout detector (active high), PLL lock detect (active high), and data clock multiplexed output DGND 18 Digital and XTAL oscillator ground DVDD 17 Digital and XTAL oscillator power supply GND 21 MODE 2 PA_GND1 5 Power amplifier ground PA_GND2 7 Power amplifier ground PA_OUT 4 PA_VCC 6 STDBY 3 I Standby input signal; active low STROBE 22 I Serial interface strobe signal TX_DATA 1 I Buffered TX data input VCO_BYPASS 11 I VCO_GND 9 VCO_TUNE 12 VCO_CORE_VCC 10 VCO core supply voltage VCO_PRE_VCC 8 Divider and prescaler supply voltage XTAL 19 I/O XTAL_SW 20 I Charge pump ground O Charge pump output Charge pump supply voltage Substrate ground I O Mode select input Power amplifier output Power amplifier supply voltage VCO bypass; connect to ground through a 100-pF capacitor VCO ground I Tuning voltage for the integrated VCO Connection to an external crystal reference Connection to external capacitor, which sets the frequency deviation of the transmitted signal absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 to 4.5 Vdc Input voltage, logic signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 to 4.5 Vdc Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C ESD protection, human body model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog supply voltage 2.2 3.6 V Digital supply voltage 2.2 3.6 V Operating free-air temperature −40 85 °C 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SWRS023B − MAY 2004 − REVISED MARCH 2005 dc electrical characteristics, VCC = 2.7 V, TA = 25°C supply current PARAMETER TEST CONDITIONS Standby current TX current, PA disabled. PLL, VCO, dividers, and reference active TX current‡, PA enabled. PLL, VCO, dividers, reference, and data clock active TYP MAX STDBY low MIN 0.6 4 315-MHz band 12 15 433-MHz band 11 14 868-MHz band 10 12 915-MHz band 10 12 0-dB attenuation 315-MHz band 37 43 10-dB attenuation 315-MHz band 30 20-dB attenuation 315-MHz band 29 0-dB attenuation 433-MHz band 36 10-dB attenuation 433-MHz band 29 20-dB attenuation 433-MHz band 28 0-dB attenuation 868-MHz band 35 10-dB attenuation 868-MHz band 28 20-dB attenuation 868-MHz band 27 0-dB attenuation 915-MHz band 35 10-dB attenuation 915-MHz band 28 20-dB attenuation 915-MHz band 27 UNIT µA mA 42 40 mA 40 ‡ The TX current consumption is dependent upon the external PA matching circuit. The matching network is normally designed to achieve the highest output power at the 0-dB attenuation setting. Changing the external matching components to optimize the output power for other attenuation settings alters the typical current consumption from the typical values noted. digital interface PARAMETER VIH VIL High-level input voltage VOH VOL High-level output voltage TEST CONDITIONS MIN TYP VDD−0.4 0 Low-level input voltage IOH = 0.5 mA IOL = 0.5 mA Low-level output voltage MAX VDD 0.4 VDD−0.4 V V V 0.4 Digital input leakage current UNIT V µA <0.01 VCO/output divider PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency range: 315-MHz band Low-side injection, A<1:0> = 11 304 315 316 MHz Frequency range: 433-MHz band High-side injection, A<1:0> = 10 430 433 450 MHz Frequency range: 868-MHz band High-side injection, A<1:0> = 01 868 869 870 MHz Frequency range: 915-MHz band Low-side injection, A<1:0> = 01 902 915 928 MHz Closed loop phase noise Frequency offset = 50 kHz −77 Frequency offset = 200 kHz −90 Tuning voltage 0.1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 dBc/Hz VCC at terminal 11 V 5 SWRS023B − MAY 2004 − REVISED MARCH 2005 ac electrical characteristics, VCC = 2.7 V, TA = 25°C (continued) impedances and loads PARAMETER TEST CONDITIONS PA_OUT MIN TYP MAX UNIT See Figure 6 transmitter (XTAL, PLL, VCO, and PA), 315-MHz band PARAMETER TEST CONDITIONS TX frequency range A<1:0> = 11 MIN TYP MAX UNIT 304 315 316 MHz 0-dB attenuation Output power† 8 10-dB attenuation −2 20-dB attenuation −12 Disabled, B<3> = 0 −80 dBm Second harmonic −25 dBc Third harmonic −30 dBc DCLK spurious at fC ± fDCLKw DCLK active: E<15> = 1, E<12:11> = 01 −28 dBc Frequency deviation‡ FSK ±32 kHz Power ON-OFF ratio OOK, 0-dB mode 75 dB FSK 64 OOK 32 Maximum data rate (NRZ) kbit/s † Matched to 50 Ω using external matching network. ‡ Dependent upon external circuitry. § This spur is only present if DCLK is active. The resulting spur is within modulation (OOK or FSK) bandwidth and is considered a modulation product. Within the authorized bands, this spur does not violate FCC or ETSI regulatory compliance. transmitter (XTAL, PLL, VCO, and PA), 433-MHz band PARAMETER TEST CONDITIONS TX frequency range A<1:0> = 10 Output power† MIN TYP MAX UNIT 430 433 450 MHz 0-dB attenuation 8 10-dB attenuation −2 20-dB attenuation −12 Disabled, B<3> = 0 −80 Second harmonic Third harmonic dBm −25 dBc −30 dBc DCLK spurious at fC ± fDCLKw DCLK active: E<15> = 1, E<12:11> = 01 −28 dBc Frequency deviation‡ FSK ±32 kHz Power ON-OFF ratio OOK, 0-dB mode 75 dB FSK 64 OOK 32 Maximum data rate (NRZ) kbit/s † Matched to 50 Ω using external matching network. ‡ Dependent upon external circuitry. § This spur is only present if DCLK is active. The resulting spur is within modulation (OOK or FSK) bandwidth and is considered a modulation product. Within the authorized bands, this spur does not violate FCC or ETSI regulatory compliance. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SWRS023B − MAY 2004 − REVISED MARCH 2005 ac electrical characteristics, VCC = 2.7 V, TA = 25°C (continued) transmitter (XTAL, PLL, VCO, and PA), 868-MHz band PARAMETER TEST CONDITIONS TX frequency range A<1:0> = 11 Output power† MIN TYP MAX UNIT 868 869 870 MHz 0-dB attenuation 8 10-dB attenuation −2 20-dB attenuation −12 Disabled, B<3> = 0 −80 Second harmonic Third harmonic dBm −25 dBc −30 dBc −28 dBc DCLK spurious at fC ± fDCLKw DCLK active: E<15> = 1, E<12:11> = 01 Frequency deviation‡ FSK 32 kHz Power ON-OFF ratio OOK, 0-dB mode 75 dB FSK 64 OOK 32 Maximum data rate (NRZ) kbit/s † Matched to 50 Ω using external matching network. ‡ Dependent upon external circuitry. § This spur is only present if DCLK is active. The resulting spur is within modulation (OOK or FSK) bandwidth and is considered a modulation product. Within the authorized bands, this spur does not violate FCC or ETSI regulatory compliance. transmitter (XTAL, PLL, VCO, and PA), 915-MHz band PARAMETER TEST CONDITIONS TX frequency range A<1:0> = 11 0-dB attenuation Output power† MIN TYP MAX UNIT 902 915 928 MHz 8 10-dB attenuation −2 20-dB attenuation −12 Disabled, B<3> = 0 −80 dBm Second harmonic −25 dBc Third harmonic −30 dBc −28 dBc DCLK spurious at fC ± fDCLKw DCLK active: E<15> = 1, E<12:11> = 01 Frequency deviation‡ FSK 32 kHz Power ON-OFF ratio OOK, 0-dB mode 75 dB FSK 64 OOK 32 Maximum data rate (NRZ) kbit/s † Matched to 50 Ω using external matching network. ‡ Dependent upon external circuitry. § This spur is only present if DCLK is active. The resulting spur is within modulation (OOK or FSK) bandwidth and is considered a modulation product. Within the authorized bands, this spur does not violate FCC or ETSI regulatory compliance. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SWRS023B − MAY 2004 − REVISED MARCH 2005 ac electrical characteristics, VCC = 2.7 V, TA = 25°C (continued) XTAL PARAMETER TEST CONDITIONS MIN Frequency range TYP 9.5 MAX UNIT 20 MHz MAX UNIT brownout detector PARAMETER TEST CONDITIONS Voltage threshold, Vdet MIN Set by B<2:1> TYP 2.2 2.8 Voltage steps (∆V) 200 Number of steps V mV 4 Output level Connected to typical input port of microcontroller CMOS timing data for serial interface PARAMETER MIN TYP MAX UNIT 20 MHz f(CLOCK) tw(CLKHI) Clock frequency Clock high-time pulse width, clock high 20 ns tw(CLKLO) tsu(D) Clock low-time pulse width, clock low 20 ns 0 ns th(D) td(CLKLO) Hold time, data valid after CLOCK ↑ 10 ns Delay time of CLOCK low before STROBE high 20 ns tw(STROBEHI) tw(STROBELO) STROBE high-time pulse width, STROBE high 20 ns STROBE low-time pulse width, STROBE low 20 ns Setup time, data valid before CLOCK↑ Data Valid DATA Data Change MSB MSB LSB t su(D) t h(D) t w(CLKHI) t d(CLKLO) Start of Next Word CLOCK t w(STROBEHI) t w(CLKLO) STROBE Clock Disabled Shift in Data Clock Enabled Note: Most significant bit (MSB) clocked in first to the synthesizer. Figure 2. Timing Data for Serial Interface 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 −V H −V L tw(STROBELOW) tr tf −V H −V L Store Data Strobe Enabled −V H −V L SWRS023B − MAY 2004 − REVISED MARCH 2005 timing data for DCLK and TX_DATA tsu(TX) th(TX) PARAMETER MIN Setup time, TX_DATA valid before DCLK ↑ 100 ns Hold time, TX_DATA valid after DCLK ↑ 100 ns Transmit tsu(TX) TYP MAX UNIT th(TX) TX_DATA Input DCLK Output 1 TSK = fc NOTE: TX_DATA is latched at the rising edge of DCLK. Figure 3. Timing Data for DCLK and TX_DATA If transmit capture mode is selected (by setting bit 15 in word E), the data transitions (high-to-low or low-to-high) on the TXDATA pin is timed to coincide with the falling edge of DCLK. Any microcontroller using the TRF6903 can then latch TXDATA on the rising edge of DCLK. For more details, see the data clock section. detailed description bit synchronizer and data clock When enabled, the integrated bit synchronizer and data clock circuitry provide as an output at terminal 16, DET_LD_DCLK, a data clock based on a programmable bit rate. The bit rate is programmable via variables D1, D2, and D3 and is always relative to the master clock (XTAL) frequency, Fx. Table 1 shows common bit rates (kbps) vs selected crystal frequencies (MHz) and the respective settings of D1, D2, and D3. The preprogrammed bit rate can be calculated based on the following equation: Bit rate (kbps) + crystal frequency (kHz) + D1 D2 D3 D1 Fx D2 D3 + f c (kHz) where: D1 = 1, 5, 6, or 8 D2 = 1, 2, 4, 8, 16, 32, 64, or 128 D3 = 15 or 16 The data clock circuit is designed to reset/clear internally with no user action required. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SWRS023B − MAY 2004 − REVISED MARCH 2005 detailed description (continued) Table 1. Common Bit Rates, Corresponding Crystal Frequencies, and Values of D1, D2, and D3 D1, D2, AND D3 MULTIPLIERS FOR COMMON CRYSTAL VALUES (CRYSTAL FREQUENCIES IN MHZ) BIT RATE (kbps) 9.8304 0.6 8x128x16 12.288 0.9 14.7456 15.72864 16.384 19.6608 8x128x16 1 6x128x16 1.024 5x128x15 1.2 8x64x16 8x128x16 8x128x15 5x128x16 1.8 6x128x16 8x128x16 8x64x16 2 6x64x16 2.048 5x64x15 2.4 8x32x16 8x64x16 8x64x15 5x64x16 3.6 5x128x15 6x64x16 8x64x16 8x32x16 4 6x32x16 4.096 5x32x15 4.8 8x16x16 8x32x16 8x32x15 5x32x16 7.2 5x64x15 6x32x16 8x32x16 8x16x16 8 6x16x16 8.192 5x16x15 9.6 8x8x16 8x16x16 8x16x15 5x16x16 14.4 5x32x15 6x16x16 8x16x16 8x8x16 16 6x8x16 16.384 5x8x15 19.2 8x4x16 8x8x16 8x8x15 5x8x16 28.8 5x16x15 6x8x16 8x8x16 8x4x16 32 6x4x16 32.768 5x4x15 38.4 8x2x16 8x4x16 8x4x15 5x4x16 57.6 5x8x15 6x4 x16 8x4x16 8x2x16 64 6x2x16 65.536 5x2x15 76.8 8x1x16 8x2x16 8x2x15 5x2x16 115.2 5x4x15 6x2x16 8x2x16 8x1x16 128 6x1x16 8x1x16 main divider The main divider is composed of a 5-bit A-counter and a 9-bit B-counter and a prescaler. The A-counter controls the divider ratio of the prescaler, which divides the VCO signal by either 33 or 32. The prescaler divides by 33 until the A-counter reaches its terminal count and then divides by 32 until the B-counter reaches terminal count, whereupon both counters reset and the cycle repeats. The total divide-by-N operation is related to the 32/33 prescaler by: NTOTAL = 33 x A + 32 x (B – A) where 0 ≤ A ≤ 31 and 31 ≤ B ≤ 511 or, NTOTAL = A + 32B Thus, the N-divider has a range of 992 ≤ NTOTAL ≤ 16383 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SWRS023B − MAY 2004 − REVISED MARCH 2005 detailed description (continued) PLL The phase-locked loop is the radio frequency synthesizer for the TRF4903. It is used to generate the transmit signal and as the local oscillator for the receive mixer. The signal (FX) from a reference crystal oscillator (XO) is divided by an integer factor R down to FR. The minimum frequency resolution, and thus, the minimum channel spacing, is FR. FR = FX ÷ R where 1 ≤ R ≤ 256 The phase-locked loop is an integer-N design. The voltage-controlled oscillator (VCO) signal is divided by an integer factor N to get a frequency at the phase detector input. FPD = FVCO ÷ N The phase detector compares the divided VCO signal to the divided crystal frequency and implements an error signal from two charge pumps. The error signal corrects the VCO output to the desired frequency. As is in any integer-N PLLs, the VCO output has spurs at integer multiples of the reference frequency (nFR). In applications requiring contiguous frequency channels, the reference frequency is often chosen to be equal to the channel spacing, thus, channel spacing = FR = FX ÷ R. When enabled and when the PLL is locked, the DET_LD_DCLK terminal is high. With the addition of an output divider for multiband operation, the actual output frequency, Fout, is given by: F F F out + VCO + X P R N+F R P N + A ) 32B P P F R where FR = FPD under locked conditions. The actual minimum channel spacing is: F BR R+ X P P F where P = 1, 2, 3 and is set by A<1:0>. oscillator circuit and reference divider The reference divider reduces the frequency of the external crystal (FX) by an 8-bit programmable integer divisor, R, to an internal reference frequency (FR) used for the phase-locked loop. The choice of internal reference frequency also has implications for lock time, maximum data rate, noise floor, and loop-filter design. The crystal frequency can be tuned using the F word to control internal trimming capacitors, which are placed in parallel with the crystal. These offset a small frequency error in the crystal. In an FSK application, an additional capacitor is placed in parallel (through terminal 19) with the external capacitor that is connected in series with the crystal, thus, changing the load capacitance as the transmit data switch (TX_DATA, terminal 1) is toggled. The change in load capacitance pulls the crystal off-frequency by the total frequency deviation. Hence, the 2-FSK frequency, set by the level of TX_DATA and the external capacitor, can be represented as follows: ƒ out1 + TX_DATA Low (XTAL switch closed) ƒ out2 + TX_DATA High (XTAL switch open) Note that the frequencies ƒout1 and ƒout2 are centered about the frequency ƒcenter = (ƒout1 + ƒout2)/2. When transmitting FSK, ƒcenter is considered to be the effective carrier frequency and any receiver local oscillator (LO) should be set to the same ƒcenter frequency ± the receiver’s IF frequency (ƒIF) for proper reception and demodulation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SWRS023B − MAY 2004 − REVISED MARCH 2005 oscillator circuit and reference divider (continued) For the case of high-side injection, the receiver LO would be set to ƒLO = ƒcenter + ƒIF. Using high-side injection, the received data would be inverted from the transmitted data applied at terminal 1, TX_DATA. Conversely, for low-side injection, the receiver LO would be set to ƒLO = ƒcenter − ƒIF. Using low-side injection, the received data would be the same as the transmitted data. 20 VCC 19 Fx ÷R Reference Divider 2...255 Crystal Oscillator Circuit FR FPD External Crystal PhaseFrequency Detector 14 External Loop Filter 12 VCO External Cap for FSK Charge Pumps ÷N Main Divider A, B Counters 32/33 992 ≤ N ≤ 16383 Fvco Output Divider P = 1, 2, 3 Fout Figure 4. TRF4903 PLL and Output Divider phase detector and charge pumps The phase detector is a phase-frequency design. The phase-frequency detector gain is given by: KP = I(CP)/2π where, I(CP) is the peak charge pump current. The peak charge pump current is programmable with A<3:2> in three steps: 250 µA, 500 µA, and 1000 µA. loop filter The loop filter must be carefully chosen for proper operation of the TRF4903. The loop filter is typically a secondor third-order passive design, and in FSK operation should have a bandwidth wide enough to allow the PLL to relock quickly as the external crystal frequency is pulled off-center during modulation. The loop filter should also be wider than the data modulation rate. These requirements should be balanced with making the loop narrow enough in consideration of the reference frequency. In OOK the VCO frequency is not changed during data modulation, so the filter bandwidth may be narrower than the modulation bandwidth. Filters can be calculated using standard formulas in reference literature. Some third-order filter examples are shown in Table 2. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SWRS023B − MAY 2004 − REVISED MARCH 2005 loop filter (continued) F(s) + 1 C3R3 s) 1 C3R3 1 ) sC2R2 s(C1 ) C2 ) sC1C2R2) R3 lcp CP_OUT Vtune 12 C3 14 C1 C2 VCO_TUNE R2 VCO_VCC External-Loop Filter Figure 5. Third-Order Loop Filter and Transfer Function Table 2. Loop Filter Component Values For Various Data Rates at a Reference Frequency of 409.6 kHz, 0.5-mA Charge Pump Current Bit rate − kbps Data rate − kHz Manchester coding 1.024 2.048 4.096 8.192 16.384 19.2 32.768 65.536 NRZ coding 2.048 4.096 8.192 16.384 32.768 38.4 65.536 131.072 Fundamental freq of BB 1.024 2.048 4.096 8.192 16.384 19.2 32.768 65.536 0.01 C1, nF 47 12 2.7 0.68 0.18 0.12 0.043 C2, nF 1800 430 100 27 6.8 5.1 1.8 0.47 C3, nF 27 6.8 1.5 0.39 0.1 0.075 0.027 0.0068 R2, kΩ 0.39 0.75 1.5 3 5.7 6.8 12 24 R3, kΩ 0.75 1.5 3 5.7 12 15 22 47 −3−dB bandwidth, kHz (approximate) 1.28 2.56 5.12 10.24 20.48 24 40.96 81.92 Loop filter component (selected to nearest standard value) VCO The voltage-controlled oscillator (VCO) produces an RF output signal with a frequency that is dependent upon the dc-tuning voltage at terminal 12. The tank circuit is passive and has integrated varactor diodes and inductors. The open-loop VCO gain is approximately 100 MHz/V. A <1:0> is used to set the output divider ratio for operation within the 315-MHz, 433-MHz, 868-MHz, or 915-MHz bands. When the STDBY terminal is high, the reference, PLL, VCO, and dividers are powered up. When STDBY is low, these blocks are powered down. power amplifier The power amplifier has three programmable attenuation states as determined by A<7:6> and B<7:6>: full power (0-dB attenuation), 10-dB attenuation, and 20-dB attenuation. This adjustment feature allows the user to fine-tune the device for optimal output power. The power amplifier can be enabled/disabled during transmit by bit B<3>, PAED. During ASK or OOK operation, the TX_DATA signal turns the output stage of the power amplifier on and off according to the transmit data incident at terminal 1. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SWRS023B − MAY 2004 − REVISED MARCH 2005 power amplifier (continued) ↑1 U CH1 S22 1 0.5 2 5 CAL OFS 0 0.2 0.5 1 2 5 10 CPL −5 FIL 1k −0.5 −2 −1 START 300 MHz STOP 1000 MHz Figure 6. Typical PA Output Impedance (S22) at Device Terminal PA_OUT brownout detector The brownout detector provides an output voltage to indicate a low supply voltage. This may be used to signal the need to change transmit power to conserve battery life, or for system power down. The brownout detector threshold is set with the B word. Four different thresholds are available. serial control interface The TRF4903 is controlled through a serial interface; there are five 24-bit control words (A, B, C, D, E) which set the device state. The A and B words are almost identical, and provide configuration settings for two modes, designated 0 and 1, which are commonly used to configure the transmit states. Two transmit states can then be rapidly selected using MODE (terminal 2). The C word sets the reference dividers, the power amplifier bias, and contains various reset bits. The E word contains the bit-rate select, data clock control bits, and the power amplifier bias control registers. The D word is used to trim the external crystal frequency and tune the demodulator. The register address is the composite of bits 23, 22, 1, and 0 of the 24 bits written to the serial interface. For some words, certain bits of the address are don’t cares and are noted as XX. This flexible addressing scheme allows compatibility with the TRF6901/TRF6903 and because of this flexibility, the data length of each register varies from 15 bits to 22 bits. Normal (write) operation of the serial interface is to clock in 24 bits through the CLOCK and DATA terminals. DATA values are clocked into the 24-bit serial interface shift register on the rising edge of CLOCK. The 24-bit value is decoded and written into the appropriate data register on the rising edge of STROBE. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SWRS023B − MAY 2004 − REVISED MARCH 2005 PRINCIPLES OF OPERATION register description ) ! ! $%&' ((& !) . . . ((&/% . /*12*3 . */ !$ 0/ ! " # *++, " )-, NOTE: r = reserved. All reserved bits should be set low (0) during normal operation. NOTE: All bits indicated as 1 should be set high (1) during normal operation. NOTE: All bits indicated as 0 should be set low (0) during normal operation. ADDRESS LOCATION NO. OF BITS DESCRIPTION DEFAULT VALUE 00xx 21 : 17 5 Main A divider coefficient (Mode 0) 00000 00xx 16 : 8 9 Main B divider coefficient (Mode 0) 001110000 00xx 7:6 2 Controls the PA attenuation (Mode 0) 10 00xx 5 1 Enables transmit path (Mode 0); set to 1 1 00xx 3:2 2 Controls charge pump peak current 00 00xx 1:0 2 Output divider coefficient; band select 10 01xx 21 : 17 5 Main A divider coefficient (Mode 1) 00000 01xx 16 : 8 9 Main B divider coefficient (Mode 1) 001110000 01xx 7:6 2 Controls the PA attenuation (Mode 1) 10 01xx 5 1 Enables transmit path (Mode 1); set to 1 1 01xx 4 1 Controls modulation scheme (FSK or OOK) 0 01xx 3 1 Enables or disables the power amplifier 0 01xx 2:1 2 Sets threshold for the brownout detector 00 01xx 0 1 Enables brownout detector 0 1000 21 : 14 8 Reference divider coefficient 01000000 1001 21 : 20 2 Bit-rate divider D1 11 1001 19 : 17 3 Bit-rate divider D2 010 1001 16 1 Bit-rate divider D3 0 1001 15 1 Transmit capture mode select 0 1001 12 : 11 2 Determines the function of terminal 16, DET_LD_DCLK 00 11x0 20 1 Controls the position of the XTAL switch during OOK operation 0 11x0 18 : 16 3 Tunes the XTAL frequency by using an internal capacitor bank 000 11x0 15 1 PFD reset 1 NOTE: x = don’t care POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SWRS023B − MAY 2004 − REVISED MARCH 2005 PRINCIPLES OF OPERATION At power on/startup, all of the TRF4903 register contents are as per the default values. Address 00XX (A-Word) Word A is a 22-bit data register comprising five fields. The main A-divider coefficient (mode 0), A<21:17>, is the 5-bit divider ratio of the A counter when the MODE terminal is low. The main B-divider coefficient (mode 0), A<16:8>, is the 9-bit value of the B counter when the MODE terminal is low. A <21:17> and A <16:8> are unsigned binary values. PA0, A<7:6>, is the 2-bit PA attenuation setting when the MODE terminal is low. CP Acc., A<3:2>, sets the charge pump current. BND, A<1:0>, sets the output divider, which in turn determines the band of operation. Terminal 2 (MODE) selects bits A< 21 : 5 > if low, or B< 21 : 5 > if high. Main divider A< 21 : 17 >: 5-bit value for divider ratio of the A counter Main divider A< 16 : 8 >: 9-bit value for divider ratio of the B counter PA attenuation A< 7 : 6 >: 2 bits for setting the PA attenuation A< 7 : 6 > PA ATTENUATION 00 0 dB 01 10 dB 10 20 dB 11 Not defined A<5 >: 1-bit; set high A<3: 2 >: 2 bits for setting the charge pump current A<3 : 2 > CP CURRENT 00 0.5 mA 01 1 mA 10 0.25 mA 11 Not defined A<1:0>: 2-bit value to set the output divider and thus select the band of operation. A<1:0 > OUTPUT DIVIDER RATIO, P BAND OF OPERATION 00 3 315 MHz 01 2 433 MHz 10 1 868 MHz or 915 MHz 11 1 868 MHz or 915 MHz Bit A<4> is reserved and should be set to 0. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SWRS023B − MAY 2004 − REVISED MARCH 2005 PRINCIPLES OF OPERATION Address 01XX (B-Word) Word B is a 22-bit data register comprising seven fields. The main A-divider coefficient (mode 1), B<21:17>, is the 5-bit divider ratio of the A counter when the MODE terminal is high. The main B-divider coefficient (mode 1), B<16:8>, is the 9-bit value of the B counter when the MODE terminal is high. B<21:17> and B<16:8> are unsigned binary values. PA1, B<7:6>, is the 2-bit PA attenuation setting when the MODE terminal is high. FSK/OOK, B<4>, sets the modulation scheme for TX. Bit B<3> enables/disables the power amplifier while in transmit mode. The detector threshold, B<2:1>, is the 2-bit setting for the threshold voltage of the brownout detector. Det. Enable, B<0>, is the brownout detector enable flag. Terminal 21 (MODE) selects bits A< 21 : 5 > if low, or B< 21 : 5 > if high. Main divider B< 21 : 17 >: 5-bit value for divider ratio of the A-counter Main divider B< 16 : 8 >: 9-bit value for divider ratio of the B-counter PA attenuation B< 7 : 6 >: 2 bits for setting the PA attenuation B< 7 : 6 > PA ATTENUATION 00 0 dB 01 10 dB 10 20 dB 11 Not defined B<5 >: 1-bit; set high B<4 > 1-bit modulation select B< 4 > TX MODULATION 0 OOK 1 FSK B<3 >: 1-bit PA enable/disable B< 3 > PA ENABLE/DISABLE 0 PA disabled 1 PA enabled B<2 : 1 >: 2-bit value to set the threshold voltage for the brownout detector B< 2 : 1 > THRESHOLD VOLTAGE 00 2.2 V 01 2.4 V 10 2.6 V 11 2.8 V B<0 >: 1 bit to enable brownout detector B< 0 > BROWNOUT DETECTOR 0 Off 1 On POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 SWRS023B − MAY 2004 − REVISED MARCH 2005 PRINCIPLES OF OPERATION Address 1000 (C-Word) Word C is a 20-bit data register comprising four fields. The reference divider coefficient, C<21:14>, is the 8-bit divider ratio of the reference divider. The allowable reference divider range is 2 (C <21:14> = 00000010) through 255 (C <21:14> = 11111111). Reference divider C < 21 : 14 >: 8-bit value for divider ratio of reference divider. C<21:14> is an unsigned binary value. Bits C<13> through C<2> are reserved and should be set to 0. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SWRS023B − MAY 2004 − REVISED MARCH 2005 PRINCIPLES OF OPERATION Address 1001 (E-Word) Word E is a 20-bit data register comprising five fields. The bit rate or bit frequency, used by the transmit synchronous mode is controlled by the BRA, E<21:20>, BRB, E<19:17>, and BRC, E<16>, fields. These three fields control a sequence of dividers, D1 through D3, that divide the reference (crystal) frequency, FX. E<21:20>: 2 bits to set D1 divider setting E<21:20> D1 00 1 01 5 10 6 11 8 E<19:17>: 3 bits to set D2 divider setting E<19:17> D2 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 E<16>: 1 bit to set D3 divider setting E<16> D3 0 16 1 15 TXM, E<15>, sets the transmit capture mode. If TXM is low, the TX_DATA terminal controls the transmit function asynchronously. If TXM is high and the bit-rate clock enabled, the bit-rate clock, DCLK, is output at the DET_LD_DCLK terminal and the transmit data at the TX_DATA terminal is latched on the rising edge of DCLK. E<12:11>: 2 bits to determine the function of terminal 16 E<12:11> TERMINAL 16, DET_LD_DCLK, FUNCTION 00 PLL lock detect output (default) 01 Data clock output 10 Brownout detect output 11 Not used Bits E<14>, E<13> and E<10> through E<2> are reserved and should be set to 0. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 SWRS023B − MAY 2004 − REVISED MARCH 2005 PRINCIPLES OF OPERATION Address 11X0 (D-Word) Word D is a 21-bit data register comprising two fields. Bit D<20> controls the position of the XTAL switch during OOK operation. XTAL_Tune, D<18:16>, is used to fine tune the crystal frequency by using an internal capacitor bank. PFD reset, D<15>, selects the source of the PFD reset signal. D<20 >: 1-bit value to control the position of the XTAL switch during OOK operation, when B<4>=0. D<20 > XTAL SWITCH DURING OOK OPERATION TERMINAL 20 0 Unconnected (open) High-Z 1 Connected (closed) Shorted to ground externally It is recommended that D<20> be set to 0 during OOK operation. D<18 :16 >: 3-bit value to fine-tune the XTAL frequency by using an internal capacitor bank D< 18:16 > TYPICAL LOAD CAPACITANCE 000 13.23 pF 001 22.57 pF 010 17.9 pF 011 27.24 pF 100 15.56 pF 101 24.9 pF 110 20.23 pF 111 29.57 pF D<15 >: 1-bit value to select the reset signal for the PFD D<15 > RESET SIGNAL 0 Derived from XTAL 1 Derived from prescaler NOTE: The default setting for D<15> is 1. Bits D<21>, D<19>, and D<12> through D<1> are reserved and should be set to 0. operating modes Controlled with terminal 3, STDBY STDBY OPERATING MODE 0 Power down of all blocks—programming mode 1 Operational mode and programming mode Controlled with terminal 2, MODE MODE 20 OPERATING MODE 0 Enable A-word 1 Enable B-word POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SWRS023B − MAY 2004 − REVISED MARCH 2005 operating modes (continued) The transmit mode is controlled by the A<5>, B<5>, and B<3> fields and the MODE and STDBY terminals. A<5> B<5> B<3> MODE STDBY OPERATING MODE X X X X 0 Off, programming mode; SPI enabled 1 X 0 0 1 Transmit mode 0, PA disabled; reference, PLL, VCO, and dividers enabled 1 X 1 0 1 Transmit mode 0, PA enabled; reference, PLL, VCO, and dividers enabled X 1 0 1 1 Transmit mode 1, PA disabled; reference, PLL, VCO, and dividers enabled X 1 1 1 1 Transmit mode 1, PA enabled; reference, PLL, VCO, and dividers enabled POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 SWRS023B − MAY 2004 − REVISED MARCH 2005 APPLICATION INFORMATION CLOCK 23 DATA 22 3 STDBY STROBE PA_OUT C1 L2 U1 TRF4903 2 MODE TX_OUT 24 1 TX_DATA 4 21 PA C3 5 L1 PA_VCC2 6 PA_VCC1 C5 C4 7 9 10 C8 0.1 mF PA_VCC1 C11 10 mF C10 0.1 mF 20 XTAL 19 Brownout Detector 8 VCO_VCC VCC XTAL_SW Reference Generator PA_VCC2 C15 C13 CP_VCC 1, 2, 3 Divider MUX XTAL 1 Crystek 017119 C7 VCO DVDD 16 DET_LD_DCLK 15 CP_OUT C9 12 VCO_VCC C6 17 Bit Synchronizer and Data Clock 11 100 pF 18 R1 100 W (See Note B) PLL 14 13 CP_VCC C14 0.1 mF R2 DVDD C12 VCO_VCC R3 C16 0.1 mF Component Selection for Band of Operation 315 MHz TX PA Matching Network PLL Loop Filter XTAL Switch Capacitors 433 MHz 868 MHz 915 MHz Component Value Component Value Component Value Component C1 390 pF C1 270 pF C1 43 pF C1 43 pF C3 5.1 pF C3 4.7 pF C3 1.5 pF C3 1.5 pF C4 390 pF C4 270 pF C4 39 pF C4 33 pF C5 390 pF C5 270 pF C5 39 pF C5 33 pF L1 560 nH L1 470 nH L1 330 nH L1 270 nH L2 75 nH L2 43 nH L2 18 nH L2 15 nH C12 5600 pF C12 5600 pF C12 5600 pF C12 5600 pF C13 120 pF C13 120 pF C13 120 pF C13 120 pF C15 75 pF C15 75 pF C15 75 pF C15 75 pF R2 15 kΩ R2 15 kΩ R2 15 kΩ R2 15 kΩ R3 7.5 kΩ R3 7.5 kΩ R3 7.5 kΩ R3 7.5 kΩ C6 27 pF C6 27 pF C6 27 pF C6 27 pF C7 5.6 pF C7 9.1 pF C7 20 pF C7 22 pF Figure 7. Typical TRF4903 FSK Application Schematic NOTES: A. Loop filter components selected for 19.2-kbps Manchester or 38.4-kbps NRZ for each band. ICP = 0.5 mA, Reference Frequency = 409.6 kHz B. R1 = 100 Ω is optional for operation in the 868-MHz and 915-MHz bands. C. XTAL switch capacitors selected for the frequency deviation of ±50 kHz. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Value SWRS023B − MAY 2004 − REVISED MARCH 2005 APPLICATION INFORMATION CLOCK 23 DATA 22 3 STDBY STROBE PA_OUT C1 L2 U1 TRF4903 2 MODE TX_OUT 24 1 TX_DATA 4 21 PA C3 5 L1 PA_VCC2 6 PA_VCC1 C5 C4 7 9 10 C8 0.1 mF PA_VCC1 C11 10 mF C10 0.1 mF 20 XTAL 19 Brownout Detector 8 VCO_VCC VCC XTAL_SW Reference Generator PA_VCC2 C15 C13 CP_VCC 1, 2, 3 Divider MUX VCO DVDD 16 DET_LD_DCLK 15 CP_OUT C9 12 VCO_VCC XTAL 1 Crystek 017119 17 Bit Synchronizer and Data Clock 11 100 pF 18 C6 27 pF PLL 14 13 CP_VCC C14 0.1 mF R2 DVDD C12 VCO_VCC R3 C16 0.1 mF Component Selection for Band of Operation 315 MHz TX PA Matching Network PLL Loop Filter 433 MHz 868 MHz Component Value Component Value Component C1 390 pF C1 270 pF C3 5.1 pF C3 4.7 pF C4 390 pF C4 C5 390 pF C5 L1 560 nH L2 75 nH C12 C13 915 MHz Value Component Value C1 43 pF C1 43 pF C3 1.5 pF C3 1.5 pF 270 pF C4 39 pF C4 33 pF 270 pF C5 39 pF C5 33 pF L1 470 nH L1 330 nH L1 270 nH L2 43 nH L2 18 nH L2 15 nH 5600 pF C12 5600 pF C12 5600 pF C12 5600 pF 120 pF C13 120 pF C13 120 pF C13 120 pF C15 75 pF C15 75 pF C15 75 pF C15 75 pF R2 15 kΩ R2 15 kΩ R2 15 kΩ R2 15 kΩ R3 7.5 kΩ R3 7.5 kΩ R3 7.5 kΩ R3 7.5 kΩ Figure 8. Typical TRF4903 OOK Application Schematic NOTE: Loop filter components selected for 19.2 kbps Manchester or 38.4 kbps NRZ for each band. ICP = 0.5 mA, Reference Frequency = 409.6 kHz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TRF4903PW ACTIVE TSSOP PW 24 60 TBD Call TI Call TI TRF4903PWR ACTIVE TSSOP PW 24 2000 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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