TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 D D D D D D D D D D Single-Chip RF Transceiver for 868 MHz and 915 MHz ISM Bands 850 MHz to 950 MHz Operation FM/FSK Operation for Transmit and Receive 24-Bit Direct Digital Synthesizer (DDS) With 11-Bit DAC On-Chip VCO and PLL On-Chip Reference Oscillator Minimal External Components Required Low Power Consumption D D D D D D Typical Output Power of 4.5 dBm Typical Output Frequency Resolution of 230 Hz Ultrafast Lock Times From DDS Implementation Two Fully Programmable Operational Modes 2.2 V to 3.6 V Operation Fast Radio Strength Signal Indicator (RSSI) Flexible Serial Interface to TI MSP430 Microcontroller 48-Pin Low Profile Plastic Quad Flat Package (PQFP) IF1_IN IF1_OUT IF_GND IF2_IN DEM_GND VREF LNA_VCC LNA_OUT MIX_IN MIX_VCC MIX_OUT MIX_GND PQFP PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 LNA_GND LNA_IN LNA_GND PA_VCC PA_OUT PA_GND PLL_GND PD_SET PD_OUT2 PD_OUT1 LOCKDET PLL_VCC 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 DEM_VCC DEM_TANK DEM_TANK RSSI_OUT AMP_IN AMP_CAP AMP_OUT S&H_CAP DATA_OUT DATA CLOCK STROBE VCO_TANK1 VCO_TANK2 DDS_GND STDBY MODE DDS_VCC TX_DATA DIG_VCC DIG_GND GND XOSC1 XOSC2 13 14 15 16 17 18 19 20 21 22 23 24 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 description The TRF6900 single-chip solution is an integrated circuit intended for use as a low cost FSK transceiver to establish a frequency-agile, half-duplex, bidirectional RF link. The device is available in a 48-lead TQFP package and is designed to provide a fully-functional multichannel FM transceiver. The chip is intended for linear (FM) or digital (FSK) modulated applications in the new 868 MHz European band and the North American 915 MHz ISM band. The single chip transceiver operates down to 2.2 V and is expressly designed for low power consumption. The synthesizer has a typical channel spacing of approximately 230 Hz to allow narrow-band as well as wide-band application. Due to the narrow channel spacing of the direct digital synthesizer (DDS), the DDS can be used to adjust the TX/RX frequency and allows the use of inexpensive reference crystals. Two fully-programmable operation modes, Mode0 and Mode1, allow extremely fast switching between two preprogrammed settings (e.g., receive(RX)/transmit(TX); TX_frequency_0/TX_frequency_1; RX_frequency_0/RX_frequency_1;…) without reprogramming the device. Each functional block of the transceiver can be specifically enabled or disabled via the serial interface. ISM band standards Europe has assigned a new unlicensed frequency band of 868 MHz to 870 MHz. This new band is specifically defined for short range devices with duty cycles from 0.1% to 100% in several sub-bands. The existing 433 MHz band for short-range devices in Europe has the great disadvantage of very high usage. The new European frequency band, due to the duty cycle assignment, allows a reliable RF link and makes many new applications possible. The North American unlicensed ISM (industrial, scientific, and medical) band covers 902 MHz to 928 MHz (center frequency of 915 MHz), and is suitable for short range RF links. transmitter The transmitter consists of an integrated VCO, a complete fully-programmable direct digital synthesizer, and a power amplifier. The internal VCO can be used with an external tank circuit or an external VCO. The divider, prescaler, and reference oscillator require only the addition of an external crystal and a loop filter to provide a complete DDS with a typical frequency resolution of 230 Hz. The 8-bit FSK frequency deviation register determines the frequency deviation in FSK mode. The modulation itself is done in the direct digital synthesizer, hence no additional external components are necessary. Since the typical RF output power is approximately 4.5 dBm, no additional external RF power amplifier is necessary in most applications. receiver The integrated receiver is intended to be used as a single-conversion FSK receiver. It consists of a low noise amplifier, mixer, IF amplifier, limiter, FM/FSK demodulator with an external LC tank circuit, and a data slicer. The receive strength signal indicator ( RSSI ) can be used for fast carrier sense detection or as an on/off keying, or amplitude shift keying, (OOK/ASK) demodulator. In the learning mode, during a learning sequence (0,1,0,1,0,....), the initial tolerances of the LC demodulator tank circuit are compensated and an external capacitor is charged to a dc voltage that is proportional to the average demodulation dc level. This level is the zero reference for the data slicer to generate the logical levels of the data sequence that follow the learning sequence. Using the internal data switch, the demodulated OOK and FSK signals are available at the same DATA_OUT terminal. baseband interface The TRF6900 can easily be interfaced to a baseband processor such as the Texas Instruments MSP430 ultra low-power microcontroller (see Figure 1). The TRF6900 serial control registers are programmed by the MSP430 and the MSP430 performs baseband operations in software. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 Antenna Microcontroller Section RF Section RSSI_OUT TX_DATA RF In LNA_IN DATA_OUT LOCKDET RF Out PA_OUT MODE TRF6900 TRANSCEIVER + DISCRETES STDBY DATA CLOCK STROBE RSSI Out (Analog Signal) Transmit Data Receive Data Lock Detect Mode Select Standby MSP430 Family µC Programmable Digital I/O Pins Serial Control Data Serial Control Clock Serial Control Strobe Figure 1. System Block Diagram for Interfacing to the MSP430 Microcontroller POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 LNA_GND LNA_IN LNA_GND PA_VCC PA_OUT PA_GND PLL_GND PD_SET 45 44 43 42 41 40 39 RF Buffer Amplifier VREF 37 FM/FSK Demodulator RSSI 1st IF Amplifier 4 Power Amplifier 36 35 RF Mixer LNA 3 38 2nd IF Amplifier/ Limiter 1 2 DEM_GND IF2_IN IF_GND IF1_OUT IF1_IN MIX_GND MIX_VCC MIX_IN 46 MIX_OUT 47 LNA_OUT 48 LNA_VCC functional block diagram LO Buffer Amplifier 34 33 Buffer Amplifier Data Switch 32 5 LPF Amplifier/ Post-Detection Amplifier 6 31 30 7 8 Data Slicer TRF6900 (TOP VIEW) 29 PD_OUT2 9 28 DEM_VCC DEM_TANK DEM_TANK RSSI_OUT AMP_IN AMP_CAP AMP_OUT S&H_CAP DATA_OUT PLL 11 12 Serial Interface 22 23 DATA CLOCK STROBE 24 XOSC2 21 XOSC1 20 GND 19 DIG_GND 18 DIG_VCC 17 TX_DATA 16 DDS_VCC 15 MODE 14 VCO_TANK1 13 26 25 VCO STDBY PLL_VCC 27 Direct Digital Synthesizer and Power-Down Logic DDS_GND LOCKDET 10 VCO_TANK2 PD_OUT1 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION Connection for LPF amplifier/post-detection amplifier capacitor/resistor used to reduce the internal low pass filter frequency and to adjust the post-detection gain AMP_CAP 31 I/O AMP_IN 32 I Analog post-detection amplifier input AMP_OUT 30 O Analog post-detection amplifier output CLOCK 26 I Serial interface clock signal DATA 27 I Serial interface data signal DATA_OUT 28 O Digital output of the data slicer, active high DDS_GND 15 4 Direct digital synthesizer ground POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 Terminal Functions (Continued) TERMINAL NAME DDS_VCC NO. I/O 18 DESCRIPTION Direct digital synthesizer supply voltage DEM_GND 38 DEM_TANK 34, 35 Quadrature demodulator ground DEM_VCC 36 Quadrature demodulator supply voltage DIG_GND 21 Digital ground DIG_VCC 20 Digital supply voltage IF_GND 40 IF1_IN 42 I IF1_OUT 41 O IF2_IN 39 I LNA_GND 1, 3 I/O Quadrature demodulator tank connection Intermediate frequency (IF) section ground Single-ended input for the 1st intermediate frequency (IF) amplifier Single-ended output for the 1st intermediate frequency (IF) amplifier Single-ended input for the 2nd IF amplifier/limiter Low-noise amplifier ground LNA_IN 2 I Low-noise amplifier input LNA_OUT 47 O Low-noise amplifier output, open collector LNA_VCC 48 Low-noise amplifier supply voltage LOCKDET 11 MIX_GND 43 O PLL lock detect output, active high. PLL locked when LOCKDET=1. MIX_IN 46 I Single-ended RF mixer input MIX_OUT 44 O Single-ended RF mixer output MIX_VCC 45 MODE 17 GND 22 PA_GND 6 PA_OUT 5 Mixer ground Mixer supply voltage I Mode select input. The functionality of the device in Mode0 or Mode1 can be programmed via the A-, B-, C-, and D-word of the serial control interface. Ground Power amplifier ground O Power amplifier output, open collector PA_VCC 4 PD_OUT1 10 O Power amplifier supply voltage Charge pump output – PLL in locked condition PD_OUT2 9 O Charge pump output – PLL in unlocked condition PD_SET 8 Charge pump current setting terminal. An external resistor, RPD, is connected to this terminal to set the nominal charge pump current. PLL_GND 7 PLL ground PLL_VCC 12 RSSI_OUT 33 O Receive strength signal indicator, analog output S&H_CAP 29 I/O Connection for sample and hold capacitor for the data slicer. This capacitor determines the integration time constant of the integrator while in the learning mode. STDBY 16 I Standby control for the TRF6900, active low. While STDBY=0, the contents of the control registers are still valid and can be programmed via the serial control interface. STROBE 25 I Serial interface strobe signal TX_DATA 19 I Digital modulation input for FSK/FM modulation of the carrier, active high VCO_TANK1 13 I VCO tank circuit connection. Should be left open if an external VCO is used. VCO_TANK2 14 I VCO tank circuit connection. May also be used to input an external VCO signal. VREF 37 I Reference voltage for the quadrature demodulator XOSC1 23 O Reference crystal oscillator connection XOSC2 24 I Reference crystal oscillator connection. May be used as a single-ended clock input if an external crystal is not used. PLL supply voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, PA_VCC, PLL_VCC, DDS_VCC, DIG_VCC, DEM_VCC, MIX_VCC, LNA_VCC (see Note 1) . . . . . . . . . . . . . . . . . . . –0.6 to 4.5 Vdc Input voltage, logic signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 to 4.5 Vdc Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All GND and VCC terminals must be connected to either ground or supply, respectively, even if the function block is not used. recommended operating conditions MIN TYP MAX UNIT Supply voltage, PA_VCC, PLL_VCC, DIG_VCC, DDS_VCC, DEM_VCC, MIX_VCC, LNA_VCC 2.2 3.6 V Operating temperature –20 60 °C High-level input voltage, VIH (DATA, CLOCK, STROBE, TX_DATA, MODE, STDBY) VCC–0.5 V Low-level input voltage, VIL (DATA, CLOCK, STROBE, TX_DATA, MODE, STDBY) 0.5 V electrical characteristics over full range of operating conditions, (typical values are at PA_VCC, PLL_VCC, DDS_VCC, DIG_VCC, DEM_VCC, MIX_VCC, LNA_VCC = 3 V, TA = 25°C) (unless otherwise noted) supply current consumption in each mode MODE ACTIVE STAGES TYP MAX 2 5 µA 24 31 mA 37 50 26 33 20 dB attenuation 21 25 PA disabled 9.5 12 Power down (standby mode) None RX – FSK (narrow-band) or Carrier sense DDS, PLL, VCO, LNA (normal mode), mixer, 1st IF amplifier, limiter, (demodulator, LPF amplifier, data slicer or RSSI) MIN UNIT PA STATE 0 dB attenuation TX 6 10 dB attenuation DDS, PLL, VCO, PA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 mA TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 electrical characteristics over full range of operating conditions, (typical values are at PA_VCC, PLL_VCC, DDS_VCC, DIG_VCC, DEM_VCC, MIX_VCC, LNA_VCC = 3 V, TA = 25°C) (unless otherwise noted) (continued) LNA/RF mixer PARAMETER TEST CONDITIONS RF frequency range MIN TYP 850 LNA in normal mode LNA gain 9 LNA in low-gain mode LNA noise figure LNA input IP3 UNIT 950 MHz 13 dB 2 LNA in normal mode dB compression LNA input 1 1-dB MAX 3.3 dB 5.5 dB LNA in normal mode –20 –15 dBm LNA in low-gain mode –18 –13 dBm LNA in normal mode –12 –5 dBm –6 1 dBm LNA in low-gain mode LNA input impedance Ω See Figure 3 LNA output impedance Ω See Figure 4 LO frequency range 850 950 MHz IF frequency range 10 21.4 MHz Mixer conversion gain –1 Mixer SSB noise figure IF frequency = 10.7 MHz Mixer input impedance 4.5 dB 26 dB Ω See Figure 5 Mixer input IP3 Mixer input 1-dB compression –7 1 dBm –14 –9 dBm LO level at mixer Input –30 Mixer output impedance IF frequency = 10.7 MHz, See Figure 6 dBm Ω 330 VCO PARAMETER TEST CONDITIONS Frequency range MIN Tuning range Phase noise TYP 850 50 kHz offset Tuning voltage 0.5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT 950 MHz 30 MHz –86 dBc/Hz 2.2 V 7 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 electrical characteristics over full range of operating conditions, (typical values are at PA_VCC, PLL_VCC, DDS_VCC, DIG_VCC, DEM_VCC, MIX_VCC, LNA_VCC = 3 V, TA = 25°C) (unless otherwise noted) (continued) 1st IF amplifier PARAMETER TEST CONDITIONS MIN IF amplifier frequency range 10 IF amplifier gain 5.5 IF amplifier noise figure TYP –12 IF amplifier input IP3 –3.5 UNIT 21.4 MHz 7 11 IF amplifier input 1-dB compression MAX dB 13 dB –3 dBm 4 dBm IF amplifier input impedance IF frequency = 10.7 MHz, See Figure 8 330 Ω IF amplifier output impedance IF frequency = 10.7 MHz, See Figure 9 330 Ω 2nd IF amplifier/limiter PARAMETER TEST CONDITIONS IF amplifier/limiter frequency range MIN TYP 10 IF amplifier/limiter gain IF amplifier/limiter noise figure IF amplifier/limiter input impedance IF frequency = 10.7 MHz, See Figure 10 MAX UNIT 21.4 MHz 80 dB 9 dB 330 Ω RSSI PARAMETER TEST CONDITIONS MIN RSSI range at limiter input –80 RSSI output voltage range 0.44 Nominal slope TYP MAX UNIT –10 dBm 2.6 19 Response time step from power off to –20 dBm at limiter input V mV/dB 1 5 TYP MAX µs low pass filter amplifier [2nd order] PARAMETER TEST CONDITIONS MIN Internal low pass filter frequency 0.75 UNIT MHz demodulator PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Demodulation output bandwidth IF frequency = 10.7 MHz 0.3 MHz Acquisition range Slew rate† IF frequency = 10.7 MHz 300 kHz 2 V/µs † Dependent upon external LC tank circuit. data slicer PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output current R(load) = 3.3 kΩ, C(load) = 10 pF 1 mA Rise time R(load) = 3.3 kΩ, C(load) = 10 pF 0.1 µs 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 electrical characteristics over full range of operating conditions, (typical values are at PA_VCC, PLL_VCC, DDS_VCC, DIG_VCC, DEM_VCC, MIX_VCC, LNA_VCC = 3 V, TA = 25 °C) (unless otherwise noted) (continued) direct digital synthesizer (DDS) PARAMETER Reference oscillator input frequency, frequency ƒreff TEST CONDITIONS MIN TYP MAX as oscillator 15 26 as buffer 15 26 0 4194303 Programmable DDS divider ratio 22 bits DDS divider resolution, ∆ƒ UNIT MHz N × ƒref ÷ 224 FSK – modulation register ratio 8 bits 0 1020 N × ƒref ÷ 222 FSK – modulation resolution PLL PARAMETER TEST CONDITIONS RF input frequency MIN TYP MAX UNIT 950 MHz 850 RF input power Internal VCO by-passed; external input applied to VCO_TANK2 RF input divider ratio, N –10 dBm 256 N × ƒref ÷ 224 RF output frequency resolution Charge pump current 512 Programmable with external resistor, 100 kΩ nominal, APLL = 0 µA 70 power amplifier PARAMETER TEST CONDITIONS Frequency range MIN TYP MAX UNIT 950 MHz 850 0 dB attenuation Amplifier output power –1 4.5 10 dB attenuation –5 –0.5 20 dB attenuation –14 –8 dBm Amplifier off Optimal load impedance 2nd-order harmonic –56 See Figure 22 VCC = 3 V, 0 dB attenuation VCC = 3 V, 0 dB attenuation 3rd-order harmonic Ω –6 dBc –20 dBc typical mode switching and lock times OPERATION TEST CONDITIONS MIN TYP MAX UNIT Frequency hop time between adjacent channels, during receive‡ From transition of MODE to DATA_OUT valid, Channel spacing = 500 kHz, APLL = 111b (maximum) 30 µs Receive-to-transmit turnaround time‡ From transition of MODE to valid RF signal at PA_OUT, PLL locked, 10.7 MHz RX to TX separation 200 µs Transmit-to-receive turnaround time‡ From transition of MODE to valid data at DATA_OUT, PLL locked, 10.7 MHz RX to TX separation 200 µs Standby to receive time‡ From rising edge of STDBY to valid data at DATA_OUT, APLL = 111b (maximum) 600 µs Standby to transmit time‡ From rising edge of STDBY to valid RF signal at PA_OUT, APLL = 111b (maximum) 500 µs ‡ Highly dependent upon loop filter topology. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 timing data for serial interface (see Figure 2) PARAMETER MIN MAX UNIT 20 MHz f(CLOCK) tw(CLKHI) CLOCK frequency CLOCK high time pulse width, CLOCK high 25 ns tw(CLKLO) tsu(DATA) CLOCK low time pulse width, CLOCK low 25 ns Setup time, data valid before CLOCK high 25 ns th(DATA) tw(STROBEHI) Hold time, data valid after CLOCK high 25 ns Strobe high time pulse width, STROBE high (see note 2) 25 ns tw(STROBELO) Strobe low time pulse width, STROBE low 25 ns tw(CLKLO) tw(CLKHI) tw(STROBEHI) CLOCK tsu(DATA) DATA tw(STROBELO) th(DATA) STROBE NOTE 2: CLOCK and DATA must both be low when STROBE is asserted (STROBE= 1). Figure 2. Serial Data Interface Timing 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 detailed description low-noise amplifier The low-noise amplifier (LNA) provides a typical gain of 13 dB and a typical noise figure of 3.3 dB. Two operating modes, normal and low-gain mode, can be selected. The normal operation mode is selected when maximum sensitivity at low input levels is required. If high RF input levels are applied to the TRF6900, the LNA should be operated in the low-gain mode. This ensures a minimum of nonlinear distortions in the overall receiver chain. ↑1 U CH1 S11 ↑1 U CH1 S22 1 1 0.5 2 0.5 5 2 5 CAL OFS 0 0.2 0.5 1 2 5 10 CAL OFS 0 0.2 0.5 1 2 5 10 1 CPL –5 CPL –5 1 FIL 1k –0.5 FIL 1k –0.5 –2 –1 START 850 MHz –2 –1 STOP 950 MHz Figure 3. Typical LNA Input Impedance (S11) at Device Terminal LNA_IN START 850 MHz STOP 950 MHz Figure 4. Typical LNA Output Impedance (S22) at Device Terminal LNA_OUT The low impedance of the LNA input can be easily matched to 50 Ω to interface with a filter or an RF switch. At the LNA open collector output, a filter network can be used for image suppression as well as impedance matching. RF mixer The RF mixer is designed to operate with the on-chip VCO. If an external LO is used, a typical drive level of –10 dBm should be applied at the VCO input terminal. The mixer is a conventional double-balanced Gilbert cell mixer designed to provide a high IP3, typically 1 dBm. Since the mixer output’s push-pull amplifier has a 330 Ω output impedance, a conventional 330 Ω ceramic filter can be directly connected to the output without additional matching. The mixer output can also be directly connected to the 2nd IF amplifier/limiter input terminal, IF2_IN, through a single conventional 330 Ω ceramic filter, thus bypassing the 1st IF amplifier. Figure 5 and Figure 6 show the RF mixer input and output impedances, respectively. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 RF mixer (continued) ↑1 U CH1 S11 ↑1 U CH1 S22 1 1 0.5 2 0.5 5 2 5 CAL OFS 0 0.2 0.5 1 2 5 CAL OFS 10 0 0.2 0.5 1 2 5 10 1 CPL CPL –5 1 –5 FIL 1k –0.5 FIL 1k –0.5 –2 –1 –2 –1 START 850 MHz STOP 950 MHz START 5 MHz Figure 5. Typical RF Mixer Input Impedance (S11) at Device Terminal MIX_IN STOP 25 MHz Figure 6. Typical RF Mixer Output Impedance (S22) at Device Terminal MIX_OUT 1st IF amplifier The 1st IF amplifier provides a typical gain of 7 dB to compensate for losses caused by a ceramic filter. The input and output of the 1st IF amplifier is matched internally to 330 Ω, permitting direct connections to 330 Ω ceramic filters. If filters with different impedances are used, an impedance matching network is required. A second filter can be connected between the 1st IF amplifier and the 2nd IF amplifier/limiter to increase the receiver selectivity. Alternately, the RF mixer output can be directly connected to the 2nd IF amplifier as shown in Figure 7. A single ceramic filter can also be used to connect terminal 41 to terminal 39. In this case, a dc-blocking capacitor of 0.1 µF should be used to connect terminal 44 to 42 to maximize receiver sensitivity. BPF External Components 46 44 42 RF Mixer 1st IF Amplifier 41 39 2nd IF Amplifier/ Limiter Figure 7. Bypassing the 1st IF Amplifier Figure 8 and Figure 9 show the 1st IF amplifier input and output impedances, respectively. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 1st IF amplifier (continued) ↑1 U CH1 S11 ↑1 U CH1 S22 1 1 PRN 0.5 2 0.5 5 2 5 CAL OFS 0 0.2 0.5 1 2 5 OFS 10 0 0.2 0.5 1 2 5 10 CPL CPL –5 –5 FIL 1k –0.5 CAL FIL 1k –0.5 –2 –1 –2 –1 START 5 MHz STOP 25 MHz START 5 MHz Figure 8. Typical 1st IF Amplifier Input Impedance (S11) at Device Terminal IF1_IN STOP 25 MHz Figure 9. Typical 1st IF Amplifier Output Impedance (S22) at Device Terminal IF1_OUT 2nd IF amplifier/limiter The 2nd IF amplifier/limiter consists of several differential amplifier stages with an overall gain of approximately 80 dB. At the IF2_IN 330 Ω input, a minimum signal level of approximately 32 µV is required to generate a limited signal at the limiter output. The limiter output is directly fed to the FM/FSK demodulator. Figure 10 shows the 2nd IF amplifier/limiter input impedance. ↑1 U CH1 S11 1 2 0.5 5 CAL OFS 0 0.2 0.5 1 2 5 10 CPL –5 FIL 1k –0.5 –2 –1 START 5 MHz STOP 25 MHz Figure 10. Typical 2nd IF Amplifier/Limiter Input Impedance (S11) at Device Terminal IF2_IN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 received signal strength indicator (RSSI) The received signal strength indicator provides a voltage at terminal 33, RSSI_OUT, that is proportional to the RF limiter input level. The slope of the RSSI circuit is typically 19 mV/dB over a frequency range of 10 MHz to 21.4 MHz. Because of its ultrafast response time (typically 1 µs per –20 dBm to off step), the RSSI can easily be used as an amplitude-shift keying (ASK) or on/off keying (OOK) demodulator for data rates up to 100 kBit/sec. FM/FSK demodulator The demodulator is intended for analog (FM) and digital (FSK) frequency demodulation. It consists of a quadrature demodulator with an external LC tank circuit. A variable inductor, internal to the TRF6900, operates in parallel with the external tank circuit (see Figure 13), and is used to adjust the external tank circuit’s resonant frequency. If the tolerances of the external demodulator tank circuit components can provide a maximum frequency error of less than 5%, then no additional adjustments are required. As long as the device is in the learning mode, the internal reactance automatically fine-adjusts the resonant frequency of the external LC tank circuit. Depending on the supply voltage, the tank circuit tuning range is approximately four times the discriminator 3-dB bandwidth. While in the learning mode i.e, during a dc-free learning sequence of 0,1,0,1,0,...., the initial tolerances of the LC demodulator tank circuit are compensated and an external capacitor (connected to terminal 29, S&H_CAP) is charged to a dc voltage that is proportional to the average demodulation dc level. This level establishes the decision threshold voltage and consequently sets the zero reference for the data slicer to generate the logical levels of the data sequence that follow the learning sequence. Therefore, the user can use a non-dc-free data signal. The demodulator will be automatically activated if the limiter (x_LIM) and low-pass filter amplifier (x_LPF) are activated and the data switch is set to FSK/FM reception (x_SW = 0). data switch The TRF6900 incorporates an internal data switch used to select the input signal for the low-pass filter amplifier/post detection amplifier. Depending on the settings in the Mode0 or Mode1 enable registers (C-word, D-word), the user can select between OOK/ASK or FSK baseband processing without having to change external components. low-pass filter amplifier/post-detection amplifier The low-pass filter amplifier/post-detection amplifier is configured to operate as a current-to-voltage amplifier and may be used to realize a low pass filter for post detection. The low-pass amplifier bandwidth may be adjusted according to noise and signal bandwidth requirements. An internal 10 pF capacitor sets the maximum –3 dB corner frequency to approximately 0.75 MHz (see Figures 11 and 12). 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 low-pass filter amplifier/post-detection amplifier (continued) C1 External Components R1 R1 32 From Data Switch C1 31 30 32 R2 – From Data Switch To Data Slicer + Vref 31 30 R2 – To Data Slicer + Vref Figure 11. 1st-Order Low-Pass Filter Example External Components C2 Figure 12. 2nd-Order Low-Pass Filter Example The amplifier can be configured as a 1st- or 2nd-order low-pass filter with bandwidths that are determined by external components. The internal resistor R2 is set to 10 kΩ, hence the –3dB corner frequency for a 2nd-order low pass filter (as shown in Figure 12) can be derived from the following formula: ƒg ^2 p Ǹ 1 W 10 k R1 C1 C2 data slicer The data slicer is fundamentally a comparator. The data slicer provides binary logic level signals, derived from the demodulated and low pass-filtered IF signal, that are able to drive external CMOS compatible inputs. The noninverting input is directly connected to the internal reference voltage, Vref, and the inverting input is driven by the output of the low-pass filter amplifier/post-detection amplifier. The decision threshold of the data slicer is determined by the internal reference voltage, Vref. The automatic frequency control (AFC) loop scheme for the TRF6900 is shown in Figure 13. Low-Pass Filter Amplifier/ Post-Detection Amplifier C1 External Tank Circuit 35 IF2_IN 34 R1 32 31 FM/FSK Demodulator 39 Limiter External Components C2 30 – Vref Internal Variable Inductor – DATA_OUT + 28 + Vref – + Integrator Vref Figure 13. AFC Loop to Control the Data Slicer Decision Threshold POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 data slicer (continued) The integrator, acting as an error amplifier, takes the low-pass filtered output signal and generates a control voltage proportional to the frequency error of the external tank circuit as compared to the limiter output signal. By adjusting the value of the internal variable inductor, this control voltage is used to fine-tune the external tank to its nominal value. The acquisition time of the AFC loop can be adjusted by an external capacitor connected to terminal 29, S&H_CAP. This capacitor determines the integration time constant of the integrator while in learning mode. As a rule of thumb, the time constant of the AFC loop should be at least five times greater than the baseband signal fundamental period. The time constant of the entire AFC control loop can be calculated as follows: tAFC [ 22 kW C terminal 29 The automatic frequency control loop controls the resonant frequency of the external LC tank without any additional external adjustments as long as learning mode operation is selected. If hold mode is selected, the AFC loop is open and an external dc voltage can be applied at terminal 29 to set the threshold of the data slicer. During learning mode, a precharged capacitor (connected to terminal 29, S&H_CAP) can be used to set the dc threshold voltage of the data slicer in hold mode. In other words, the data slicer constantly integrates the incoming signal during the learning sequence (0,1,0,1. . .) and charges the external capacitor connected to terminal 29, S&H_CAP to a dc voltage level, Vref, that is proportional to the average demodulation dc level. After a predefined time (dependent upon the application), the data slicer is switched to hold mode. The data slicer stops integrating and uses the voltage stored on the external capacitor as the decision threshold between a logic 0 or a logic 1 on the DATA_OUT terminal 28. reference oscillator The reference oscillator provides the DDS system clock. It allows operation, with a suitable external crystal, between 15 MHz and 26 MHz. An external oscillator may be used to supply clock frequencies between 15 MHz and 26 MHz. The external oscillator should be directly connected to XOSC2, terminal 24. The other oscillator terminal (XOSC1, terminal 23) should be left open or can be used as a buffered version of the signal applied at terminal 24 (see Figure 14). The same crystal or externally supplied oscillator signal is used to derive both the transmit and receive frequencies. XOSC1 XOSC2 23 24 NC External Signal, ƒref Figure 14. Applying an External Oscillator Signal 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 direct digital synthesizer general principles of DDS operation In general, a direct digital synthesizer (DDS) is based on the principle of generating a sinewave signal in the digital domain. Benefits include high precision, wide frequency range, a high degree of software programmability, and extremely fast lock times. A block diagram of a typical DDS is shown in Figure 15. It generally consists of an accumulator, sine lookup table, a digital-to-analog converter, and a low-pass filter. All digital blocks are clocked by the reference oscillator. Synthesizer + Sine Lookup Table N-Bit Register Low-Pass Filter DAC Analog Output Signal Frequency Register Load With Frequency Word Figure 15. Typical DDS Block Diagram The DDS constructs an analog sine waveform using an N-bit adder counting up from 0 to 2N in steps of the frequency register, whereby generating a digital ramp waveform. Each number in the N-bit output register is used to select the corresponding sine wave value out of the sine lookup table. After the digital-to-analog conversion, a low-pass filter is necessary to suppress unwanted spurious responses. The analog output signal can be used as a reference input signal for a phase locked loop. The PLL circuit then multiplies the reference frequency by a predefined factor. TRF6900 direct digital synthesizer implementation A block diagram of the DDS implemented in the TRF6900 is shown in Figure 16. It consists of a 24-bit accumulator clocked by the reference oscillator along with control logic settings. 24 Reference Frequency, ƒref + 24-Bit Register 11 11-Bit DAC Sine Shaper Low-pass Filter ƒDDS to PLL DDS Frequency Register MODE – (Terminal 17) A – Word DDS Mode0 Frequency Setting B – Word DDS Mode1 Frequency Setting 22 D – Word / DEV Bits (FSK Deviation) 24 22 Mode0/1 Select Logic FSK Frequency Deviation Register + 8 Modulation Control Logic TX_DATA – (Terminal 19) C – Word / MM Bit (Modulation Mode Select) Figure 16. DDS Block Diagram as Implemented in the TRF6900 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 TRF6900 direct digital synthesizer implementation (continued) The frequency of the reference oscillator, ƒref, is the DDS sample frequency, which also determines the maximum DDS output frequency. Together with the accumulator width (in bits), the frequency resolution of the DDS can be calculated. Multiplied by the divider ratio (prescaler) of the PLL, N, the minimum frequency step size of the TRF6900 is calculated as follows: ƒ Dƒ N ref 2 24 + The 24-bit accumulator can be programmed via two 22-bit frequency setting registers (the A-word determines the mode0 frequency, the B-word determines the mode1 frequency) with the two MSB bits set to zero. Consequently, the maximum bit weight of the DDS system is reduced to 1/8 (see Figure 17). This bit weight corresponds to a VCO output frequency of (ƒref/8) × N. Depending on the MODE terminal’s (terminal 17) logic level, the internal mode select logic loads the frequency register with either the DDS_0 or DDS_1 frequency (see Figure 16 and Figure 17). 22 DDS Frequency Setting For Mode0/1 From A-Word/B-Word 23 DDS Frequency Register ... X X X X X 0 0 X X .... LSB MSB 22 21 20 . . . ... 4 3 Bit weight: 1/2 1/4 1/8 1/16 . . . 8 2 1 0 ... 1 2 24 FSK Frequency Deviation Register – DEV 0 0 .... .... X X X X X X X X 0 0 MSB DDS Frequency Register LSB 23 22 . . . . ....9 8 7 6 5 4 3 2 1 0 Figure 17. Implementation of the DDS Frequency and FSK Frequency Deviation in the DDS Frequency Register The VCO output frequency, ƒout, which is dependent on the DDS_x frequency settings ( DDS_0 in the A-word or DDS_1 in the B-word ), can be calculated as follows: ƒ out + DDS_x ƒ ref N 2 24 +N ƒ ref DDS_x 2 24 If FSK modulation is selected (MM=0; C-Word, bit 16) the 8-bit FSK deviation register can be used to program the frequency deviation of the 2-FSK modulation. Figure 17 illustrates where the 8 bits of the FSK deviation register map into the 24-bit DDS frequency register. Since the two LSBs are set to zero, the total FSK deviation can be determined as follows: Dƒ2–FSK + N ƒ ref DEV 2 22 Hence, the 2-FSK frequency, set by the level of TX_DATA, is calculated as follows: +Low + N ƒ out1:TX_DATA ƒ ref DDS_x 2 24 +High + N ƒ out2:TX_DATA ƒ ref (DDS_x )4 2 24 This frequency modulated output signal is used as a reference input signal for the PLL circuit. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DEV) TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 TRF6900 direct digital synthesizer implementation (continued) Channel width (frequency deviation) for 2-FSK modulation and channel spacing are software programmable. The minimum channel width and minimum channel spacing depend on the RF system frequency plan. Since the DDS registers are static, preprogrammed values are retained during standby mode. This feature greatly reduces turn on time, reduces current consumption when coming out of standby mode, and enables very fast lock-times. The PLL lock-times ultimately determine when data can be transmitted or received. phase-locked loop The phase-locked loop (PLL) of the TRF6900 consists of a phase detector (PD) and a frequency acquisiton aid (FD), two charge pumps, an external loop filter, a voltage controlled oscillator (VCO), and a programmable fixed prescaler (N-divider) in the feedback loop (see Figure 18). The PLL as implemented in the TRF6900 multiplies the DDS output frequency and further suppresses the unwanted spurious signals produced by the direct digital synthesizer. DDS ƒDDS PD 10 IPD_1 IPD_2 ƒref FD External Loop Filter 13, 14 VCO ƒout 9 N-Divider 256 / 512 Figure 18. Basic PLL Structure VCO A modified Colpitts oscillator architecture with an external resonant circuit is used for the TRF6900. The internal bias current network adjusts the signal amplitude of the VCO. This allows a wide range of Q-factors (30….60) for the external tank circuit. The VCO can be bypassed by applying an external RF signal at VCO_TANK2, terminal 14. To drive the internal PLL and power amplifier, a typical level of –10 dBm should be applied. When an external VCO is used, the x_VCO bit should be set to 0. phase detector and charge pumps The TRF6900 contains two charge pumps for locking to the desired frequency; one for coarse tuning of the frequency differences (called the frequency acquisition aid), and one for fine tuning of the phase differences (used in conjunction with the phase detector). The XOR phase detector and charge pumps produce a mean output current that is proportional to the phase difference between the reference frequency and the VCO frequency divided by N; N=256 or 512. The TRF6900 generates the current pulses IPD_1 during normal operation (PLL locked). An additional slip detector and acquisition aid charge pump generates current pulses at terminal PD_OUT2 during the lock-in of the PLL. This charge pump is turned off when the PLL locks in order to reduce current consumption. The multiplication factor of the acquisition aid current IPD_2 can be programmed by three bits (APLL) in the C-word. The slip detector output, PD_OUT2, at terminal 9 should be connected directly to the loop filter capacitor C1, as in Figure 21. The nominal charge pump current I0 is determined by the external resistor RPD, connected to terminal 8, and can be calculated as follows: I0 + R7 V PD POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 phase detector and charge pumps (continued) During normal operation (PLL locked), the acquisition aid charge pump is disabled and the maximum charge pump current IPD_1 is determined by the nominal value I0 (see Figure 19). I0 IPD_1 1 Figure 19. Normal Operation Charge Pump Current, IPD_1 Each time the PLL is in an unlocked condition, the acquisition aid charge pump generates current pulses IPD_2. The IPD_2 current pulses are APLL times larger than I0 (see Figure 20). I0 1 IPD_1 APLL IPD_2 Figure 20. Acquisition Aid, IPD_2, and Normal Operation, IPD_1, Charge Pump Currents programmable divider The internal divider ratio, N, can be set to 256 or 512 via the C-word. Since a higher divider ratio adds additional noise within the multiplication loop, the lowest divider ratio possible for the target application should be used. loop filter Loop filter designs are a balance between lock-time, noise, and spurious suppression. For the TRF6900, common loop filter design rules can be used to determine an appropriate low-pass filter. Standard formulas can be used as a first approach to calculate a basic loop filter. Figure 21 illustrates a basic 3rd-order loop filter. VCO_TANK1 C3 VCO_TANK2 14 13 R2 10 PD_OUT1 C3c L1 R1 PD_OUT2 9 C3d C2 VCO C4 C1 2nd-Order Loop Filter 3rd-Order Loop Filter Figure 21. Basic 3rd-Order Loop Filter Structure For maximum suppression of the unwanted frequency components, the loop filter bandwidth should generally be made as narrow as possible. At the same time, the filter bandwidth has to be wide enough to allow for the 2-FSK modulation and appropriate lock-time. A detailed simulation of the phase-locked loop should be performed and later verified on PCB implementations. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 power amplifier The power amplifier (PA) can be programmed via two bits (P0 and P1 in the D-word) to provide varying output power levels. Several control loops are implemented internally to set the output power and to minimize the sensitivity of the power amplifier to temperature, load impedance, and power supply variations. The output stage of the PA usually operates in Class-C and enables easy impedance matching. PA_OUT, terminal 5, is an open collector output terminal. ↑1 U CH1 S22 1 2 0.5 5 CAL OFS 0 0.2 0.5 1 2 10 CPL –5 1 FIL 1k –2 –0.5 –1 START 850 MHz STOP 950 MHz Figure 22. Power Amplifier Output Impedance (S22) at Device Terminal 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 PRINCIPLES OF OPERATION serial control interface A 3-wire unidirectional serial bus (CLOCK, DATA, STROBE) is used to program the TRF6900 (see Figure 23). The internal registers contain all user programmable variables including the DDS frequency setting registers as well as all control registers. At each rising edge of the CLOCK signal, the logic value on the DATA terminal is written into a 24-bit shift register. Setting the STROBE terminal high loads the programmed information into the selected latch. While the STROBE signal is high, the DATA and CLOCK lines must be low (see Figure 2). Since the CLOCK and STROBE signals are asynchronous, care should be taken to ensure these signals remain free of glitches and noise. As additional leading bits are ignored, only the least significant 24 bits are serial-clocked into the shift register. Due to the static CMOS design, the serial interface consumes virtually no current and it can be programmed in active as well as in standby mode. CLOCK STROBE Serial Interface Logic Shift Register DATA 22 A - Latch 22 ADDR 3 B - Latch ADDR Decoder 22 C - Latch 21 D - Latch Figure 23. Serial Interface Block Diagram The control words are 24 bits in length. The first incoming bit functions as the most significant bit ( MSB ). To fully program the TRF6900, four 24-bit words must be sent: the A-, B-, C-, and D-word. If individual bits within a word are to be changed, then it is sufficient to program only the appropriate 24-bit word. The definition of the control words are illustrated in Figure 24. Tables 1, 2, and 3 describe the function of each parameter. An ADDR equal to 111 is reserved for test purposes and should not be used. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 PRINCIPLES OF OPERATION A–Word (Programming of DDS_0) MSB 23 0 22 21 20 19 18 17 0 LSB 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DDS Frequency Setting for Mode0 (DDS_0 [21:0]) ADDR B–Word (Programming of DDS_1) MSB 23 0 22 21 20 19 18 17 1 LSB 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DDS Frequency Setting for Mode1 (DDS_1 [21:0]) ADDR C–Word ( Control Register for PLL, Data Slicer and Mode1 Settings) MSB 23 1 22 21 0 20 19 18 17 APLL A2 ADDR 16 15 A1 14 13 12 11 10 X X PLL 1 NPLL MM SLCTL 9 LSB 8 7 6 5 4 3 2 1 PA PLL VCO P1 A0 SLC LPF SW RSSI LIM IF MIX P0 LNAM L1 D–Word (Control Register for Modulation and Mode0 Settings) MSB 23 1 22 21 1 0 20 19 18 17 16 15 14 13 ADDR 12 11 L0 LSB 10 Modulation Register [20:13] DEV 0 Mode1 Control Register [12:0] 9 8 7 6 5 4 3 2 1 0 Mode0 Control Register [12:0] PA PLL VCO DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 P1 SLC LPF SW RSSI LIM P0 IF MIX LNAM L1 L0 NOTE: Start programming with MSB and ensure that the CLOCK and DATA lines are low during the rising edge of the strobe signal. Figure 24. Serial Control Word Format POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 PRINCIPLES OF OPERATION Table 1. Mode0 Control Register Description (D-Word) SYMBOL BIT LOCATION 0_LNAM [1:0] NUMBER OF BITS INITIAL SETTINGS AFTER POWER-UP DESCRIPTION Low-noise amplifier operation mode 2 L1 0 0 1 1 L0 0 1 0 1 DEFAULT VALUE Disabled 00b : LNA disabled : LNA enable – low-gain mode : LNA disabled : LNA enable – normal operation mode 0_MIX [2] 1 0_IF [3] 1 Enable mixer Enable 1st IF amplifier 0_LIM [4] 1 Enable limiter 0_RSSI [5] 1 Enable RSSI 0_SW [6] 1 DEFAULT STATE 1: enabled 0: disabled Disabled 0b 1: enabled 0: disabled Disabled 0b 1: enabled 0: disabled Disabled 0b 1: enabled 0: disabled Disabled 0b Routed to Demodulator 0b 0b Data switch 0 : LPF amplifier input routed to demodulator (FSK/FM) 1 : LPF amplifier input routed to RSSI (OOK/ASK) 0_LPF 0_SLC 0_PA [7] 1 Enable LPF amplifier 1: enabled 0: disabled Disabled [8] 1 Enable data slicer 1: enabled 0: disabled Disabled 0b Disabled 00b [10:9] Power amplifier mode 2 0_VCO [11] 0_PLL [12] P1 0 0 1 1 P0 0 : disabled 1 : 10 dB attenuation, enable modulation via TX_DATA 0 : 20 dB attenuation, enable modulation via TX_DATA 1 : 0 dB attenuation, enable modulation via TX_DATA 1 During operation, this bit should always be enabled (1: enabled), unless an external VCO is used. Disabled 0b Enable PLL (DDS system, RF, VCO, divider, phase comparator and charge pump) 1: enabled 0: disabled Disabled 0b 1 NOTE: The FM/FSK demodulator is automatically enabled if the limiter and low-pass amplifier are enabled and the data switch is set to FSK reception. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 PRINCIPLES OF OPERATION Table 2. Mode1 Control Register Description (C-Word) SYMBOL BIT LOCATION 1_LNAM [1:0] NUMBER OF BITS INITIAL SETTINGS AFTER POWER-UP DESCRIPTION Low-noise amplifier operation mode 2 L1 0 0 1 1 L0 0 1 0 1 DEFAULT VALUE Disabled 00b : LNA disabled : LNA enable – low-gain mode : LNA disabled : LNA enable – normal operation mode 1_MIX [2] 1 1_IF [3] 1 Enable mixer Enable 1st IF amplifier 1_LIM [4] 1 Enable limiter 1_RSSI [5] 1 Enable RSSI 1_SW [6] 1 DEFAULT STATE 1: enabled 0: disabled Disabled 0b 1: enabled 0: disabled Disabled 0b 1: enabled 0: disabled Disabled 0b 1: enabled 0: disabled Disabled 0b Routed to Demodulator 0b 0b Data switch 0 : LPF amplifier input routed to demodulator (FSK/FM) 1 : LPF amplifier input routed to RSSI (OOK/ASK) 1_LPF 1_SLC 1_PA [7] 1 Enable LPF amplifier 1: enabled 0: disabled Disabled [8] 1 Enable data slicer 1: enabled 0: disabled Disabled 0b Disabled 00b [10:9] Power amplifier mode 2 1_VCO [11] 1_PLL [12] P1 0 0 1 1 P0 0 : disabled 1 : 10 dB attenuation, enable modulation via TX_DATA 0 : 20 dB attenuation, enable modulation via TX_DATA 1 : 0 dB attenuation, enable modulation via TX_DATA 1 During operation, this bit should always be enabled (1: enabled), unless an external VCO is used. Disabled 0b Enable PLL (DDS system, VCO, RF divider, phase comparator and charge pump) 1: enabled 0: disabled Disabled 0b 1 NOTE: The FM/FSK demodulator is automatically enabled if the limiter and low-pass amplifier are enabled and the data switch is set to FSK reception. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 PRINCIPLES OF OPERATION Table 3. Miscellaneous Control Register Description SYMBOL WORD BIT LOCATION NUMBER OF BITS DDS_0 A-word [21:0] 22 DDS_1 B-word [21:0] DEV D-word [20:13] SLCTL C-word APLL DESCRIPTION INITIAL SETTINGS AFTER POWER-UP DEFAULT STATE DEFAULT VALUE DDS frequency setting in Mode0 Zero All zeroes 22 DDS frequency setting in Mode1 Zero All zeroes 8 FSK frequency deviation register Zero All zeroes [15] 1 Slicer mode select bit 0 : hold mode 1 : learning mode Hold mode 0b C-word [20:18] 3 Acceleration factor for the frequency acquisition aid charge pump A2 A1 A0 0 0 0 :1 0 0 1 : 20 0 1 0 : 40 0 1 1 : 60 : 1 1 1 : 140 Zero 000b NPLL C-word [17] 1 PLL divider ratio 0 : 256 1 : 512 256 0b MM C-word [16] 1 Modulation mode select. Sets the behavior of pin TX_DATA to FSK data input. 0 : FSK/FM 1 : Do not use FSK mode 0b operating modes Tables 4 and 5 illustrate operating modes and transmit frequencies as set by the STDBY, MODE, and TX_DATA terminals used in conjunction with the DDS frequency settings. Table 4. Transmitting Data in FSK Mode (MM bit set to 0) TERMINAL TRANSMIT FREQUENCY STDBY MODE TX_DATA 1 0 0 ƒout =ƒref × N × (DDS_0)/224 1 0 1 1 1 0 ƒout =ƒref × N × (DDS_0 + 4 × DEV)/224 ƒout = ƒref × N × (DDS_1)/224 1 1 1 ƒout = ƒref × N × (DDS_1 + 4 × dev)/224 Table 5. Operating Mode Per STDBY Terminal STDBY OPERATING MODE 0 Standby/programming mode – power down of all blocks 1 Operating mode and programming mode Two independent operating modes, Mode0 and Mode1, allow extremely fast switching between two preprogrammed settings by toggling the MODE terminal. Each mode can be viewed as a bank of configuration registers which store the frequency settings and the enable/disable settings for each functional block of the TRF6900. The MODE terminal is then used to asynchronously switch between Mode0 and Mode1 as shown in Figure 25. Several examples of operating sequences are shown in Table 6. 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 PRINCIPLES OF OPERATION operating modes (continued) MODE Terminal (Terminal 17) = 1 Mode0 Register Settings (D-Word) Mode1 Register Settings (C-Word) Mixer Enable Mixer Enable 1st IF Amplifier Enable 1st IF Amplifier Enable Limiter Enable Limiter Enable RSSI Enable RSSI Enable Data Switch Data Switch LPF Amplifier Enable LPF Amplifier Enable Data Slicer Enable Data Slicer Enable Power Amplifier Mode Power Amplifier Mode VCO Enable VCO Enable PLL Enable PLL Enable Synthesizer: Synthesizer: DDS Frequency DDS Frequency MODE Terminal (Terminal 17) = 0 Figure 25. Interaction Between MODE Terminal and Preprogrammed Mode0 and Mode1 Control Registers Table 6. Operating Mode Examples FUNCTION/DESCRIPTION MODE0 MODE1 Receive polling with frequency hopping, or scan band Receive on frequency 0 Receive on frequency 1 Transmit and receive on different frequencies Transmit on frequency 0 Receive on frequency 1 Broadcast on one frequency and receive on another Transmit on frequency 0 (broadcast channel) Receive on frequency 1 Rapid switch between receive and power saving mode (keep DDS/VCO running) Receive on frequency 0 All blocks off except DDS, VCO, and PLL Emulate FSK transmit operation using the MODE terminal for wideband FSK Transmit on frequency 0 Transmit on frequency 0 + deviation POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 PRINCIPLES OF OPERATION operating modes (continued) Received Data Stream RSSI Active PLL Locked, Wait For RSSI Signal Enter Operating Mode Store Control Word Enter Standby/Programming Mode, Scan in Serial Control Word (MSB Scanned in First) OPERATION RSSI_OUT LOCKDET STDBY STROBE CLOCK DATA_OUT Bit 21 Bit 22 DATA MSB Bit 23 ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Not Valid Data Bit 2 Bit 1 LSB Bit 0 Valid Valid Valid Data Data Data Figure 26 illustrates how the user of the TRF6900 can preload the serial control words while in standby/programming mode and then receive baseband data while in operating mode. Figure 26. Preloading Serial Control Word and Receiving Baseband Data 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 APPLICATION INFORMATION A typical application schematic for an FSK system operating in the European 868 MHz to 870 MHz ISM band is shown in Figure 27. FLT-SMD BPF1 J4 SMA/B/L L2 6.8 nH 3 RF Buffer Amplifier RF Mixer LNA_GND 37 C6 470 pF 4 C40 150 pF C5 150 pF L1 5.6 nH 6 J1 7 RF_Out SMA/B/L R3 8 36 35 FM/FSK Demodulator 34 RSSI_OUT 33 Data Switch PA_GND PLL_GND Data Slicer TRF6900 (TOP VIEW) PD_SET AMP_CAP 31 PLL AMP_OUT 30 S&H_CAP 29 DATA_OUT 28 14 15 16 17 18 19 20 Serial Interface CLOCK 22 23 XOSC2 GND 21 XOSC1 STROBE DIG_GND VCO 13 DIG_VCC PLL_VCC TX_DATA 12 C1 8.2 nF MODE LOCKDET DDS_VCC C2 820 pF C17 100 pF 1% R28 5.6 kΩ C19 15 pF C18 220 pF R5 22 kΩ R4 TBD C20 12 nF DATA Direct Digital Synthesizer and Power-Down Logic PD_OUT1 STDBY R2 8.2 kΩ 11 PD_OUT2 DDS_GND 10 L7 2.2 µH 5% AMP_IN 32 LPF Amplifier/ Post-Detection Amplifier Power Amplifier 68 kΩ 9 C16 18 pF Buffer Amplifier PA_VCC 5 C4 3.3 pF DEM_VCC 2nd IF Amplifier/ Limiter 1st IF Amp LNA 38 VREF 39 DEM_GND 40 IF2_IN 41 IF_GND 42 IF1_OUT MIX_GND MIX_OUT 43 IF1_IN 44 45 LNA_GND 2 LNA_in 46 C15 47 nF RSSI 1 C7 100 pF 47 MIX_IN LNA_VCC 48 FLT-SMD BPF2 L4 33 nH LNA_OUT C8 150 pF C9 1.2 pF MIX_VCC L3 12 nH 27 26 25 AMP_OUT RSSI_OUT RX_DATA DATA CLOCK STROBE MODE STDBY TX_DATA LOCKDET 24 R1 10 kΩ L8 10 nH C24 6.8 pF C41 150 pF R7 820 Ω C23 3.3 pF SMV1233–011 CQ1 18 MHz R6 V1 C22 15 pF 1 MΩ C21 15 pF Figure 27. Typical Application Schematic for 868 to 870 MHz European ISM Band POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 APPLICATION INFORMATION external component list (5% tolerance unless otherwise noted) for Figure 27 DESIGNATOR DESCRIPTION (SIZE) VALUE C1 Capacitor 8.2 nF C2 Capacitor 820 pF C4 Capacitor 3.3 pF C5 Capacitor 150 pF C6 Capacitor 470 nF C7 Capacitor 100 pF C8 Capacitor 150 pF C9 Capacitor 1.2 pF C15 Capacitor 47 nF C16 Capacitor 18 nF C17 Capacitor 100 pF C18 Capacitor 220 pF C19 Capacitor 15 pF C20 Capacitor 12 nF C21 Capacitor 15 pF C22 Capacitor 15 pF C23 Capacitor 3.3 pF C24 Capacitor 6.8 pF C40 Capacitor 150 pF C41 Capacitor 150 pF L1 Coil 5.6 nH Murata LQW1608 L2 Coil 6.8 nH Murata LQW1608 L3 Coil 12 nH Murata LQW1608 L4 Coil 33 nH Murata LQW1608 L7 Coil 2.2 µH Murata LQH1N2RZJ04, 5% tolerance Murata LQW1608, 5% tolerance 30 L8 Coil 10 nH R1 Resistor 10 kΩ R2 Resistor 8.2 kΩ R3 Resistor 68 kΩ R4 Resistor Optional R5 Resistor 22 kΩ R6 Resistor 1 MΩ R7 Resistor 820 Ω MANUFACTURER PART NUMBER/COMMENTS 1% tolerance R28 Resistor 5.6 kΩ V1 Varactor diode SMV1233-011 Alpha Industries 18 MHz CMAC Frequency Products CQ1 Crystal BPF1 Filter Murata SFECV10.7MJ-Z, 10.7 MHz IF filter BPF2 Filter Murata SFECV10.7MJ-Z, 10.7 MHz IF filter POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CX-1 SMI TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 APPLICATION INFORMATION A typical application schematic for an FSK system operating in the North American 902 MHz to 928 MHz ISM band is shown in Figure 28. DNP FLT-SMD BPF1 J4 SMA/B/L L2 10 nH C32 4.7 pF 3 39 RF Buffer Amplifier RF Mixer LNA_GND DEM_GND C6 1 nF 4 C5 1 nF C40 0.1 µF L1 4.7 nH 6 C4 3.3 pF J1 7 RF_Out SMA/B/L R3 8 C27 0.1 µF DEM_VCC 36 35 FM/FSK Demodulator 34 RSSI_OUT 33 L7 2.2 µH 5% Data Switch AMP_CAP PA_GND PLL_GND Data Slicer TRF6900 (TOP VIEW) PD_SET PLL AMP_OUT 30 S&H_CAP 29 DATA_OUT 28 13 14 15 16 17 18 19 20 Serial Interface CLOCK XOSC2 GND 21 XOSC1 STROBE DIG_GND VCO C30 0.1 µF DIG_VCC PLL_VCC TX_DATA 12 C1 4.7 nF MODE LOCKDET DDS_VCC C2 470 pF Direct Digital Synthesizer and Power-Down Logic PD_OUT1 22 23 C19 330 pF 31 C18 100 pF C20 0.1 µF DATA STDBY R2 6.2 kΩ 11 PD_OUT2 DDS_GND 10 C28 3 pF DNP SAT C17 100 pF 1% AMP_IN 32 LPF Amplifier/ Post-Detection Amplifier Power Amplifier 100 kΩ 9 R4 10k Buffer Amplifier PA_VCC 5 37 2nd IF Amplifier/ Limiter 1st IF Amp LNA 38 VREF 40 IF2_IN 41 IF_GND MIX_GND MIX_VCC 42 IF1_OUT 43 IF1_IN C26 0.1 µF 44 45 LNA_GND 2 LNA_in 46 C15 0.1 µF RSSI 1 C7 100 pF 47 MIX_IN LNA_VCC 48 FLT-SMD BPF2 L4 18 nH LNA_OUT C8 0.1 µF C9 1 pF MIX_OUT L3 8.2 nH C25 0.1 µF 27 26 25 R5 39 kΩ AMP_OUT RSSI_OUT RX_DATA DATA CLOCK STROBE MODE STDBY TX_DATA LOCKDET 24 R1 10 kΩ L8, 10 nH R8 10 kΩ C41 0.1 µF C24 2.7 pF C29 0.1 µF R7 CQ1 100 Ω 25.6 MHz C23 2.7 pF SMV1247–079 SMV1247–079 V1 R6, 1 MΩ V2 C22 10 pF C21 10 pF C31 DNP SAT Figure 28. Typical Application Schematic for 902 to 928 MHz North American ISM Band external component list (5% tolerance unless otherwise noted) for Figure 28 DESIGNATOR DESCRIPTION (SIZE) VALUE C1 Capacitor 4.7 nF C2 Capacitor 470 pF C3 Capacitor 0.5 pF C4 Capacitor 3.3 pF MANUFACTURER POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PART NUMBER/COMMENTS 31 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 APPLICATION INFORMATION external component list (5% tolerance unless otherwise noted) for Figure 28 (continued) DESIGNATOR DESCRIPTION (SIZE) VALUE C5 Capacitor 1 nF C6 Capacitor 1 nF C7 Capacitor 100 pF C8 Capacitor 0.1 µF C9 Capacitor 1 pF C15 Capacitor 0.1 µF C17 Capacitor 100 pF C18 Capacitor 100 pF C19 Capacitor 330 pF C20 Capacitor 0.1 µF C21 Capacitor 10 pF C22 Capacitor 10 pF C23 Capacitor 2.7 pF C24 Capacitor 2.7 pF C25 Capacitor 0.1 µF C26 Capacitor 0.1 µF C27 Capacitor 0.1 µF C28 Capacitor 3 pF C29 Capacitor 0.1 µF C30 Capacitor 0.1 µF C31 Capacitor C32 Capacitor 4.7 pF C40 Capacitor 0.1 µF C41 Capacitor 150 pF L1 Coil 4.7 nH Murata LQW1608 L2 Coil 10 nH Murata LQW1608 L3 Coil 8.2 nH Murata LQW1608 L4 Coil 18 nH Murata LQW1608 L7 Coil 2.2 µH Murata LQH1N2RZJ04, 5% tolerance L8 Coil 10 nH Murata LQW1608, 5% tolerance R1 Resistor 10 kΩ R2 Resistor 6.2 kΩ R3 Resistor 100 kΩ R4 Resistor 10 kΩ R5 Resistor 39 kΩ R6 Resistor 1 MΩ R7 Resistor 100 Ω 32 MANUFACTURER PART NUMBER/COMMENTS 1% tolerance Select at test (SAT), Do not place (DNP) Select at test (SAT), Do not place (DNP) R8 Resistor 10 kΩ V1, V2 Varactor diode SMV1247–079 Alpha Industries CQ1 Crystal 25.6 MHz ICM (International Crystal Manufacturing, Incorporated) BPF1 Filter Murata SFECV10.7H-A, 10.7 MHz IF filter, DNP. If not used, replace with 0.1 µF capacitor. BPF2 Filter Murata SFECV10.7H-A, 10.7 MHz IF filter POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 865842 TRF6900 SINGLE-CHIP RF TRANSCEIVER SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000 MECHANICAL DATA PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0°– 7° 0,75 0,45 0,10 4040052 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 This may also be a thermally enhanced plastic package with leads connected to the die pads. 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