CADEKA KH207

www.cadeka.com
KH207
Low Distortion Wideband Op Amp
Features
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General Description
The KH207 is a wideband, low distortion operational
amplifier designed specifically for applications requiring
both high speed and wide dynamic range. Utilizing
a proprietary current feedback architecture, the
KH207 offers performance far superior to that of
conventional voltage feedback op amps.
-80/-85dBc 2nd/3rd HD at 20MHz
-3dB bandwidth of 170MHz
0.1% settling in 22ns
Complete overdrive protection
2400V/µs slew rate
3MΩ input resistance
Output may be current limited
Direct replacement for CLC207
The most attractive feature of the KH207 is its
extremely low distortion: -80/-85dBc 2nd/3rd harmonics
at 20MHz (2Vpp, RL = 200Ω). The KH207 also provides
-3dB bandwidth of 170MHz at a gain of +20, settles to
0.1% in 22ns and slews at a rate of 2400V/µs. The
combination of these features positions the KH207 as
the right choice for high speed applications requiring
exceptional signal purity.
Applications
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Fast, precision A/D conversion
Automatic test equipment
Input/output amplifiers
Photodiode, CCD preamps
High-speed modems, radios
Line drivers
High speed, high resolution A/D and D/A converter
systems requiring low distortion operation will find
the KH207 an excellent choice. Wide dynamic range
systems such as radar and communication receivers
will find that the KH207’s low harmonic distortion and
low noise make it an attractive high speed solution.
The addition of the KH207 to the KH205/206 Series
of high speed operational amplifiers broadens the
selection of features available from which to choose.
The KH205 offers low power operation, the KH206
offers higher drive operation, and the KH207 offers
operation with extremely low distortion, all of which
are pin compatible and overdrive protected.
The KH207 is constructed using thin film resistor/bipolar
transistor technology, and is available in the following
versions:
Bottom View
Internal
Feedback
Case
ground
GND
7
Rf
-VCC
8
9
-VCC
2000Ω
Non-Inverting
Input
10
V+ 6
Inverting
Input
V- 5
Not
Connected
NC 4
Case and
bias ground
Supply
Voltage
+
6
-
6
3
2
1
GND
NC
+VCC
-25°C to +85°C
-55°C to +125°C
KH207AM
-55°C to +125°C
KH207HXC
KH207HXA
-55°C to +125°C
-55°C to +125°C
Collector
Supply
11 Vo
Output
12
Collector
Supply
+VCC
KH207AI
KH207AK
Supply
Voltage
Typical Performance
Gain Setting
Not Connected
Parameter
Pin 8 provides access to a 2000Ω feedback resistor which can be connected to
the output or left open if an external feedback resistor is desired.
12-pin TO-8 can
12-pin TO-8 can, features
burn-in & hermetic testing
12-pin TO-8 can,
environmentally
screened and electrically
tested to MIL-STD-883
SMD#: 5962-9097701HXC
SMD#: 5962-9097701HXA
-20 -50
Units
-3dB bandwidth
220 170 80 220 130 80
rise time
1.7 2.2 4.7 1.7 2.9 4.7
slew rate
2.4 2.4 2.4 2.4 2.4 2.4
settling time (to 0.1%) 22 22 20 21 20 19
MHz
ns
V/ns
ns
+7
+20 +50
-1
REV. 1A January 2004
DATA SHEET
KH207
KH207 Electrical Characteristics
(Av = +20V, VCC = ±15V, RL = 200Ω, Rf = 2kΩ; unless specified)
PARAMETERS
CONDITIONS
Ambient Temperature
KH207AI
+25°C
-25°C
+25°C
+85°C
Ambient Temperature
KH207AK/AM/HXC/HXA
+25°C
-55°C
+25°C
+125°C
FREQUENCY DOMAIN RESPONSE
= -3dB bandwidth
large-signal bandwidth
gain flatness
=
peaking
=
peaking
=
rolloff
group delay
linear phase deviation
Vo <2Vpp
Vo <10Vpp
Vo <2Vpp
0.1 to 35MHz
>35MHz
at 70MHz
to 70MHz
to 50MHz
170
100
>140
>72
>140
>80
0
0
–
3.0 ± .2
0.8
<0.3
<0.8
<0.8
–
<3.0
2.2
4.8
22
24
7
2.4
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.1%
to 0.05%
overshoot
slew rate
2V step
10V step
10V step, note 2
10V step, note 2
5V step
20Vpp at 50MHz
NOISE AND DISTORTION RESPONSE
= 2nd harmonic distortion
= 2Vpp, 20MHz, RL = 200Ω
2Vpp, 20MHz, RL = 100Ω
= 3rd harmonic distortion
= 2Vpp, 20MHz, RL = 200Ω
2Vpp, 20MHz, RL = 100Ω
equivalent input noise
voltage
>100kHz
inverting current
>100kHz
non-inverting current
>100kHz
noise floor
>100kHz
integrated noise
1kHz to 150MHz
integrated noise
5MHz to 150MHz
STATIC, DC PERFORMANCE
* input offset voltage
average temperature coefficient
* input bias current
average temperature coefficient
* input bias current
average temperature coefficient
* power supply rejection ratio
common mode rejection ratio
* supply current
MISCELLANEOUS PERFORMANCE
non-inverting input resistance
non-inverting input capacitance
output impedance
output voltage range
internal feedback resistor
absolute tolerance
temperature coefficient
inverting input current self limit
non-inverting
inverting
no load
DC
70MHz
DC
no load
TYP
MIN & MAX RATINGS
UNITS
SYM
>125
>80
MHz
MHz
SSBW
FPBW
<0.3
<0.5
<0.8
–
<2.0
<0.5
<0.8
<0.8
–
<3.0
dB
dB
dB
ns
°
GFPL
GFPH
GFR
GD
LPD
<2.6
<5.5
<27
<30
<14
>1.8
<2.6
<5.5
<27
<30
<14
>2.0
<3.0
<5.5
<27
<30
<14
>2.0
ns
ns
ns
ns
%
V/ns
TRS
TRL
TS
TSP
OS
SR
-80
-69
-85
-69
<-68
<-64
<-76
<-64
<-76
<-64
<-76
<-64
<-76
<-64
<-76
<-64
dBc
dBc
dBc
dBc
HD2
HD2
HD3
HD3
1.6
20
2.2
-158
33
33
<1.8
<23
<2.5
<-157
<38
<38
<1.8
<23
<2.5
<-157
<38
<38
<1.8
<23
<2.5
<-157
<38
<38
3.5
11
3.0
15
2.0
20
69
60
25
<8.0
<25
<25
<100
<22
<150
>55
>50
<27
<8.0
<25
<15
<100
<10
<150
>55
>50
<27
<11.0
<25
<15
<100
<25
<150
>55
>50
<29
mV
µV/°C
µA
nA/°C
µA
nA/°C
dB
dB
mA
VIO
DVIO
IBN
DIBN
IBI
DIBI
PSRR
CMRR
ICC
3.0
5.0
–
±12
2.0
–
–
2.2
>1.0
<7.0
<0.1
>±11
–
–
–
<3.0
>1.0
<7.0
<0.1
>±11
–
<0.2
-100 ±40
<3.0
>1.0
<7.0
<0.1
>±11
–
–
–
<3.2
MΩ
pF
Ω
V
kΩ
%
ppm/°C
mA
RIN
CIN
RO
VO
RF
RFA
RFTC
ICL
VN
nV/√Hz
ICN
pA/√Hz
pA/√Hz NCN
dBm(1Hz) SNF
µV
INV
µV
INV
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
Recommended Operating Conditions
VCC
Io
common mode input voltage, Vo
VCC
±5V to ±15V
Io
±100mA
common mode input voltage
±(|VCC| -5)V
gain range
+7 to +50, -1 to -50
note 1:
* AI/AK/AM/HXC/HXA 100% tested at +25°C
= AK/AM/HXC/HXA
100% tested at +25°C and sample
tested at -55°C and +125°C
= AI
sample tested at +25°C
note 2:
Settling time specifications require the use of an external
feedback resistor (2kΩ).
±20V
±150mA
|VCC| > 15V ±(29 - |VCC|)V
|VCC| ≤ 15V ±(|VCC| -1)V
differential input voltage
±3V
thermal resistance
(see thermal model)
junction temperature
+175°C
operating temperature
AI: -25°C to +85°C
AK/AM/HXC/HXA: -55°C to +125°C
storage temperature
-65°C to +150°C
lead temperature (soldering 10s)
+300°C
2
REV. 1A January 2004
KH207
DATA SHEET
KH207 Typical Performance Characteristics (TA = +25°C,Av = +20,VCC = ±15V, Rf = 20Ω, RL = 200Ω; unless specified)
Normalized Magnitude (1dB/div)
Inverting Frequency Response
Phase (45°/div)
Gain
Av = +20
Av = +50
Av = +7
Phase
Av = +50
Av = +20
0
20
40
60
80 100 120 140 160 180 200
Av = +50
Av = -1
Gain
Av = -7
Av = -20
Phase
Av = -50
Av = -1
Av = -20
Av = -7
Rf = 3kΩ
Rf = 1.5kΩ
0
20
40
60
Rf = 3kΩ
80 100 120 140 160 180 200
0
20
Rf = 2kΩ
Rf = 3kΩ
40
60
80 100 120 140 160 180 200
Frequency (MHz)
Relative Bandwidth vs. VCC
2
Rf = 1.5kΩ
Av = +7
Frequency (MHz)
Large Signal Gain and Phase
Gain and Phase for Various Loads 2
2
1.0
Vo = 10Vpp
RL = 50Ω
Magnitude (1dB/div)
Phase
RL = 100Ω
Gain
0.8
0.7
0.6
0.5
0.4
RL = 200Ω
RL = 1kΩ
Phase
Phase (45°/div)
Phase (45°/div)
Gain
Relative Bandwidth
0.9
Magnitude (1dB/div)
Rf = 2kΩ
Av = +20
Av = -50
Frequency (MHz)
Rf = 1.5kΩ
Rf = 2kΩ
Relative Gain (5dB/div)
Av = +7
Frequency Response vs. External Rf
Phase (45°/div)
Normalized Magnitude (1dB/div)
Non-Inverting Frequency Response
RL = 1kΩ
RL = 200Ω
RL = 100Ω
RL = 50Ω
0.3
0.2
0
15
30
45
60
75
90 105 120 135 150
4
6
8
Small Signal Pulse Response
12
14
0
16
20
40
Large Signal Pulse Response
2
Av = -20
80 100 120 140 160 180 200
Settling Time
2
2
0.20
10V step
Rf = 2kΩ (external)
0.15
Av = +20
Output Voltage (2V/div)
Av = +20
60
Frequency (MHz)
Settling Error (%)
Output Voltage (0.4V/div)
10
±VCC (V)
Frequency (MHz)
0.10
0.05
0
-0.05
-0.10
-0.15
Av = -20
-0.20
Time (5ns/div)
2nd and 3rd Harmonic Distortion 2
Distortion (dBc)
-50
2nd
-60
-65
-70
-75
-20
-20
-30
-30
16Vpp
-40
8Vpp
-50
-60
4Vpp
-70
2Vpp
-80
-80
3rd
-85
-90
10
100
1
10
2Vpp
-70
100
1
10
45
Interdept Point (dBm)
PSRR
CMRR
40
20
Equivalent Input Noise
2-Tone, 3rd Order Intermod. Intercept
K
40
K
100
100
Pout
50Ω
35
30
25
20
Inverting Current 20pA√Hz
10
10
Non-Inverting Current 2.2pA√Hz
Noise Current (pA√Hz)
80
100
Frequency (MHz)
50Ω
PSRR and CMRR (dB)
-60
Frequency (MHz)
K
4Vpp
8Vpp
-50
1Vpp
Noise Voltage (nV√Hz)
CMRR and PSRR
-40
-90
Frequency (MHz)
100
16Vpp
-80
1Vpp
-90
1
60
Distortion (dBc)
-45
-55
3rd Harmonic Distortion, RL = 100Ω2
2nd Harmonic Distortion, RL = 100Ω
2
-40
Distortion (dBc)
Time (5ns/div)
Time (5ns/div)
Voltage 1.6nV/√Hz
100
1k
10k
100k
1M
10M
100M
2
REV. 1A January 2004
0
10
20
30
40
50
60
70
80
90 100
102
103
104
105
106
107
108
Frequency (Hz)
Frequency (MHz)
Frequency (Hz)
1
1
15
0
K
K
3
DATA SHEET
KH207
Current Feedback Amplifiers
Some of the key features of current feedback technology
are:
n Independence of AC bandwidth and voltage gain
n Adjustable frequency response with feedback resistor
n High slew rate
n Fast settling
Short Circuit Protection
Damage caused by short circuits at the output may be
prevented by limiting the output current to safe levels.
The most simple current limit circuit calls for placing
resistors between the output stage collector supplies and
the output stage collectors (pins 12 and 10). The value
of this resistor is determined by:
Current feedback operation can be described using a simple
equation. The voltage gain for a non-inverting or inverting
current feedback amplifier is approximated by Equation 1.
V
RC = C − RI
II
Vo
Av
=
Vin 1 + R f
Z( jω )
Equation 1
where:
n
n
n
n
where II is the desired limit current and RI is the minimum
expected load resistance (0Ω for a short to ground).
Bypass capacitors of 0.01µF on should be used on the
collectors as in Figures 2 and 3.
Av is the closed loop DC voltage gain
Rf is the feedback resistor
Z(jω) is the CLC205’s open loop transimpedance
gain
n
n
n
n
6
5
+
Vo
Rg
common mode
protection
Figure 1: Diode Clamp Circuits for Common Mode
and Differential Mode Protection
K
11
-
Vo
200Ω
3,7
9
Rf
Rg
Rf = 2000Ω (internal)
33Ω
3.9
A v = 1+
.1
.01
33Ω
+15V
3.9
differential protection
KH207
8
10
-15V
Capactance in µF
.1
50Ω 6
-Vcc
12
KH207
Figure 2: Recommended Non-Inverting Gain Circuit
Overdrive Protection
Unlike most other high-speed op amps, the KH207 is not
damaged by saturation caused by overdriving input
signals (where Vin x gain > max. Vo). The KH207 self
limits the current at the inverting input when the output is
saturated (see the inverting input current self limit
specification); this ensures that the amplifier will not be
damaged due to excessive internal currents during overdrive.
For protection against input signals which would exceed
either the maximum differential or common mode input
voltage, the diode clamp circuits below may be used.
4
1
+
Rg
Decreases loop gain
Decreases bandwidth
Reduces gain peaking
Lowers pulse response overshoot
Affects frequency response phase linearity
+Vcc
.01
Ri
50Ω
Vin
Capactance in µF
.1
Vin
Z( jω )
is the loop gain
Rf
The denominator of Equation 1 is approximately equal to
1 at low frequencies. Near the -3dB corner frequency,
the interaction between Rf and Z(jω) dominates the circuit
performance. The value of the feedback resistor has a
large affect on the circuits performance. Increasing Rf
has the following affects:
n
33Ω
+15V
3.9
Rg 5
Vin
.01
1
+
12
8
11
KH207
Vo
10
-
200Ω
3,7
9
Ri
Av =
33Ω
-15V
3.9
.1
.01
-R f
Rg
Rf = 2000Ω (internal)
For Zin = 50Ω, select Rg||Ri = 50Ω
Figure 3: Recommended Inverting Gain Circuit
A more sophisticated current limit circuit which provides a
limit current independent of RI is shown in Figure 4 on
page 5.
With the component values indicated, current limiting
occurs at 50mA. For other values of current limit (II),
select RC to equal Vbe/lI. Where Vbe is the base to
emitter voltage drop of Q3 (or Q4) at a current of [2VCC –
1.4] / Rx, where Rx ≤ [(2VCC – 1.4) / II] Bmin.
Also, Bmin is the minimum beta of Q1 (or Q2) at a current
of II. Since the limit current depends on Vbe, which is
temperature dependent, the limit current is likewise
temperature dependent.
REV. 1A January 2004
KH207
DATA SHEET
+Vcc
Rc
12Ω
Q3
(2N3906)
Noise Analysis
Approximate noise figure can be determined for the
KH207 using the Equivalent Input Noise plot on page 3
and the equations shown below.
Q1
(MJE170)
kT = 4.00 x 10-21 Joules at 290°K
Vn is spot noise voltage (V/√Hz)
in is non-inverting spot noise current (A/√Hz)
ii is inverting spot noise current (A/√Hz)
0.01ΩF
to pin 12
Rx
14.3kΩ
to pin 10
0.01ΩF
Rs
Q2
(MJE180)
+
Rn
Q4
(2N3904)
Rc
12Ω
Ro
KH207
Rf
Rg
-Vcc
Figure 4: Active Current Limit Circuit (50mA)
Controlling Bandwidth and Passband Response
K
In most applications, a feedback resistor
value of 2kΩ
will provide optimum performance; nonetheless, some
applications may require a resistor of some other value.
The response versus Rf plot on the previous page shows
how decreasing Rf will increase bandwidth (and frequency
response peaking, which may lead to instability).
Conversely, large values of feedback resistance tend to
roll off the response.
The best settling time performance requires the use of an
external feedback resistor (use of the internal resistor
results in a 0.1% to 0.2% settling tail). The settling
performance may be improved slightly by adding a
capacitance of 0.4pF in parallel with the feedback
resistor (settling time specifications reflect performance
with an external feedback resistor but with no external
capacitance).
Thermal Model

R 2f i i2
Rs
R s  2 V n2
F = 10 log  1 +
+
⋅ in +
+

R n 4 kT 
R p2 R p2 A 2v


where R p =
Rs Rn
Rs +Rn
;
Av =
Rf
Rg








+1
Figure 5: Noise Figure Diagram and Equations
(Noise Figure is for the Network Inside this Box.)
Driving Cables and Capacitive Loads
When driving cables, double termination is used to
prevent reflections. For capacitive load applications, a
small series resistor at the output of the KH207 will
improve stability and settling performance.
Transmission Line Matching
One method for matching the characteristic impedance
(Zo) of a transmission line or cable is to place the
appropriate resistor at the input or output of the amplifier.
Figure 6 shows typical inverting and non-inverting circuit
configurations for matching transmission lines.
Tcase
100°C/W
Tj(pnp)
Ppnp
100°C/W
Tj(npn)
Pnpn
17.5°C/W
θca
R1
Z0
R3
Tj(circuit)
Pcircuit
V1 +-
+
Tambient
Pcircuit = [(+VCC) – (-VCC)]2 / 1.77kΩ
Pxxx = [(±VCC) – Vout – (Icol) (Rcol + 6)] (Icol)
(% duty cycle)
(For positive Vo and VCC, this is the power in the npn output stage.)
(For negative Vo and VCC, this is the power in the pnp output stage.)
θca = 65°C/W in still air without a heatsink.
35°C/W in still air without a Thermalloy 2268.
15°C/W in 300ft/min air with a Thermalloy 2268
(Thermalloy 2240 works equally well.)
Icol = Vout/Rload or 3mA, whichever is greater.
(Include feedback R in Rload.)
Rcol is a resistor (33Ω recommended) between the xxx collector and ±VCC.
Tj (pnp) = Ppnp (100 + θca) + (Pcir + Pnpn)θca + Ta, similar for Tj (npn).
R2
R4
V2 +-
Z0
Rg
C6
+
Z0
KH207
-
R6
Vo
R7
Rf
R5
Figure 6: Transmission Line Matching
Non-inverting gain applications:
n
n
n
Connect Rg directly to ground.
Make R1, R2, R6, and R7 equal to Zo.
Use R3 to isolate the amplifier from reactive
loading caused by the transmission line,
or by parasitics.
Tj (cir) = Pcir (17.5 + θca) + (Ppnp + Pnpn)θca + Ta.
REV. 1A January 2004
5
DATA SHEET
Inverting gain applications:
n
n
n
Connect R3 directly to ground.
Make the resistors R4, R6, and R7 equal to Zo.
Make R5 II Rg = Zo.
The input and output matching resistors attenuate the
signal by a factor of 2, therefore additional gain is needed.
Use C6 to match the output transmission line over a
greater frequency range. C6 compensates for the increase
of the amplifier’s output impedance with frequency.
Dynamic Range (Intermods)
For RF applications, the KH207 specifies a third
order intercept of 26dBm at 60MHz and Po = 10dBm. A
2-Tone, 3rd Order IMD Intercept plot is found in the
Typical Performance Characteristics section. The output power level is taken at the load. Third-order harmonic distortion is calculated with the formula:
HD 3rd = 2 • (IP3o – Po)
n
n
n
IP3o = third-order output intercept, dBm at
the load.
Po = output power level, dBm at the load.
HD 3 rd = third-order distortion from the
fundamental, -dBc.
dBm is the power in mW, at the load,
expressed in dB.
Realized third-order output distortion is highly
dependent upon the external circuit. Some of the
common external circuit choices that improve 3rd order
distortion are:
n
n
n
n
6
Printed Circuit Layout
As with any high frequency device, a good PCB layout
will enhance the performance of the KH207. Good
ground plane construction and power supply bypassing
close to the package are critical to achieving full performance. In the non-inverting configuration, the amplifier is
sensitive to stray capacitance to ground at the inverting
input. Hence, the inverting node connections should be
small with minimal stray capacitance to the ground plane
or other nodes. Shunt capacitance across the feedback
resistor should not be used to compensate for this effect.
General layout and supply bypassing play major roles in
high frequency performance. Follow the steps below as
a basis for high frequency layout:
n
n
n
where:
n
KH207
short and equal return paths from the load
to the supplies.
de-coupling capacitors of the correct value.
higher load resistance.
a lower ratio of the output swing to the
power supply voltage.
n
n
n
Include 6.8µF tantalum and 0.1µF ceramic
capacitors on both supplies.
Place the 6.8µF capacitors within 0.75
inches of the power pins.
Place the 0.1µF capacitors less than 0.1
inches from the power pins.
Remove the ground plane under and
around the part, especially near the input
and output pins to reduce parasitic
capacitance.
Minimize all trace lengths to reduce series
inductances.
Use flush-mount printed circuit board pins
for prototyping, never use high profile DIP
sockets.
An evaluation PC board (part number 730009) for the
KH207 is available to aid in device testing.
REV. 1A January 2004
DATA SHEET
KH207
KH207 Package Dimensions
L
A
e1
e2
7
φD
e
D1
8
9
6
10
5
11
4
12
k
φb
3
2
1
α
F
k1
TO-8
SYMBOL
INCHES
Minimun
MILIMETERS
Maximum
Minimum
Maximum
A
0.142
0.181
3.61
4.60
φb
0.016
0.019
0.41
0.48
φD
0.595
0.605
15.11
15.37
φD1
0.543
0.555
13.79
14.10
e
0.400 BSC
10.16 BSC
e1
0.200 BSC
5.08 BSC
e2
0.100 BSC
2.54 BSC
F
0.016
0.030
0.41
0.76
k
0.026
0.036
0.66
0.91
k1
0.026
0.036
0.66
0.91
L
0.310
0.340
7.87
8.64
α
45° BSC
NOTES:
Seal: cap weld
Lead finish: gold per MIL-M-38510
Package composition:
Package: metal
Lid: Type A per MIL-M-38510
45° BSC
Life Support Policy
Cadeka’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Cadeka Microcircuits, Inc.
As used herein:
1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used
in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect
its safety or effectiveness.
Cadeka does not assume any responsibility for use of any circuitry described, and Cadeka reserves the right at any time without notice to change said circuitry and specifications.
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© 2004 Cadeka Microcircuits, LLC