N CLC446 400MHz, 50mW Current-Feedback Op Amp General Description Features The National CLC446 is a very high-speed unity-gain-stable current-feedback op amp that is designed to deliver the highest levels of performance from a mere 50mW quiescent power. It provides a very wide 400MHz bandwidth, a 2000V/µs slew rate and 900ps rise/fall times. The CLC446 achieves its superior speedvs-power using an advanced complementary bipolar IC process and National’s current-feedback architecture. ■ The CLC446 is designed to drive video loads with very low differential gain and phase errors (0.02%, 0.03°). Combined with its very low power (50mW), the CLC446 makes an excellent choice for NTSC/PAL video switchers and routers. With its very quick edge rates (900ps) and high slew rate (2000V/µs), the CLC446 also makes an excellent choice for high-speed, highresolution component RGB video systems. Applications ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The CLC446 makes an excellent low-power high-resolution A/D converter driver with its very fast 9ns settling time (to 0.1%) and low harmonic distortion. High resolution video A/D driver Medical imaging Video switchers & routers RF/IF amplifier Communications Instrumentation Non-Inverting Frequency Response (Av = +2) 8 Vo = 0.5Vpp 6 Gain (dB) The combination of high performance and low power make the CLC446 useful in many high-speed general purpose applications. Its current-feedback architecture maintains consistent performance over a wide gain range and signal levels. DC gain and bandwidth can be set independently. Also, either maximally flat AC response or linear phase response can be emphasized. 400MHz bandwidth (Av = +2) 5mA supply current 0.02%, 0.03° differential gain, phase 2000V/µs slew rate 9ns settling to 0.1% 0.05dB gain flatness to 100MHz -65/-78dBc HD2/HD3 CLC446 400MHz, 50mW Current-Feedback Op Amp November 1998 4 2 0 -2 1M 10M 100M 1G Frequency (Hz) Typical Application Pinout Elliptic-Function Low Pass Filter R1 R2 DIP & SOIC C1 Vin VCC + C3 C4 C2 R4 CLC446 - Vo R5 C5 VEE R3 Rg © 1998 National Semiconductor Corporation Printed in the U.S.A. Rf http://www.national.com Electrical Characteristics (AV = +2, Rf = 249Ω: VCC = + 5V, RL = 100Ω; unless specified) PARAMETERS Ambient Temperature CONDITIONS CLC446AJ TYP +25˚C MIN/MAX RATINGS +25˚C 0 to 70˚C -40 to 85˚C UNITS FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vo < 0.2Vpp Vo < 2.0Vpp gain flatness Vo < 2.0Vpp <100MHz linear phase dev. Vo < 2.0Vpp <100MHz differential gain NTSC, RL=150Ω differential phase NTSC, RL=150Ω 400 280 ±0.05 0.2 0.02 0.03 340 210 ±0.2 0.5 0.04 0.05 300 190 ±0.2 0.8 0.04 0.05 300 190 ±0.2 0.8 0.04 0.05 MHz MHz dB deg % deg TIME DOMAIN RESPONSE rise and fall time settling time to 0.1% overshoot slew rate 0.9 9 6 2000 1.4 13 15 1400 1.5 15 18 1300 1.6 15 18 1200 ns ns % V/µs -65 -55 -54 -78 -70 -50 -59 -48 -43 -70 -62 -45 -58 -48 -42 -68 -60 -42 -58 -48 -42 -68 -60 -42 dBc dBc dBc dBc dBc dBc 3.8 2.0 16 4.8 2.6 19 5.0 2.8 20 5.1 3.3 21 nV/√Hz pA/√Hz pA/√Hz 2 17 3 30 10 26 52 48 4.8 7 – 12 – 22 – 45 44 5.8 10 25 25 90 30 75 43 42 6.2 11 35 25 130 35 85 43 42 6.2 mV µV/˚C µA nA/˚C µA nA/˚C dB dB mA 1.5 1 ±2.8 ±3.1 ±3.2 48 0.04 1.0 2 ±2.6 ±2.8 ±3.0 48 0.1 0.85 2 ±2.4 ±2.8 ±2.9 48 0.1 0.70 2 ±2.3 ±2.6 ±2.8 48 0.1 MΩ pF V V V mA Ω 2V step 2V step 2V step 2V step, ±0.5V crossing DISTORTION AND NOISE RESPONSE 2Vpp, 5MHz 2nd harmonic distortion 2Vpp, 20MHz 2Vpp, 50MHz 3rd harmonic distortion 2Vpp, 5MHz 2Vpp, 20MHz 2Vpp, 50MHz equivalent input noise voltage (eni) >1MHz non-inverting current (ibn) >1MHz inverting current (ibi) >1MHz STATIC DC PERFORMANCE input offset voltage average drift input bias current average drift input bias current average drift power supply rejection ratio common-mode rejection ratio supply current non-inverting inverting DC DC RL= ∞ MISCELLANEOUS PERFORMANCE input resistance non-inverting input capacitance non-inverting input range common-mode output voltage range RL = 100Ω RL = ∞ output current output resistance, closed loop DC NOTES A A A A Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Ordering Information Absolute Maximum Ratings supply voltage output current common-mode input voltage maximum junction temperature storage temperature range lead temperature (soldering 10 sec) ESD rating (human body model) ±6V ±48mA ±Vcc +175˚C -65˚C to +150˚C +300˚C 1000V Model Temperature Range Description CLC446AJP -40˚C to +85˚C 8-pin PDIP CLC446AJE -40˚C to +85˚C 8-pin SOIC CLC446ALC -40˚C to +85˚C dice CLC446A8B -55˚C to +125˚C 8-pin CerDIP, MIL-STD-883 CLC446AMC -55˚C to +125˚C dice, MIL-STD-883 Contact the factory for other packages and DESC SMD number. Package Thermal Resistance Notes A) J-level: spec is 100% tested at +25˚C. θJC θJA 70˚C/W 60˚C/W 40˚C/W 125˚C/W 140˚C/W 130˚C/W Package Plastic (AJP) Surface Mount (AJE) Ceramic (A8B) Reliability Information Transistor Count MTBF (based on limited test data) http://www.national.com 2 36 39Mhr Typical Performance Characteristics (VCC = ±5V,Av = +2,Rf =249ΩΩ, RL = 100ΩΩ; unless specified) 0 -90 Av = 10V/V Rf = 200Ω -180 -270 Av = 5V/V Rf = 200Ω -360 -450 10M 100M 1G -180 -225 1M 10M -360 RL = 1kΩ 0 -90 0.1Vpp 1Vpp 4Vpp 2Vpp 100M -360 -450 10M 100M 1G Frequency (Hz) Recommended Rs vs. CL CL = 10pF Rs = 46.4Ω 40 CL = 22pF Rs = 33.2Ω CL = 47pF Rs = 21Ω + - 249Ω 30 20 CL = 100pF Rs = 13.3Ω Rs CL 10 1k 249Ω 0 10M 100M 1G 10 20 30 40 50 Frequency (Hz) Frequency (Hz) 60 70 80 100 90 CL(pF) Large Signal Pulse Response Small Signal Pulse Response -270 RL = 500Ω 50 1M 1G -180 RL = 100Ω 1M 1G 100M Frequency Response vs. CL Normalized Magnitude (1dB/div) Normalized Magnitude (1dB/div) -315 Vo = 0.5Vpp Frequency (Hz) Frequency Response vs. Vo 10M -270 Av = -5V/V Rf = 200Ω Av = -10V/V Rf = 200Ω Frequency (Hz) 1M Av = -2V/V Rf = 249Ω Rs(Ω) 1M Av = -1V/V Rf = 249Ω Normalized Magnitude (1dB/div) Normalized Magnitude (1dB/div) Av = 2V/V Rf = 249Ω Vo = 0.5Vpp Phase (deg) Av = 1V/V Rf = 453Ω Frequency Response vs. RL Inverting Frequency Response Phase (deg) Vo = 0.5Vpp Phase (deg) Normalized Magnitude (1dB/div) Non-Inverting Frequency Response Equivalent Input Noise Av = -2V/V Voltage Noise (nV/√Hz) Output Voltage (1V/div) Av = +2V/V Av = +2V/V Av = -2V/V 100 ibi 10 10 eni ibn 1 Time (2ns/div) Time (2ns/div) Current Noise (pA/√Hz) Output Voltage (0.5V/div) 100 1k 10k 100k 1M 10M 1 100M Frequency (Hz) 3rd Harmonic Distortion 2nd Harmonic Distortion -50 -80 2nd RL = 1kΩ -70 3rd RL = 100Ω -80 -90 -90 Differential Gain (%) Distortion (dBc) 3rd RL = 1kΩ -0.08 -0.01 Phase Neg Sync Gain Pos Sync -0.02 -0.12 -0.03 10M 1M 10M 1M -0.16 Gain Neg Sync -0.2 1 2 Frequency (Hz) Frequency (Hz) 3 4 Number of 150Ω Loads 3rd Harmonic Distortion vs. Pout 2nd Harmonic Distortion vs. Pout -0.04 -0.04 -100 -100 0 Vos, IBN, & IBI vs. Temperature -65 -40 -70 5MHz -60 2MHz -70 1MHz Vos -75 5MHz -80 2MHz -85 0 2 4 6 8 Output Power (dBm) -2 IBN -6 0 1MHz IBI -95 -2 1 -90 -80 -4 2 2 10MHz 10 12 IBI, IBN(µA) Distortion (dBc) 10MHz -50 Vos (mV) Distortion (dBc) 2nd RL = 100Ω Phase Pos Sync Differential Phase (deg) -60 -70 0 0.01 Vo = 2Vpp -60 Distortion (dBc) Differential Gain and Phase (3.58MHz) -50 Vo = 2Vpp -10 -1 -4 -2 0 2 4 6 8 Output Power (dBm) 3 10 12 -60 -40 -20 0 20 40 60 80 Temperature (°C) http://www.national.com Typical Performance Characteristics (VCC = ±5V, Av = +2, Rf = 249ΩΩ, RL = 100ΩΩ; Long Term Settling Time Short Term Settling Time 0.2 0.2 VO = 2V step Vo (% Output Step) VO = 2V step Vo (% Output Step) unless specified) 0.1 0 -0.1 0.1 0 -0.1 -0.2 -0.2 1n 10n 100n 1µ 1µ 10µ 10µ 100µ 1m 10m 100m 1 Time (s) Time (sec) CLC446 Operation The CLC446 has a current-feedback architecture built in an advanced complementary bipolar process. The key features of current-feedback are: ■ ■ ■ ■ ■ ■ where ■ ■ AC bandwidth is independent of voltage gain Unity-gain stability Frequency response may be adjusted with Rf High slew rate Low variation in performance for a wide range of gains, signal levels and loads Fast settling ■ ■ The denominator of the equation above is approximately 1 at low frequencies. Near the -3dB corner frequency, the interaction between Rf and Z(jω) dominates the circuit performance. Increasing Rf does the following: Current-feedback operation can be explained with a simple model. The voltage gain for the circuits in Figures 1 and 2 is approximately: Vo = Vin Av is the DC voltage gain Rf is the feedback resistor Z(jω) is the CLC446’s open-loop transimpedance gain Z( jω ) is the loop-gain Rf ■ ■ Av Rf 1+ Z( jω ) ■ ■ ■ Decreases loop-gain Decreases bandwidth Lowers pulse response overshoot Reduces gain peaking Affects frequency response phase linearity CLC446 Design Information The following topics will supply you with: ■ ■ ■ ■ ■ Select Rg to set the DC gain: R g = Design parameters, formulas and techniques Interfaces Application circuits Layout techniques SPICE model information Rf . Av − 1 DC gain accuracy is usually limited by the tolerance of Rf and Rg. VCC 6.8µF + DC Gain (non-inverting) The non-inverting DC voltage gain for the configuration shown in Figure 1 is A v = 1 + Vin Rf . Rg Rt The normalized gain plots in the Typical Performance Characteristics section show different feedback resistors (Rf) for different gains. These values of Rf are recommended for obtaining the highest bandwidth with minimal peaking. The resistor Rt provides DC bias for the non-inverting input. + 7 0.1µF CLC446 2 - 4 6 Vo Rf 0.1µF Rg + 6.8µF VEE For Av < 5, use linear interpolation on the nearest Av values to calculate the recommended value of Rf. For Av ≥ 5, the minimum recommended Rf is 200Ω. http://www.national.com 3 Fi Figure 1: Non-Inverting Gain 4 VCC DC Gain (unity gain buffer) The recommended Rf for unity gain buffers is 453Ω. Rg is left open. Parasitic capacitance at the inverting node may require a slight increase of Rf to maintain a flat frequency response. 6.8µF + Rt 3 + 0.1µF 7 2 - Rf 4 0.1µF Iin + VCC 6.8µF 6.8µF + Rt 3 + 7 Vin Rg - 4 VEE Figure 3: Transimpedance Gain 0.1µF Vo 6 CLC446 2 Vo 6 CLC446 DC Gain (inverting) The inverting DC voltage gain for the configuration R shown in Figure 2 is A v = − f . Rg DC Design (level shifting) Figure 4 shows a DC level shifting circuit for inverting gain configurations. Vref produces a DC output level Rf 0.1µF shift of − Vref ⋅ + Rf , which is independent of the DC Rref output produced by Vin. 6.8µF VEE Rt Figure 2: Inverting Gain The normalized gain plots in the Typical Performance Characteristics section show different feedback resistors (Rf) for different gains. These values of Rf are recommended for obtaining the highest bandwidth with minimal peaking. The resistor Rt provides DC bias for the non-inverting input. Rf . Av Vin Rg Vref Rref At large Rf VCC VCC R1 Vin + C1 DC gain accuracy is usually limited by the tolerance of Rf and Rg. Vo CLC446 R2 Rf DC Gain (transimpedance) Figure 3 shows a transimpedance circuit where the current Iin is injected at the inverting node. The current source’s output resistance is much greater than Rf. AR = - DC Design (single supply) Figure 5 is a typical single-supply circuit. R1 and R2 form a voltage divider that sets the non-inverting input DC voltage. This circuit has a DC gain of 1. A low frequency zero is set by Rg and C2. The coupling capacitor C1 isolates its DC bias point from the previous stage. Both capacitors make a high pass response; high frequency gain is determined by Rf and Rg. gains, Rg becomes small and will load the previous stage. This can be solved by driving Rg with a low impedance buffer like the CLC111, or increasing Rf and Rg. See the AC Design (small signal bandwidth) sub-section for the tradeoffs. The DC transimpedance gain is: Vo Figure 4: Level Shifting Circuit For |Av| < 5, use linear interpolation on the nearest Av values to calculate the recommended value of Rf. For |Av| ≥ 5, the minimum recommended Rf is 200Ω. Select Rg to set the DC gain: R g = + CLC446 Rg C2 Figure 5: Single Supply Circuit Vo = − Rf Iin The complete gain equation for the circuit in Figure 5 is: The recommended Rf is 453Ω. Parasitic capacitance at the inverting node may require a slight increase of Rf to maintain a flat frequency response. R 1 + sτ 2 ⋅ 1 + f Rg sτ1 Vo = ⋅ Vin 1 + sτ1 1 + sτ 2 DC gain accuracy is usually limited by the tolerance of Rf. 5 http://www.national.com The slew rate of the CLC446 in inverting gains is always higher than in non-inverting gains. where s = jω ( ) τ1 = R1 R 2 ⋅ C1 AC Design (linear phase/constant group delay) The recommended value of Rf produces minimal peaking and a reasonably linear phase response. To improve phase linearity when |Av| < 5, increase Rf approximately 50% over its recommended value. Some adjustment of Rf may be needed to achieve phase linearity for your application. See the AC Design (small signal bandwidth) sub-section for other effects of changing Rf. τ 2 = Rg ⋅ C2 DC Design (DC offsets) The DC offset model shown in Figure 6 is used to calculate the output offset voltage. The equation for output offset voltage is: Rf Vo = − Vos + IBN ⋅ Req1 ⋅ 1 + + (IBI ⋅ R f ) Req2 ( ) Propagation delay is approximately equal to group delay. Group delay is related to phase by this equation: The current offset terms, IBN and IBI , do not track each other. The specifications are stated in terms of magnitude only. Therefore, the terms Vos, IBN, and IBI can have either polarity. Matching the equivalent resistance seen at both input pins does not reduce the output offset voltage. τ gd = (f) = − ∆φ(f) 1 dφ(f) ⋅ ≈− 360° df ∆f where φ(f) is the phase in degrees. Linear phase implies constant group delay. The technique for achieving linear phase also produces a constant group delay. IBN + + Vos CLC446 IBI Rf Req1 AC Design (peaking) Peaking is sometimes observed with the recommended Rf. If a small increase in Rf does not solve the problem, then investigate the possible causes and remedies listed below. Vo RL Req2 ■ Figure 6: DC Offset Model ■ DC Design (output loading) RL, Rf, and Rg load the op amp output. The equivalent load seen by the output in Figure 6 is: RL(eq) = RL || (Rf + Req2), non-inverting gain RL(eq) = RL || Rf, inverting gain ■ RL(eq) needs to be large enough so that the minimum output current can produce the required output voltage swing. For non-inverting and transimpedance gain configurations: ■ AC Design (small signal bandwidth) The CLC446 current-feedback amplifier bandwidth is a function of the feedback resistor (Rf), not of the DC voltage gain (AV). The bandwidth is approximately proportional to 1 . As a rule, if Rf doubles, the bandRf Extra capacitance between the inverting pin and ground (Cg) ■ See the Printed Circuit Board Layout subsection below for suggestions on reducing Cg ■ Increase Rf if peaking is still observed after reducing Cg For inverting gain configurations: ■ width is cut in half. Other AC specifications will also be degraded. Decreasing Rf from the recommended value increases peaking, and for very small values of Rf oscillation will occur. AC Design (minimum slew rate) Slew rate influences the bandwidth of large signal sinusoids. To determine an approximate value of slew rate necessary to support a large sinusoid, use the following equation: Inadequate ground plane at the non-inverting pin and/or long traces between non-inverting pin and ground ■ Place a 50 to 200Ω resistor between the noninverting pin and ground (see Rt in Figure 2) Capacitive Loads Capacitive loads, such as found in A/D converters, require a series resistor (Rs) in the output to improve settling performance. The Recommended R s vs. C L plot in the Typical Performance Characteristics section provides the information for selecting this resistor. SR ≅ 5 • f • Vpeak where Vpeak is the peak output sinusoidal voltage. http://www.national.com Capacitance across Rf ■ Do not place a capacitor across Rf ■ Use a resistor with low parasitic capacitance for Rf A capacitive load ■ Use a series resistor between the output and a capacitive load (see the Recommended Rs vs. CL plot) Long traces and/or lead lengths between Rf and the CLC446 ■ Keep these traces as short as possible 6 Using a resistor in series with a reactive load will also reduce the load’s effect on amplifier loop dynamics. For instance, driving coaxial cables without an output series resistor may cause peaking or oscillation. may exceed the supply voltages, we recommend using diode clamps at the amplifier’s input to limit the signals to less than the supply voltages. Dynamic Range (input /output levels) The Electrical Characteristics section specifies the Common-Mode Input Range and Output Voltage Range; these voltage ranges scale with the supplies. Output Current is also specified in the Electrical Characteristics section. Transmission Line Matching One method for matching the characteristic impedance of a transmission line is to place the appropriate resistor at the input or output of the amplifier. Figure 7 shows the typical circuit configurations for matching transmission lines. R1 Z0 V1 +- R2 R4 V2 +- R3 Z0 Rg Unity gain applications are limited by the Common-Mode Input Range. At greater non-inverting gains, the Output Voltage Range becomes the limiting factor. Inverting gain applications are limited by the Output Voltage Range. For transimpedance gain applications, the sum of the input currents injected at the inverting C6 + Z0 CLC446 - R6 Vo R7 Rf R5 input pin of the op amp needs to be: Iin ≤ Figure 7: Transmission Line Matching Vmax , Rf where Vmax is the Output Voltage Range (see the DC Gain (transimpedance) sub-section for details). In non-inverting gain applications, Rg is connected directly to ground. The resistors R1, R2, R6, and R7 are equal to the characteristic impedance, Zo, of the transmission line or cable. Use R3 to isolate the amplifier from reactive loading caused by the transmission line, or by parasitics. The equivalent output load needs to be large enough so that the minimum output current can produce the required output voltage swing. See the DC Design (output loading) sub-section for details. Dynamic Range (noise) In RF applications, noise is frequently specified as Noise Figure (NF). This allows the calculation of signal to noise ratio into a defined load. Figure 8 plots the NF for a CLC446 at a gain of 10, and with a feedback resistor Rf of 100Ω. The minimum NF (3.9dB) occurs when the source impedance equals 1600Ω. In inverting gain applications, R3 is connected directly to ground. The resistors R4, R6, and R7 are equal to Zo. The parallel combination of R5 and Rg is also equal to Zo. The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. Use C6 to match the output transmission line over a greater frequency range. It compensates for the increase of the op amp’s output impedance with frequency. 20 Noise Figure (dB) Thermal Design To calculate the power dissipation for the CLC446, follow these steps: 1. Calculate the no-load op amp power: Pamp = ICC • (VCC – VEE) 2. Calculate the output stage’s RMS power: Po = (VCC – Vload) • Iload, where Vload and Iload are the RMS voltage and current across the external load. 3. Calculate the total op amp RMS power: Pt = Pamp + Po 15 10 5 0 10 1k 100 100k 10k Source Resistance (Ω) Figure 8: Noise Figure vs. Source Resistance To calculate the maximum allowable ambient temperature, solve the following equation: Tamb = 175 – Pt • θJA, where θJA is the thermal resistance from junction to ambient in °C/W, and Tamb is in °C. The Package Thermal Resistance section contains the thermal resistance for various packages. Rs Vs +- eni2 + ibn2 Vo CLC446 - Rf Rg ibi2 Dynamic Range (input /output protection) ESD diodes are present on all connected pins for protection from static voltage damage. For a signal that Figure 9: Noise Model 7 http://www.national.com The CLC446 noise model in Figure 9 is used to develop this equation for NF: ( ■ ) 2 2 2 eni + (ibnR s ) + 4kTRs + ibi ⋅ R f R g + 4kT ⋅ R f R g NF = 10log 4kTRs Evaluation Board Separate evaluation boards are available for prototyping and measurements. Additional information is available in the evaluation board literature. where: ■ ■ ■ ■ ■ RS is the source resistance at the noninverting input There is no matching resistor from the input to ground eni, ibn, and ibi are the voltage and current noise density terms (see the Electrical Characteristics section) ( CLC446 Applications Low Noise Composite Amp With Input Matching The composite amp shown in Figure 10 eliminates the need for a matching resistor to ground at the input. By connecting two amplifiers in series, the first noninverting and the second inverting, an overall inverting gain is realized. The feedback resistor (Rf) closes the loop, and generates a set input resistance (Rin) that can be matched to RS. Rf generates less noise than a matching resistor to ground at the input. ) T 4kT = 16.0 x 10 −21J ⋅ , T is in °K 290°K Rf is the feedback resistor, and Rg is the gain-setting resistor Rf To achieve a low Noise Figure while matching the source, use a matching transformer or the Low Noise Composite Amp With Input Matching circuit found in the CLC446 Applications section. Vs +- ■ ■ ■ ■ ■ Rg2 CLC446 - - CLC446 Vo + 20Ω Figure 10: Composite Amplifier The input resistance and DC voltage gain of the amplifier are: Rf R R Rin = , where G = 1 + f1 ⋅ f2 1+ G R g1 R g2 Short and equal return paths from the load to the supplies De-coupling capacitors of the correct value Higher load resistance A lower ratio of the output voltage swing to power supply voltage Rin Vo = − G⋅ Vs Rin + R s Match the source resistance by setting: Rin = RS. The voltage noise produced by Rf, referred to the source VS, is: Rs eRf 2 = 4kTRs ⋅ Rin ⋅ (1 + G) The noise of a simple input matching resistor connected to ground can be calculated by setting G to 0 in this equation. Thus, this circuit reduces the thermal noise power produced by the matching resistor by a factor of (1+G). Use a ground plane Bypass power supply pins with: ■ ceramic capacitors of about 0.1µF placed less than 0.1" (3mm) from the pin ■ tantalum capacitors of about 6.8µF for large signal current swings or improved power supply noise rejection; we recommend a minimum of 2.2µF for any circuit Minimize trace and lead lengths for components between the inverting and output pins Remove ground plane underneath the amplifier package and 0.1" (3mm) from all input/output pads http://www.national.com Rs Rg1 Printed Circuit Board Layout High Frequency op amp performance is strongly dependent on proper layout, proper resistive termination and adequate power supply decoupling. The most important layout points to follow are: ■ + Rf1 Realized output distortion is highly dependent upon the external circuit. Some of the common external circuit choices that can improve distortion are: ■ Rf2 Rin Dynamic Range (distortion) The distortion plots in the Typical Performance Characteristics section show distortion as a function of load resistance, frequency, and output amplitude. Distortion places an upper limit on the CLC446’s dynamic range. ■ For prototyping, use flush-mount printed circuit board pins; never use high profile DIP sockets Rectifier Circuit Wide bandwidth rectifier circuits have many applications. Figure 11 shows a 200MHz wideband full-wave rectifier circuit using a CLC446 and a CLC522 amplifier. Schottky or PIN diodes are used for D1 and D2. They produce an active half-wave rectifier whose signals are taken at the feedback diode connection. The CLC522 takes the difference of the two half-wave rectified signals, producing a full-wave rectifier. The CLC522 is used at a gain of 5 to achieve high differential bandwidth. For best 8 high frequency performance, maintain low parasitic capacitance from the diodes D1 and D2 to ground, and from the input of the CLC522 to ground. Vin 3 + CLC446 Rin 50Ω 6 2 - Vg 500Ω Rf 800Ω 3 250Ω 3. Denormalize the frequency by multiplying by the cutoff frequency (ωo) in radians/second. For our filter we have: Cutoff frequency: ωo = 2π(10MHz) = 62.832 x 106rad/s Pole 1: α' = ωoα = 24.266 x 106rad/s Pole 2: αo' = ωoαo = 55.712 x 106rad/s Zero 1: β' = ωoβ = 21.052 x 106rad/s Zero 2: ω∞ ' = ωoω∞ = 71.564 x 106rad/s 250Ω D1 250Ω D2 R1 50Ω 2 + 12 Rg 4 10 CLC522 162Ω 5 9 Ro 50Ω Vo 4. Calculate these intermediate coefficients used in Reference [2]. 6 20Ω c= R2 50Ω (α')2 + (β')2 a= 2α' c b= ω' ∞ c 2 For this design, a = 0.64226, b = 7.7612 and c = 75.556 x 106. Figure 11: Full-Wave Rectifier 5. Set the following resistance and capacitance scaling factors: R = an arbitrary value C = an arbitrary value We chose C = 47pF and R = 1.00kΩ. Elliptic Low-pass, Anti-aliasing Filter Elliptic filters are often used in anti-aliasing applications. If there is noise or undesired signals at frequencies above 1/2 the sampling rate of an A/D converter, then these signals are aliased down into the operating frequency range, degrading the signal of interest. To filter out these undesired signal components, place a low pass filter in front of the A/D converter. 6. Calculate the capacitor, resistor and gain (K) values using these equations: C1 = C The Typical Application depicted on the front page is a 10MHz, third-order elliptic filter. It has a voltagecontrolled, voltage source (VCVS) topology using a CLC446. To calculate the component values for this filter, do the following: C 2 C (b − 1) C2 ≥ 4 1 R3 = cC b C3 = C4 = 1. Select the filter approximation function for your application (see References [1-2]). For this design we chose: Filter type = Elliptic Filter order (n) = 3 Passband ripple = 0.18dB Mininimum stopband attenuation (Amin) = 37.44dB Cuttoff frequency = 10MHz (at 0.18dB attenuation) These choices produce the following results: -3dB frequency = 12.7MHz Stopband corner frequency = 29.3MHz R1 = R 2 = R4 = R3 2 4 b cC (1 − b) + 4cC2 R5 = R C5 = 1 Rα' o K = 2+ 2. Find the pole and zero locations. Reference [1] gave the following for our filter: Pole 1: α = 0.38621 Pole 2: αo = 0.88668 Zero 1: β = 1.13897 Zero 2: ω∞ = 3.3505 2C2 a 2 − + C 2 b C b 1 ⋅ − aC2 cR 4 For this design, the calculated values are: C1 = 47pF, C2 = 91pF, C3 = C4 = 23.5pF, C5 = 17.95pF, R1 = R2 = 202.1Ω, R3 = 101.1Ω, R4 = 3190Ω, R5 = 1000Ω and K = 4.928. 7. Select the feedback resistor (Rf) and gainsetting resistor (Rg) values to obtain a noninverting voltage gain of Av = K. See the DC Gain (non-inverting) sub-section for details on selecting these values. 9 http://www.national.com References: [1] Anatol I. Zverev, Handbook of FILTER SYNTHESIS, John Wiley & Sons, 1967, p. 177 [2] Arthur B. Williams and Fred J. Taylor, Electronic Filter Design Handbook, McGraw Hill, 1995, pp. 3-29 to 3-31. Figure 12 shows the ideal response of this filter. Some methods to bring actual performance closer to this ideal are: ■ ■ ■ ■ Compensate for op amp delay effects (pre-distortion) Adjust for parasitic capacitances in the layout Use components with small tolerances Add trim capacitors 20 Gain (dB) 10 0 -10 -20 -30 -40 1M 10M 100M 1G Frequency (Hz) Figure 12: Ideal Elliptic Filter Frequency Response http://www.national.com 10 This page intentionally left blank. 11 http://www.national.com CLC446 400MHz, 50mW Current-Feedback Op Amp Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. Life Support Policy National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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