CLC449 1.1GHz Ultra Wideband Monolithic Op Amp General Description Features The CLC449 is an ultra high speed monolithic op amp, with a typical −3dB bandwidth of 1.1GHz at a gain of +2. This wideband op amp supports rise and fall times less than 1ns, settling time of 6ns (to 0.2%) and slew rate of 2500V/µs. The CLC449 achieves 2nd harmonic distortion of −68dBc at 5MHz at a low supply current of only 12mA. These performance advantages have been achieved through improvements in National’s proven current feedback topology combined with a high speed complementary bipolar process. The DC to 1.2GHz bandwidth of the CLC449 is suitable for many IF and RF applications as a versatile op amp building block for replacement of AC coupled discrete designs. Operational amplifier functions such as active filters, gain blocks, differentiation, addition, subtraction and other signal conditioning functions take full advantage of the CLC449’s unity-gain stable closed-loop performance. The CLC449 performance provides greater headroom for lower frequency applications such as component video, high resolution workstation graphics, and LCD displays. The amplifier’s 0.1dB gain flatness to beyond 200MHz, plus 0.8ns (2V step) rise and fall times are ideal for improved time domain performance. In addition, the 0.03%/0.02˚ differential gain/phase performance allows system flexibility for handling standard NTSC and PAL signals. In applications using high speed flash A/D and D/A converters, the CLC449 provides the necessary wide bandwidth (1.1GHz), settling (6ns to 0.02%) and low distortion into 50Ω loads to improve SFDR. n n n n n n n n 1.1GHz small-signal bandwidth (Av =+2) 2500V/µs slew rate 0.03%, 0.02˚ DG, DΦ 6ns settling time to 0.2% 3rd order intercept, 30dBm @ 70MHz Dual ± 5V or single 10V supply High output current: 80mA 2.5dB noise figure Applications n n n n n n n High performance RGB video RF/IF amplifier Instrumentation Medical electronics Active filters High speed A/D driver High speed D/A buffer Frequency Response (AV = +2V/V) DS012715-1 Connection Diagram DS012715-3 Pinout DIP & SOIC © 2001 National Semiconductor Corporation DS012715 www.national.com CLC449 1.1GHz Ultra Wideband Monolithic Op Amp February 2001 CLC449 Typical Application DS012715-2 120MSPS High Speed Flash ADC Driver Ordering Information Package Temperature Range Industrial Part Number Package Marking NSC Drawing 8-pin plastic DIP −40˚C to +85˚C CLC449AJP CLC449AJP N08E 8-pin plastic SOIC −40˚C to +85˚C CLC449AJE CLC449AJE M08A www.national.com 2 Storage Temperature Range Lead Solder Duration (+300˚C) ESD (human body model) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) IOUT is short circuit protected to ground Common Mode Input Voltage Maximum Junction Temperature Operating Temperature Range −65˚C to +150˚C 10 sec 500V Operating Ratings ± 6V Thermal Resistance Package MDIP SOIC ± VCC +150˚C −40˚C to +85˚C (θJC) 90˚C/W 110˚C/W (θJA) 105˚C/W 130˚C/W Electrical Characteristics AV = +2, VCC = ± 5V, RL = 100Ω, Rf = 250Ω; unless specified Symbol Parameter Ambient Temperature Conditions Typ CLC449AJ +25˚C < 0.2VPP < 2.0VPP < 2.0VPP 1100 Min/Max (Note 2) Units +25˚C 0 to 70˚C −40 to +85˚C 380 380 360 Frequency Domain Response -3dB Bandwidth Small Signal Large Signal ± 0.1 dB Bandwidth 500 MHz 200 MHz MHz Gain Glatness Peaking DC to 200MHz 0 Rolloff DC to 200MHz 0.1 dB Linear Phase Deviation < 200MHz 0.8 Differential Gain RL = 150Ω, 4.43MHz 0.03 0.05 0.05 0.05 % Differential Phase RL = 150Ω, 4.43MHz 0.02 0.02 0.05 0.05 deg Rise and Fall Time 2V Step 0.8 1.1 1.1 1.1 Settling Time to ± 0.2% 2V Step 6 Settling Time to ± 0.1% 2V Step 11 Overshoot 2V Step 10 18 18 18 % Slew Rate 4V Step 2500 2000 2000 2000 V/µs 0.5 0.5 0.5 dB deg Time Domain Response ns ns ns Distortion And Noise Response 2nd Harmonic Distortion 3rd Harmonic Distortion 3rd Order Intercept 2VPP, 5MHz −63 −59 −59 −59 dBc 2VPP, 20MHz −52 −48 −48 −48 dBc 2VPP, 50MHz −44 −40 −40 −40 dBc 2VPP, 5MHz −84 −77 −75 −75 dBc 2VPP, 20MHz −73 −66 −64 −64 dBc 2VPP, 50MHz −62 −55 −53 −53 dBc 70MHz 1dB Gain Compression @ 50MHz 30 dBm 16 dBm Equivalent Input Noise Non-Inverting Voltage 1MHz 2.2 2.9 nV/ Inverting Current 1MHz 15 20.0 pA/ Non-Inverting Current 1MHz 3 5.0 pA/ 3 7 Static, DC Performance Input Offset Voltage (Note 3) 3 9 9 mV www.national.com CLC449 Absolute Maximum Ratings (Note 1) CLC449 Electrical Characteristics (Continued) AV = +2, VCC = ± 5V, RL = 100Ω, Rf = 250Ω; unless specified Symbol Parameter Conditions Typ Min/Max (Note 2) Units Static, DC Performance Average Drift Input Bias Current (Note 3) 25 Non-Inverting 6 Average Drift Input Bias Current (Note 3) µV/C˚ 30 45 60 50 Inverting 2 Average Drift µA nA/˚C 20 25 40 25 µA nA/C˚ Power Supply Rejection Ratio DC 48 43 41 41 Common Mode Rejection Ratio DC 47 44 45 46 dB dB Supply Current (Note 3) RL = ∞ 12 13.5 14 14 mA Input Resistance Non-Inverting 400 200 200 150 KΩ Input Capacitance Non-Inverting 1.3 Output Resistance Closed Loop 0.1 0.15 0.15 0.25 Output Voltage Range RL = ∞ 3.3 3.1 3.1 3.1 V RL = 100Ω 2.9 2.8 2.8 2.8 V Common-Mode 2.4 2.2 2.1 1.9 V 80 60 50 40 mA Miscellaneous Performance Input Voltage Range Output Current pF Ω Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: AJ-level: spec. is 100% tested at +25˚C. Typical Performance Characteristics Non-Inverting Frequency Response Inverting Frequency Response DS012715-4 www.national.com DS012715-5 4 (Continued) Frequency Response vs. Load Open Loop Transimpedance, Z(s) DS012715-6 Harmonic Distortion vs. Frequency CLC449 Typical Performance Characteristics DS012715-7 2-Tone, 3rd Order Intermodulation Intercept DS012715-8 2nd Harmonic Distortion vs. Pout DS012715-9 3rd Harmonic Distortion vs. Pout DS012715-10 DS012715-11 5 www.national.com Gain Flatness and Linear Phase Equivalent Input Noise Phase (1deg/div) Noise Voltage (nV/√Hz), Current (pA/√Hz) (Continued) Magnitude (0.1dB/div) CLC449 Typical Performance Characteristics DS012715-12 0.1k 1k 10k 100k 1M Frequency (Hz) 10M 100M DS012715-13 Single Supply −3dB Bandwidth Differential Gain and Phase DS012715-14 PSRR, CMRR, and Closed Loop ROUT DS012715-15 Small Signal Pulse Response DS012715-17 DS012715-16 www.national.com 6 (Continued) Large Signal Pulse Response Gain Compression CLC449 Typical Performance Characteristics DS012715-18 DS012715-19 RS and Settling Time vs. CL Input Bias Current, IBI, IBN (µA) Input Offset Voltage, VIO (mV) Typical IBI, IBN, VIO vs. Temperature DS012715-20 DS012715-21 Input VSWR Output VSWR DS012715-22 DS012715-23 7 www.national.com (Continued) Reverse Isolation (S12) -10 -20 -30 -40 |S12| (dB) CLC449 Typical Performance Characteristics -50 -60 -70 -80 -90 -100 0 100M 200M 300M Frequency (Hz) 400M 500M DS012715-24 Rf ) 340 − AV x Ri where Ri = 45Ω. For AV > 5, the minimum recommended Rf is 100Ω. Select Rg to set the DC gain: Application Division CLC449 Operation CLC449 Extended Application Information The following design and application topics will supply you with: • A comprehensive set of design parameters and design parameter adjustment techniques. • A set of formulas that support design parameter change prediction • A series of common applications that the CLC449 supports. Accuracy of DC gain is usually limited by the tolerance of Rf and Rg. DC Gain (unity gain buffer) Unity gain buffers are easily designed with a current-feedback amplifier as long as the recommended feedback resistor Rf = 402Ω is used and Rg = ∞, i.e., open. Parasitic capacitance at the inverting node may require a slight increase of Rf to maintain a flat frequency response. DC Gain (inverting) The inverting DC voltage gain for the configuration shown in Figure 2 is • A set of easy to use design guidelines for the CLC449. Additional design applications are possible with the CLC449. If you have application questions, call 1-800-272-9959 in the U.S. to contact a technical staff member. DC Gain (Non-inverting) The non-inverting DC voltage gain for the configuration shown in is: DS012715-25 FIGURE 1. Non-Inverting Gain The normalized gain plots in the Typical Performance Characteristics section show different feedback resistors, Rf, for different gains. These values of Rf are recommended for obtaining the highest bandwidth with minimal peaking. The resistor t in Figure 1 provides DC bias for the non-inverting input. For Av ≤5, calculate the recommended Rf as follows: www.national.com DS012715-28 FIGURE 2. Inverting Gain 8 CLC449 Application Division (Continued) Req1 The normalized gain plots in the Typical Performance Characteristics section show different feedback resistors Rf for different gains. These values of Rf are recommended for obtaining the highest bandwidth with minimal peaking. The resistor Rt in Figure 2 provides DC bias for the non-inverting input. For |Av|≤4, calculate the recommended Rf as follows: Vin Req2 Vref Rref + Vo CLC449 Rf DS012715-31 FIGURE 3. Level Shifting Circuit Rf ) 295 − |AV| x Ri where Ri = 45Ω. For |AV| > 4, the minimum recommended Rf is 100Ω. DC Design (Single Supply) Figure 4 is a typical single-supply circuit. Resistors R1 and R2 form a voltage divider that sets the non-inverting input DC voltage. This circuit has a DC gain of 1. The coupling capacitor C1 isolates the DC bias point from the previous stage. Both capacitors make a high pass response; the high frequency gain is determined by Rf and Rg. Select Rg to set the DC gain: At large gains, Rg becomes small and will load the previous stage. This situation is resolved by driving Rg with a low impedance buffer like the CLC111, or increasing Rf and Rg see the Bandwidth (Small Signal) sub-section for the tradeoffs). Accurate DC gain is usually limited by the tolerance of the external resistors Rf and Rg. Bandwidth (Small Signal) The CLC449 current-feedback amplifier bandwidth is a function of the feedback resistor (Rf), not of the DC voltage gain (Av). The bandwidth is approximately proportional to 1/Rf. As a rule, if Rf doubles, the bandwidth is cut in half. Other AC specifications will also be degraded. Decreasing Rf from the recommended value increases peaking and for very small values of Rf oscillation will occur. With an inverting amplifier design, peaking is sometimes observed. This is often the result of layout parasitics caused by inadequate ground planes or long traces. If this is observed, placing a 50 to 200Ω resistor between the non-inverting pin and ground will usually reduce the peaking. Bandwidth (Minimum Slew Rate) Slew rate influences the bandwidth for large signal sinusoids. To determine an approximate value of slew rate, necessary to support large sinusoids use the following equation: SR)5 x f x Vpeak Vcc Vcc R1 Vin + C1 Vo CLC449 R2 Rf Rg C2 DS012715-32 FIGURE 4. Single Supply Circuit The complete gain equation for the circuit in Figure 4 is R 1 + sτ 2 ⋅ 1 + f Rg sτ1 Vo = ⋅ Vin 1 + sτ1 1 + sτ 2 Vpeak is the peak output sinusoid voltage, f is the frequency of the sinusoid. The slew rate of the CLC449 in inverting gains is always higher than in non-inverting gains. DC Design (Level Shifting) where s = jω, τ1 = (R1\R2) x C1, and τ2 = RgC2. DC Design (DC Offsets) The DC offset model shown in Figure 5 is used to calculate the output offset voltage. The equation for output offset voltage is: Figure 3 shows a DC level shifting circuit for inverting gain configurations. Vref produces a DC output level shift of Rf Vo = − Vos + IBN ⋅ Req1 ⋅ 1 + + (IBI ⋅ R f ) Req2 ( ) The current offset terms, IBN and IBI, do not track each other. The specifications are stated in terms of magnitude only. Therefore, the terms VOS, IBN, and IBI may have either positive or negative polarity. Matching the equivalent resistance seen at both input pins does not reduce the output offset voltage. which is independent of the DC output produced by Vin. 9 www.national.com CLC449 Application Division Thermal Design (Continued) To calculate the power dissipation for the CLC449, follow these steps: IBN + Req1 + Vos CLC449 IBI Rf 1. Calculate the no-load op amp power: Pamp = Icc (Vcc−VEE) 2. Calculate the output stage’s RMS power: Vo Po = (Vcc − Vload) Iload, where Vload and Iload are the RMS voltage and current across the external load. 3. Calculate the total op amp RMS power: Pt = Pamp + Po RL Req2 To calculate the maximum allowable ambient temperature, solve the following equation: Tamb = 150 − Pt x θJA where θJA is the thermal resistance from junction to ambient in ˚C/W, and Tamb is in ˚C. The Package Thermal Resistance section contains the thermal resistance for various packages. Dynamic Range (input/output protection) Input ESD diodes are present on all connected pins for protection from static voltage damage. For a signal that may exceed the supply voltages, we recommend using diode clamps at the amplifier’s input to limit the signals to less than the supply voltages. Dynamic Range (input/output levels) The Electrical Characteristics section specifies the Common-Mode Input Range and Output Voltage Range; these voltage ranges scale with the supplies. Output Current also specified in the Electrical Characteristics section. Unity gain applications are limited by the Common-Mode Input Range. At greater non-inverting gains, the Output Voltage Range becomes the limiting factor. Inverting gain applications are limited by the Output Voltage Range. For transimpedance or inverting gain applications, the current (Iinv) injected at the inverting input of the op amp needs to be: DS012715-35 FIGURE 5. DC Offset Model DC Design (Output Loading) RL, Rf, and Rg load the op amp output. The equivalent closed-loop load impedance seen by the output in Figure 5 is: RL_eq = RL\ (Rf+Req2), non-inverting gain RL_eq = RL\ Rf inverting gain RL_eq needs to be kept large enough so that the minimum available output current can produce the required output voltage swing. Capacitive Loads Capacitive loads, such as found in A/D converters, require a series resistor (Rs in the output to improve settling performance. The Rs and Settling Time vs. CL plot in the Typical Performance Characteristics section provides the information for selecting this resistor. Also, use a series resistor to reduce the effects of reactive loads on amplifier loop dynamics. For instance, driving coaxial cables without an output series resistor may cause peaking or oscillation. Transmission Line Matching One method for matching the characteristic impedance of a transmission line is to place the appropriate resistor at the input or output of the amplifier. Figure 6 shows the typical circuit configurations for matching transmission lines. In non-inverting gain applications, Rg is connected directly to ground. The resistors R1, R2, R6, and R7 are equal to the characteristic impedance DS012715-36 FIGURE 6. Transmission Line Matching where: In inverting gain applications, R3 is connected directly to ground. The resistor R4, R6, and R7 are equal to Z0. The parallel combination of R5 and Rg is also equal to Z0. • • • The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. Use C6 to match the output transmission line over a greater frequency range. It compensates for the increase of the op amp’s output impedance with frequency. www.national.com where Vmax is the Output Voltage Range . The voltage ranges discussed above are achieved as long as the equivalent output load is large enough so that the output current can produce the required output voltage swing. See the DC Design (output loading ) sub-section for details. Dynamic Range (Intermods) In RF applications, the CLC449 specifies a third order intercept of 30dBm at 70MHz and PO = 10dBm.at a gain of 10. A2-Tone, 3rd Order IMD Intercept plot is found in the Typical Performance Characteristics section. The output power level is taken at the load. Third-order harmonic distortion is calculated with the formula: HD3rd = 2 x (IP3O − PO) 10 IP3O =Third-order output intercept, dBm at the load. PO = output power level, dBm at the load. HD3rd = Third-order distortion from the fundamental, −dBc. (Continued) • dBm is the power in mW, at the load, expressed in dB. Realized third-order output distortion is highly dependent upon the external circuit. Some of the common external circuit choices that improve 3rd order distortion are: • short and equal return paths from the load to the supplies. • de-coupling capacitors of the correct value. • higher load resistance • a lower ratio of the output swing to the power supply voltage. Dynamic Range (Noise) In RF applications, noise is frequently specified as Noise Figure (NF). Figure 7 plots NF for the CLC449 at a gain of 10, with a feedback resistor Rf of 100Ω, and with no input matching resistor. The minimum Noise Figure (2.5dB) for these conditions occurs when the source resistance equals 700Ω. Noise Figure (dB) There is no matching resistor from the input to ground. • • 4kT = 16 x 10−21J, T= 290˚K. • • • Use a ground plane • tantalum capacitors of about 6.8µF for large signal current swings or improved power supply noise rejection; we recommend a minimum of 2.2 µF for any circuit • Minimize trace and lead lengths for components between the inverting and output pins • Remove ground plane underneath the amplifier package and 0.1” (3mm) from all input/output pads eni, ibn, ibi are the voltage and current noise density terms (see in the Distortion and Noise Response sub-section of the Electrical Characteristics section). Rf is the feedback resistor and Rg is the gain setting resistor. Printed Circuit Board Layout High Frequency op amp performance is strongly dependent on proper layout, proper resistive termination and adequate power supply decoupling. The most important layout points to follow are: 20 15 Bypass power supply pins with monolithic: ceramic capacitors of about 0.1µF placed less than 0.1” (3mm) from the pin • If parts must be socketed, always use flush-mounted socket pins instead of high profile sockets. Evaluation boards are available for proto-typing and measurements. Additional layout information is available in the evaluation board literature. Low Noise Composite Amp With Input Matching The composite circuit shown in Figure 9 eliminates the need for a matching resistor to ground at the input. By connecting two amplifiers in series, the first non-inverting and second inverting, an overall inverting gain is realized. The feedback resistor (Rf) connected from the output of the second amplifier to the non-inverting input of the first amplifier closes the loop, and generates a set input resistance (Rin) that can be matched to Rs. This resistor generates less noise than a matching resistor to ground at the input. 10 5 0 10 1000 100 10000 Source Resistance (Ω) DS012715-38 FIGURE 7. Noise Figure Plot en Rs Vs • • + - Rf + * * CLC449 ibn Vo Rf2 Rin Vs +- - + Rs - - CLC449 Rf1 Rf Rg1 * ibi Vo + 20Ω Rg DS012715-41 FIGURE 9. Composite Amplifier The input resistance and DC voltage gain of the amplifier are: DS012715-39 FIGURE 8. CLC449 Noise Model Rin = The CLC449 noise model in Figure 8 is used to develop the equation below. The equation for Noise Figure (NF) is: ( e + i R 2 + 4kTR + i ⋅ R ||R 2 ( bn s ) s g bi f NF = 10LOG ni 4kTRs ) 2 R R Rf , where G = 1+ f 1 ⋅ f2 1+ G R g1 R g2 Rin Vo = − G⋅ Vs Rin + R s + 4kT ⋅ R f ||R g Match the source resistance by setting: Rin = Rs Where: • Rg2 CLC449 Noise voltage produced by Rf, referred to the source Vs is: Rs is the source resistance at the non-inverting input. 11 www.national.com CLC449 Application Division CLC449 Application Division (Continued) Rs e 2R = 4kTRs ⋅ f Rin ⋅ (1 + G) The noise of a simple input matching resistor connected to ground can be calculated by setting G to 0 in this equation. Thus, this circuit reduces the thermal noise power produced by the matching resistor by a factor of (1+G). Rectifier Circuit Wide bandwidth rectifier circuits have many applications. Figure 10 shows a 200MHz wideband full-wave rectifier circuit using a CLC449 and a CLC522 amplifier. Schottky or PIN diodes are used for D1 and D2. They produce an active half-wave rectifier whose signals are taken at the feedback diode connection. The CLC522 takes the difference of the two half-wave rectified signals, producing a full-wave rectifier. The CLC522 is used at a gain of 5 to achieve high differential bandwidth. For best high frequency performance, maintain low parasitic capacitance from the diodes D1 and D2 to ground, and from the input of the CLC522 to ground. www.national.com DS012715-44 FIGURE 10. Full-Wave Rectifier Flash A/D Application The Typical Application circuit on the front page shows the CLC449 driving a flash A/D. Flash A/D’s require fast settling, low distortion, low noise and wide bandwidth to achieve high Effective Number of Bits and Spurious Free Dynamic Range (SFDR). This circuit connects a CLC449 to a TDA8716, 8-bit, 120MHz Flash Converter. The input capacitance for this converter is typically 13pF plus layout capacitace. From the Rs and Settling Time vs. CL plot in the Typical Performance Characteristics section, select a series resistor (Rs) of 55Ω. Place Rs in series with the output of the CLC449 to achieve settling to 0.1% in approximately 11ns. Keep the amplifier noise seen at the A/D input at least 3dB lower than the A/D’s noise, to avoid degrading A/D noise performace. 12 CLC449 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin SOIC NS Package Number M08A 8-Pin MDIP NS Package Number N08E 13 www.national.com CLC449 1.1GHz Ultra Wideband Monolithic Op Amp Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.supp[email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.