FAIRCHILD FMS3115KRC

www.fairchildsemi.com
FMS3110/3115
Triple Video D/A Converters
3 x 10 bit, 150 Ms/s
Features
Description
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FMS3110/3115 products are low-cost triple D/A converters
that are tailored to fit graphics and video applications where
speed is critical. Two speed grades are available:
10-bit resolution
150 megapixels per second
± 0.1% linearity error
Sync and blank controls
1.0V p-p video into 37.5Ω or 75Ω load
Internal bandgap voltage reference
Double-buffered data for low distortion
TTL-compatible inputs
Low glitch energy
Single +5 Volt power supply
FMS3110
100 Ms/s
FMS3115
150 Ms/s
TTL-level inputs are converted to analog current outputs that
can drive 25–37.5Ω loads corresponding to doubly-terminated
50–75Ω loads. A sync current following SYNC input timing
is added to the IOG output. BLANK will override RGB
inputs, setting IOG, IOB and IOR currents to zero when
BLANK = L. Although appropriate for many applications
the internal 1.235V reference voltage can be overridden by
the VREF input.
Applications
• Video signal conversion
– RGB
– YCBCR
– Composite, Y, C
• Multimedia systems
• Image processing
• True-color graphics systems (1 billion colors)
• Broadcast television equipment
• High-Definition Television (HDTV) equipment
• Direct digital synthesis
Few external components are required, just the current
reference resistor, current output load resistors, and
decoupling capacitors.
Package is a 48-lead LQFP. Fabrication technology is
CMOS. Performance is guaranteed from 0 to 70°C.
Block Diagram
SYNC
SYNC
BLANK
G9-0
B9-0
R9-0
10
10 bit D/A
Converter
IOG
10
10 bit D/A
Converter
IOB
10
10 bit D/A
Converter
IOR
CLOCK
+1.235V
Ref
COMP
RREF
VREF
Rev. 1.07 12/8/04
FMS3110/3115
DATA SHEET
Functional Description
D/A Outputs
Within the FMS3110/3115 are three identical 10-bit D/A
converters, each with a current source output. External loads
are required to convert the current to voltage outputs. Data
inputs RGB7-0 are overridden by the BLANK input. SYNC
= H activates, sync current from IOS for sync-on-green video
signals.
Each D/A output is a current source. To obtain a voltage
output, a resistor must be connected to ground. Output
voltage depends upon this external resistor, the reference
voltage, and the value of the gain-setting resistor connected
between RREF and GND.
Digital Inputs
All digital inputs are TTL-compatible. Data is registered on
the rising edge of the CLK signal. Following one stage of
pipeline delay, the analog output changes tDO after the rising
edge of CLK.
SYNC and BLANK
SYNC and BLANK inputs control the output level (Figure 1
and Table 1) of the D/A converters during CRT retrace
intervals. BLANK forces the D/A outputs to the blanking
level while SYNC = L turns off a current source that is
connected to the green D/A converter. SYNC = H adds a 40
IRE sync pulse to the green output, SYNC = L sets the green
output to 0.0 Volts during the sync tip. SYNC and BLANK
are registered on the rising edge of CLK.
BLANK gates the D/A inputs and sets the pedestal voltage.
If BLANK = HIGH, the D/A inputs are added to a pedestal
which offsets the current output. If BLANK = Low, data
inputs and the pedestal are disabled.
Normally, a source termination resistor of 75 Ohms is
connected between the D/A current output pin and GND
near the D/A converter. A 75 Ohm line may then be
connected with another 75 Ohm termination resistor at the
far end of the cable. This “double termination” presents the
D/A converter with a net resistive load of 37.5 Ohms.
The FMS3110/3115 may also be operated with a single 75
Ohm terminating resistor. To lower the output voltage swing
to the desired range, the nominal value of the resistor on
RREF should be doubled.
Voltage Reference
All three D/A converters are supplied with a common
voltage reference. Internal bandgap voltage reference voltage
is +1.235 Volts with a 3KΩ source resistance. An external
voltage reference may be connected to the VREF pin,
overriding the internal voltage reference.
A 0.1µF capacitor must be connected between the COMP
pin and VDD to stabilize internal bias circuitry and ensure
low-noise operation.
Power and Ground
data: 660 mV max.
pedestal: 54 mV
sync: 286 mV
Figure 1. Nominal Output Levels
2
Required power is a single +5.0 Volt supply. To minimize
power supply induced noise, analog +5V should be connected
to VDD pins with 0.1 and 0.01 µF decoupling capacitors
placed adjacent to each VDD pin or pin pair.
The high slew-rate of digital data makes capacitive coupling
to the outputs of any D/A converter a potential problem.
Since the digital signals contain high-frequency components
of the CLK signal, as well as the video output signal, the
resulting data feedthrough often looks like harmonic
distortion or reduced signal-to-noise performance. All
ground pins should be connected to a common solid ground
plane for best performance.
REV. 1.07 12/8/04
DATA SHEET
FMS3110/3115
Table 1. Output Voltage Versus Input Code, SYNC and BLANK
VREF = 1.235 V, RREF = 590 Ω, RL = 37.5 Ω
Blue and Red D/As
Green D/A
RGB9-0 (MSB…LSB)
SYNC
BLANK
VOUT
SYNC
BLANK
VOUT
11 1111 1111
X
1
0.7140
1
1
1.0000
11 1111 1111
X
1
0.7140
0
1
0.7140
11 1111 1110
X
1
0.7134
1
1
0.9994
11 1111 1101
X
1
0.7127
1
1
0.9987
•
•
•
•
•
•
•
•
•
•
•
•
•
•
10 0000 0000
X
1
0.3843
1
1
0.6703
01 1111 1111
X
1
0.3837
1
1
0.6697
•
•
•
•
•
•
•
•
•
•
•
•
•
•
00 0000 0010
X
1
0.0553
1
1
0.3413
00 0000 0001
X
1
0.0546
1
1
0.3406
00 0000 0000
X
1
0.0540
1
1
0.3400
XX XXXX XXXX
X
0
0.0000
1
0
0.2860
XX XXXX XXXX
X
0
0.0000
0
0
0.0000
48
48
47
47
46
46
45
45
44
44
43
43
42
42
41
41
40
40
39
39
38
38
37
37
G00
G
R99
R
R88
R
R77
R
R66
R
R55
R
R44
R
R33
R
R22
R
R11
R
R00
R
NC
NC
Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
LQFP
FMS3110/3115
36
35
34
33
32
31
30
29
28
27
26
25
RREF
VREF
COMP
IOR
IOG
OV
VDD
DD
VDD
IOB
GND
GND
CLOCK
NC
NC
NC
B00
B
B11
B
B22
B
B33
B
B44
B
B55
B
B66
B
B77
B
B88
B
B99
B
NC
NC
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
G1
G2
G3
G4
G5
G6
G7
G8
G9
BLANK
SYNC
VDD
Rev. 1.07 12/8/04
3
FMS3110/3115
DATA SHEET
Pin Descriptions
Pin Name
Pin Number
Value
Description
Clock and Pixel I/O
CLK
26
TTL
Clock Input. The clock input is TTL-compatible and all pixel data is
registered on the rising edge of CLK. It is recommended that CLK be
driven by a dedicated TTL buffer to avoid reflection induced jitter,
overshoot, and undershoot.
R9-0
47-37
TTL
Red Pixel Data Inputs. TTL-compatible Red Data Inputs are
registered on the rising edge of CLK.
G9-0
48, 9–1
TTL
Green Pixel Data Inputs. TTL-compatible Green Data Inputs are
registered on the rising edge of CLK.
B9-0
23–14
TTL
Blue Pixel Data Inputs. TTL-compatible Blue Data Inputs are
registered on the rising edge of CLK.
11
TTL
Sync Pulse Input. Bringing SYNC LOW, turns off a 40 IRE (7.62 mA)
current source which forms a sync pulse on the Green D/A converter
output. SYNC is registered on the rising edge of CLK with the same
pipeline latency as BLANK and pixel data. SYNC does not override
any other data and should be used only during the blanking interval.
Controls
SYNC
Since this is a single-supply D/A and all signals are positive-going,
sync is added to the bottom of the Green D/A range. So turning SYNC
OFF means turning the current source ON. When a sync pulse is
desired, the current source is turned OFF. If the system does not
require sync pulses from the Green D/A converter, SYNC should be
connected to GND.
BLANK
10
TTL
Blanking Input. When BLANK is LOW, pixel inputs are ignored and
the D/A converter outputs fall to the blanking level. BLANK is
registered on the rising edge of CLK and has the same pipeline
latency as SYNC.
IOR
33
0.714 Vp-p
Red Current Output. The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M compatible
levels into doubly-terminated 75 Ohm lines.
IOG
32
1 Vp-p
Green Current Output. The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M compatible
levels into doubly-terminated 75 Ohm lines. Sync pulses may be
added to the Green D/A output.
IOB
29
0.714 Vp-p
Blue Current Output. The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M compatible
levels into doubly-terminated 75 Ohm lines.
Video Outputs
4
Rev. 1.07 12/8/04
DATA SHEET
FMS3110/3115
Pin Descriptions (continued)
Pin Name
Pin Number
Value
Description
Voltage Reference
VREF
35
+1.235 V
RREF
36
560 Ω
Voltage Reference Output/Input. An internal voltage source of
+1.235 Volts is output on this pin. An external +1.235 Volt reference
may be applied here which overrides the internal reference.
Decoupling VREF to GND with a 0.1µF ceramic capacitor is required.
Current-Setting Resistor. Full-scale output current of each D/A
converter is determined by the value of the resistor connected
between RREF and GND. Nominal value of RREF is found from:
RREF = 9.1 (VREF/IFS)
where IFS is the full-scale (white) output current (in amps) from the
D/A converter (without sync). Sync is 0.4 * IFS.
D/A full-scale (white) current may also be calculated from:
IFS = VFS/RL
Where VFS is the white voltage level and RL is the total resistive load
(in ohms) on each D/A converter. VFS is the blank to full-scale
voltage.
COMP
34
0.1 µF
Compensation Capacitor. A 0.1 µF ceramic capacitor must be
connected between COMP and VDD to stabilize internal bias circuitry.
Power and Ground
VDD
12, 30, 31
+5 V
Power Supply.
GND
27, 28
0.0V
Ground.
Equivalent Circuits
VDD
VDD
p
Digital
Input
n
p
VDD
n
OUT
GND
GND
Figure 2. Equivalent Digital Input Circuit
Rev. 1.07 12/8/04
Figure 3. Equivalent Analog Output Circuit
5
FMS3110/3115
DATA SHEET
Equivalent Circuits (continued)
VDD
p
p
RREF
VREF
27012B
GND
Figure 4. Equivalent Analog Input Circuit
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter
Min
Typ
Max
Unit
-0.5
7.0
V
-0.5
VDD + 0.5
V
-10.0
10.0
mA
-0.5
VDD + 0.5
V
Power Supply Voltage
VDD (Measured to GND)
Inputs
Applied Voltage (measured to GND)2
Forced
Current3,4
Outputs
Applied Voltage (measured to GND)2
Forced
Current3,4
-60.0
60.0
mA
Infinite
second
110
°C
Junction
150
°C
Lead Soldering (10 seconds)
300
°C
Vapor Phase Soldering (1 minute)
220
°C
150
°C
Short Circuit Duration (single output in HIGH state to ground)
Temperature
Operating, Ambient
Storage
-20
-65
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if
Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
6
REV. 1.07 12/8/04
DATA SHEET
FMS3110/3115
Operating Conditions
Parameter
VDD
Power Supply Voltage
fS
Conversion Rate
tPWH
CLK Pulsewidth, HIGH
Min
Nom
Max
Units
4.75
5.0
5.25
V
100
Msps
150
Msps
FMS3110
FMS3115
tPWL
tW
CLK Pulsewidth, LOW
CLK Pulsewidth
FMS3110
3.1
ns
FMS3115
2.5
ns
FMS3110
3.1
ns
FMS3115
2.5
ns
FMS3110
10
ns
FMS3115
6.6
ns
tS
Input Data Setup Time
1.7
ns
th
Input Date Hold Time
0
ns
VREF
Reference Voltage, External
CC
Compensation Capacitor
0.1
µF
RL
Output Load
37.5
Ω
VIH
Input Voltage, Logic HIGH
2.0
VDD
V
VIL
Input Voltage, Logic LOW
GND
0.8
V
TA
Ambient Temperature, Still Air
0
70
°C
1.0
1.235
1.5
V
Electrical Characteristics
Parameter
Conditions3
IDD
Power Supply Current2
PD
Total Power Dissipation2
RO
Output Resistance
CO
Output Capacitance
IOUT = 0mA
30
pF
IIH
Input Current, HIGH
VDD = Max, VIN = 2.4V
-5
µA
IIL
Input Current, LOW
VDD = Max, VIN = 0.4V
5
µA
IREF
VREF Input Bias Current
±100
µA
VREF
Reference Voltage Output
VOC
Output Compliance
CDI
Digital Input Capacitance
Min
Typ1
Max
Units
VDD = Max
125
mA
VDD = Max
655
mW
100
0
kΩ
1.235
Referred to VDD
-0.4
V
0
+1.5
V
4
10
pF
Notes:
1. Values shown in Typ column are typical for VDD = +5V and TA = 25°C.
2. Minimum/Maximum values with VDD = Max and TA = Min.
3. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 540Ω
Rev. 1.07 12/8/04
7
FMS3110/3115
DATA SHEET
Switching Characteristics
Conditions2
Parameter
tD
Clock to Output Delay
Min
VDD = Min
Typ1
Max
Units
10
15
ns
1
tSKEW
Output Skew
2
ns
tR
Output Risetime
10% to 90% of Full Scale
3
ns
tF
Output Falltime
90% to 10% of Full Scale
3
ns
Notes:
1. Values shown in Typ column are typical for VDD = +5V and TA = 25°C.
2. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 590Ω.
System Performance Characteristics
Parameter
Conditions2
ELI
Integral Linearity Error
ELD
Typ1
Max
Units
VDD, VREF = Nom
±0.1
±0.25
%/FS
Differential Linearity Error
VDD, VREF = Nom
±0.1
±0.25
%/FS
EDM
DAC to DAC Matching
VDD, VREF = Nom
3
10
%
PSR
Power Supply Rejection Ratio
0.05
%/%
Min
Notes:
1. Values shown in Typ column are typical for VDD = +5V and TA = 25°C.
2. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 590Ω.
Timing Diagram
tPWL
1/fS
tPWH
CLK
tH
tS
PIXEL DATA
& CONTROLS
DataN
DataN+1
DataN+2
3%/FS
90%
tD
OUTPUT
50%
8
tSET
tF
tR
10%
Rev. 1.07 12/8/04
DATA SHEET
FMS3110/3115
Applications Discussion
2.
Power plane for the FMS3110/3115 should be separate
from that which supplies the digital circuitry. A single
power plane should be used for all of the VDD pins. If
the power supply for the FMS3110/3115 is the same as
that of the system's
digital circuitry, power to the FMS3110/3115 should be
decoupled with 0.1µF and 0.01µF capacitors and isolated with a ferrite bead.
It is important that the FMS3110/3115 power supply is wellregulated and free of high-frequency noise. Careful power
supply decoupling will ensure the highest quality video signals at the output of the circuit. The FMS3110/3115 has separate analog and digital circuits. To keep digital system noise
from the D/A converter, it is recommended that power supply
voltages (VDD) come from the system analog power source
and all ground connections (GND) be made to the analog
ground plane. Power supply pins should be individually
decoupled at the pin.
3.
The ground plane should be solid, not cross-hatched.
Connections to the ground plane should have very short
leads.
4.
If the digital power supply has a dedicated power plane
layer, it should not be placed under the FMS3110/3115,
the voltage reference, or the analog outputs. Capacitive
coupling of digital power supply noise from this layer to
the FMS3110/3115 and its related analog circuitry can
have an adverse effect on performance.
Printed Circuit Board Layout
5.
CLK should be handled carefully. Jitter and noise on
this clock will degrade performance. Terminate the
clock line carefully to eliminate overshoot and ringing.
Figure 5 illustrates a typical FMS3110/3115 interface circuit. In this example, an optional 1.2 Volt bandgap reference
is
connected to the VREF output, overriding the internal voltage reference source.
Grounding
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall system
performance is strongly influenced by the board layout.
Capacitive coupling from digital to analog circuits may
result in poor D/A conversion. Consider the following suggestions when doing the layout:
1.
Related Products
• FMS38XX Triple 8-bit 150 Msps D/A Converters
• FMS9884A 3 x 8-bit 140 Ms/s A/D Converter
Keep the critical analog traces (VREF, IREF, COMP,
IOS, IOR, IOG) as short as possible and as far as possible from all digital signals. The FMS3110/3115 should
be located near the board edge, close to the analog output connectors.
+5V
10µF
0.1µF
VDD
RED PIXEL
INPUT
R9-0
GREEN PIXEL
INPUT
G9-0
BLUE PIXEL
INPUT
CLOCK
SYNC
BLANK
B9-0
GND
Red
IOG
FMS31XX
ZO=75Ω
IOR
IOB
75Ω
75Ω
ZO=75Ω
75Ω
Blue
ZO=75Ω
75Ω
75Ω
Triple 10-bit
D/A Converter
+5V
COMP
CLK
SYNC
BLANK
75Ω
Green w/Sync
0.1µF
VREF
RREF
560Ω
3.3kΩ (not required without
external reference)
LM185-1.2
(Optional)
0.1µF
Figure 5. Typical Interface Circuit
REV. 1.07 12/8/04
9
FMS3110/3115
DATA SHEET
Mechanical Dimensions
48-Lead LQFP Package
Inches
Symbol
Min.
A
A1
A2
B
D/E
D1/E1
e
L
N
ND
α
ccc
Millimeters
Max.
.055
.063
.001
.005
.053
.057
.006
.010
.346
.362
.268
.284
.019 BSC
.017
.029
48
12
0°
7°
.004
Min.
Notes:
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982.
Max.
1.40
1.60
.05
.15
1.35
1.45
.17
.27
8.8
9.2
6.8
7.2
.50 BSC
.45
.75
48
12
0°
7°
0.08
2. Dimensions "D1" and "E1" do not include mold protrusion.
Allowable protrusion is 0.25mm per side. D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Pin 1 identifier is optional.
7
8
2
4. Dimension ND: Number of terminals.
5. Dimension ND: Number of terminals per package edge.
6. "L" is the length of terminal for soldering to a substrate.
7. Dimension "B" does not include dambar protrusion. Allowable
dambar protrusion shall not cause the lead width to exceed the
maximum B dimension by more than 0.08mm. Dambar can not be
located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm
pitch packages.
6
4
5
8. To be determined at seating place —C—
D
D1
e
PIN 1
IDENTIFIER
E E1
C
L
α
0.063" Ref (1.60mm)
See Lead Detail
A
Base Plane
A2
B
A1
Seating Plane
-CLEAD COPLANARITY
ccc
10
C
REV. 1.07 12/8/04
FMS3110/3115
DATA SHEET
Ordering Information
Product Number
FMS3110KRC
Conversion
Rate
Lead
Free
100 Ms/s
FMS3110KRC_NL
100 Ms/s
FMS3115KRC
150 Ms/s
Yes
Temperature
Range
Screening
Package
Package
Marking
0°C to 70°C
Commercial
48-Lead LQFP
3110KRC
0°C to 70°C
Commercial
48-Lead LQFP
3110KRC_NL
0°C to 70°C
Commercial
48-Lead LQFP
3115KRC
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user.
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