CS4953xx Data Sheet FEATURES 32-bit Audio Decoder DSP Family with Dual DSP Engine Technology Multi-standard 32-bit Audio Decoding plus Post Processing Large On-chip X, Y, and Program RAM & ROM SDRAM and Serial Flash Memory Support Framework™ Applications Library in ROM — Dolby Digital® EX, Dolby® Pro Logic® IIx, Dolby Headphone®, Dolby® Virtual Speaker® 96/24™, DTS-ES™ Discrete — DTS-ES Matrix 6.1, DTS:Neo6™ 6.1, DTS-ES™ — AAC™ Multichannel 5.1 — SRS® CS2® and TSXT® THX® Ultra2™, THX® ReEQ™ Cirrus Original Multi-Channel Surround (COMS) Crossbar Mixer, Signal Generator Advanced Post-Processor including: 7.1Bass Manager, Tone Control, 12- Band Parametric EQ, Delay, 1:2 Upsampler IN AR Y — — — — The CS4953xx DSP family are the enhanced versions of the CS495xx DSP family with higher overall performance and lower system cost. The CS4953xx includes all mainstream audio processing codes in on-chip ROM. This saves external memory for code storage. In addition, the intensive decoding tasks of Dolby Digital® Surround EX®, AAC multi-channel, DTS-ES 96/24, THX Ultra2 Cinema and Dolby Headphone can be accomplished without the expense of external SDRAM memory. — Microsoft® HDCD® Framework™ Applications for Download — Thomson MP3 Surround — Internal DSD-to-PCM Conversion Up to 12 Channels of 32-bit Serial Audio Input 6 Channel DSD Input 16 Ch x 32-bit PCM Out with either two 192 kHz S/PDIF Tx (144-pin package) or one 192 kHz S/PDIF Tx (128-pin package) With larger internal memories than the CS495xx, the CS49531x is designed to support up to 150 ms per channel of lip-sync delay. With 150 MHz internal clock speed, the CS4953xx supports the most demanding post-processing requirements. It is also designed for easy upgrading. Customers currently using the CS495xx can upgrade to the CS4953xx with minor hardware and software changes. Ordering Information See page 28 for ordering information. PR EL IM Two SPI™/I2C®, one Parallel and one UART Port Customer Software Security Keys Serial Control 1 Serial Control 2 Parallel Control UART GPIO 12 Ch. Audio In / 6 Ch. SACD In 32-bit DSP A S/PDIF S/PDIF P X Y Debug STC D M A 32-bit DSP B TMR1 TMR2 P X Y 16 Ch PCM Audio Out Ext. Memory Controller Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright 2008 Cirrus Logic, http://www.cirrus.com PLL SEP ’08 DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family Table of Contents 1. Documentation Strategy ...........................................................................................................4 2. Overview ....................................................................................................................................4 2.1 Migrating from the CS495xx(2) to the CS4953xx ..................................................................................... 4 2.2 Licensing .................................................................................................................................................. 4 3. Code Overlays ...........................................................................................................................5 4. Hardware Functional Description ...........................................................................................7 IN AR Y 4.1 DSP Core ................................................................................................................................................. 7 4.1.1 DSP Memory ...............................................................................................................................7 4.1.2 DMA Controller ............................................................................................................................7 4.2 On-chip DSP Peripherals ......................................................................................................................... 8 4.2.1 Digital Audio Input Port (DAI) .......................................................................................................8 4.2.2 Digital Audio Output Port (DAO) ..................................................................................................8 4.2.3 Serial Control Port 1 & 2 (I2C® or SPI™) .....................................................................................8 4.2.4 Parallel Control Port ....................................................................................................................8 4.2.5 External Memory Interface ..........................................................................................................8 4.2.6 GPIO ............................................................................................................................................8 4.2.7 PLL-based Clock Generator ........................................................................................................8 4.3 DSP I/O Description ................................................................................................................................. 8 4.3.1 Multiplexed Pins ..........................................................................................................................8 4.3.2 Termination Requirements ...........................................................................................................9 4.3.3 Pads ............................................................................................................................................9 4.4 Application Code Security ........................................................................................................................ 9 5. Characteristics and Specifications .......................................................................................10 PR EL IM 5.1 Absolute Maximum Ratings .................................................................................................................... 10 5.2 Recommended Operating Conditions .................................................................................................... 10 5.3 Digital DC Characteristics ...................................................................................................................... 10 5.4 Power Supply Characteristics ................................................................................................................ 11 5.5 Thermal Data (144 LQFP) ...................................................................................................................... 11 5.6 Thermal Data (128 LQFP) ...................................................................................................................... 11 5.7 Switching Characteristics— RESET ....................................................................................................... 11 5.8 Switching Characteristics — XTI ............................................................................................................ 12 5.9 Switching Characteristics — Internal Clock ............................................................................................ 13 5.10 Switching Characteristics — Serial Control Port - SPI Slave Mode. .................................................... 14 5.11 Switching Characteristics — Serial Control Port - SPI Master Mode ................................................... 15 5.12 Switching Characteristics — Serial Control Port - I2C Slave Mode ...................................................... 16 5.13 Switching Characteristics — Serial Control Port - I2C Master Mode .................................................... 17 5.14 Switching Characteristics — Parallel Control Port - Intel® Slave Mode .............................................. 18 5.15 Switching Characteristics — Parallel Control Port - Motorola® Slave Mode ....................................... 20 5.16 Switching Characteristics — UART ...................................................................................................... 22 5.17 Switching Characteristics — Digital Audio Slave Input Port ................................................................. 23 5.18 Switching Characteristics — DSD Slave Input Port ............................................................................ 24 5.19 Switching Characteristics — Digital Audio Output Port ........................................................................ 24 5.20 Switching Characteristics — SDRAM Interface .................................................................................... 25 6. Ordering Information ..............................................................................................................28 7. Environmental, Manufacturing, and Handling Information ................................................28 8. Device Pinout Diagrams .........................................................................................................29 8.1 128-Pin LQFP Pinout Diagram ............................................................................................................... 29 8.2 144-Pin LQFP Pinout Diagram ............................................................................................................... 30 2 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 9. Package Mechanical Drawings ..............................................................................................31 9.1 128-pin LQFP Package Drawing ............................................................................................................ 31 9.2 144-Pin LQFP Package Drawing ............................................................................................................ 32 10. Revision History ....................................................................................................................33 List of Figures PR EL IM IN AR Y Figure 1. RESET Timing ........................................................................................................................................12 Figure 2. XTI Timing ..............................................................................................................................................12 Figure 3. Serial Control Port - SPI Slave Mode Timing ..........................................................................................14 Figure 4. Serial Control Port - SPI Master Mode Timing ........................................................................................15 Figure 5. Serial Control Port - I2C Slave Mode Timing ..........................................................................................16 Figure 6. Serial Control Port - I2C Master Mode Timing ........................................................................................17 Figure 7. Parallel Control Port - Intel® Mode Read Cycle ......................................................................................19 Figure 8. Parallel Control Port - Intel Mode Write Cycle ........................................................................................19 Figure 9. Parallel Control Port - Motorola® Mode Read Cycle Timing ...................................................................21 Figure 10. Parallel Control Port - Motorola Mode Write Cycle Timing ...................................................................21 Figure 11. UART Timing ........................................................................................................................................22 Figure 12. Digital Audio Input (DAI) Port Timing Diagram .....................................................................................23 Figure 13. Direct Stream Digital - Serial Audio Input Timing ..................................................................................24 Figure 14. Digital Audio Port Timing, MCLK Master Mode ....................................................................................25 Figure 15. External Memory Interface - SDRAM Burst Read Cycle .......................................................................26 Figure 16. External Memory Interface - SDRAM Burst Write Cycle .......................................................................26 Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle ....................................................................27 Figure 18. External Memory Interface - SDRAM Load Mode Register Cycle ........................................................27 Figure 19. 128-Pin LQFP Pin-Out Drawing ............................................................................................................29 Figure 20. 144-Pin LQFP Pin-Out Drawing ............................................................................................................30 Figure 21. 128-Pin LQFP Package Drawing .........................................................................................................31 Figure 22. 144-Pin LQFP Package Drawing .........................................................................................................32 List of Tables Table 1. CS4953xx Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2. Device and Firmware Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. CS495303 DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. CS495313 DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 6. Environmental, Manufacturing, and Handling Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 7. 128-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 8. 144-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DS705PP3 Copyright 2008 Cirrus Logic 3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 1. Documentation Strategy The CS4953xx Datasheet describes the CS4953xx family of multichannel audio decoders. This document should be used in conjunction with the following documents when evaluating or designing a system around the CS4953xx family of processors. Table 1. CS4953xx Related Documentation Document Name Description CS4953xx Datasheet This document CS4953xx Hardware User’s Manual Includes detailed system design information including Typical Connection Diagrams, Boot-Procedures, Pin Descriptions, Etc. AN288 - CS4953xx Firmware User’s Manual Includes detailed firmware design information including signal processing flow diagrams and control API information IN AR Y The scope of the CS4953xx Datasheet is primarily the hardware specifications of the CS4953xx family of devices. This includes hardware functionality, characteristic data, pinout, and packaging information. The intended audience for the CS4953xx Data Sheet is the system PCB designer, mcu programmer, and the quality control engineer. 2. Overview The CS4953xx DSP Family, together with Cirrus Logic’s comprehensive library of audio processing algorithms, enables the development of next-generation audio solutions. Cirrus Logic also provides a broad array of digital interface products, audio converters, and ARM® Processors to meet your audio system-level design requirements. PR EL IM There are two devices in the CS4953xx DSP family. The CS495303 and CS495313 are differentiated by internal memory size and DSP Firmware. The CS495303 is available in a 128-pin QFP package and the CS495313 is available in either a 128-pin or 144-pin QFP package. The audio processing features of the CS495313 are a superset of audio features available in the CS495303. Please refer to Table 2 on page 6 for the speed and firmware features of each device. 2.1 Migrating from the CS495xx(2) to the CS4953xx The CS4953xx was designed to provide an easy upgrade path from the CS495xx(2). Although 144-pin versions of the two devices are virtually identical with respect to external system connection, there are some small differences the hardware designer should be aware of: • • • • • • The PLL supply voltage on the CS4953xx is 3.3V vs. 1.8V on the CS495xx(2). The PLL filter topology is simpler when using the CS4953xx rather than the CS495xx(2). The CS4953xx adds support for 6-channel DSD input. The CS4953xx adds support for TDM mode on both audio input and output ports. The CS4953xx does not support external SRAM operation. The CS4953xx external SDRAM bus speed is fixed at 150 MHz vs. the 120 MHz max bus speed for the CS495xx(2). Some firmware modules also support a 75 MHz CS4953xx SDRAM bus speed. Please refer to AN288 for details. • The CS4953xx CLKOUT pin can output XTALI or XTALI/2. The CS495xx(2) can only output XTALI. 2.2 Licensing Licenses are required for all of the 3rd party audio decoding/processing algorithms listed below, including the application notes. Please contact your local Cirrus Sales representative for more information. 4 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 3. Code Overlays The suite of software available for the CS4953xx family consists of an operating system (OS) and a library of overlays. The overlays have been divided into three main groups called Decoders, Mid-processors, and Postprocessors. All software components are defined below: 1. OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory, processing host messages, calling audio-processing subroutines, error concealment, etc. 2. Decoders - Any Module that initially writes data into the audio I/O buffers, e.g. AC-3®, DTS, PCM, etc. All the decoding/processing algorithms listed below require delivery of PCM or IEC61937-packed, compressed data via I2S- or LJ-formatted digital audio to the CS4953xx. 3. Mid-processors - Any module that processes audio I/O buffer PCM data in-place before the Postprocessors. Generally speaking, these modules alter the number of valid channels in the audio I/O buffer through processes like Virtualization (nÖ2 channels) or Matrix Decoding (2Ön channels). Examples are Dolby ProLogic IIx and DTS Neo:6. IN AR Y 4. Post-processors - Any module that processes audio I/O buffer PCM data in-place after the Mid-Processors. Examples are Bass Management, Audio Manager, Tone Control, EQ, Delay, Customer-specific Effects, Dolby Headphone/Virtual Speaker, etc. The overlay structure reduces the time required to reconfigure the DSP when a processing change is requested. Each overlay can be reloaded independently without disturbing the other overlays. For example, when a new decoder is selected, the OS, mid-, and post-processors do not need to be reloaded — only the new decoder (the same is true for the other overlays). PR EL IM Table 2 below lists the firmware available based on device selection. Please refer AN288 CS4953xx Firmware User’s Manual for the latest listing of application codes and Cirrus Framework™ modules available. DS705PP3 Copyright 2008 Cirrus Logic 5 DS705PP3 Table 2. Device and Firmware Selection Guide1 Device PreProcess Decode Processor A Mid-processor A Mid-processor B Post-processor B Dolby PLIIx Stereo PCM Multi-Channel PCM CS495303 300 MIPS (2:1 Down-sampling Option) N/A Dolby Digital AAC MP3 HDCD Circle Surround® II Dolby Headphone (Stereo In) Dolby Virtual Speaker Cirrus Original MultiChannel Surround (Effects / Reverb Processor) SRSTruSurround XT THX Select Down-mix (Simultaneous Process) Copyright 2008 Cirrus Logic CS495313 (Superset of CS495303) 300 MIPS Lip Sync Delay Same as CS495303 + DTS DTS-ES DTS 96/24 Same as CS495303 + DTS Neo:6 (Stereo In) APP (Advanced Post-processing) Same as CS495303 + THX Ultra2 –Tone Control –Re-EQ –PEQ (up to 11 Bands) –Delay –7.1 Bass Manager –Audio Manager 1:2 Up-sampling 1.This feature list is a snapshot of features available as of the publication date of this revision of the data sheet. More features may now be available. Check with your Cirrus Logic Field Application Engineer (FAE) to obtain the latest feature list for the CS495303 and CS495313 products. CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 6 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 4. Hardware Functional Description 4.1 DSP Core The CS4953xx is a dual-core DSP with separate X and Y data and P code memory spaces. Each core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two memory access control (MAC) operations per clock cycle. Each core has eight 72-bit accumulators, four X- and four Ydata registers, and 12 index registers. Both DSP cores are coupled to a flexible DMA engine. The DMA engine can move data between peripherals such as the digital audio input (DAI) and digital audio output (DAO), external memory, or any DSP core memory, all without the intervention of the DSP. The DMA engine offloads data move instructions from the DSP core, leaving more MIPS available for signal processing instructions. CS4953xx functionality is controlled by application codes that are stored in on-board ROM or downloaded to the CS4953xx from a host mcu or external FLASH/EEPROM. Users can choose to use standard audio decoder and post-processor modules which are available from Cirrus Logic. 4.1.1 DSP Memory IN AR Y The CS4953xx is suitable for Audio Decoder, Audio Post-processor, Audio Encoder, DVD Audio/Video Player, and Digital Broadcast Decoder applications. Each DSP core has its own on-chip data and program RAM and ROM and does not require external memory for any of today’s popular audio algorithms including Dolby Digital Surround EX, AAC Multichannel, DTS-ES 96/24, and THX Ultra2. The memory maps for the DSPs are as follows. All memory sizes are composed of 32-bit words. Table 3. CS495303 DSP Memory Sizes Memory Type DSP B 16k SRAM, 16k ROM 10k SRAM, 8k ROM PR EL IM X DSP A Y 16k SRAM, 32k ROM 16k SRAM, 16k ROM P 8k SRAM, 32k ROM 8k SRAM, 24k ROM Table 4. CS495313 DSP Memory Sizes Memory Type DSP A DSP B X 16k SRAM, 16k ROM 10k SRAM, 8k ROM Y 24k SRAM, 32k ROM 16k SRAM, 16k ROM P 8k SRAM, 32k ROM 8k SRAM, 24k ROM 4.1.2 DMA Controller The powerful 12-channel DMA controller can move data between 8 on-chip resources. Each resource has its own arbiter: X, Y, and P RAM/ROMs on DSP A; X, Y, and P RAM/ROMs on DSP B; external memory; and the peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment controls. The service interval for each DMA channel as well as up to 6 interrupt events, is programmable. DS705PP3 Copyright 2008 Cirrus Logic 7 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 4.2 On-chip DSP Peripherals 4.2.1 Digital Audio Input Port (DAI) The 12-channel (6 line) DAI port supports a wide variety of data input formats. The port is capable of accepting PCM, IEC61937, or DSD. Up to 32-bit word lengths are supported. Up to 6 channels of DSD are supported and internally converted to PCM before processing. The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, which off-loads the task of monitoring the S/PDIF receiver from the host. A time-stamping feature allows the input data to be sample-rate converted via software. 4.2.2 Digital Audio Output Port (DAO) IN AR Y There are two DAO ports. Each port can output 8 channels of up to 32-bit PCM data. The port supports data rates from 32 kHz to 192 kHz. Each port can be configured as an independent clock domain in slave mode, or the ratio of the two clocks can be set to even multiples of each other in master mode. The two ports can also be ganged together into a single clock domain. Each port has one serial audio pin that can be configured as a 192 kHz S/PDIF transmitter (data with embedded clock on a single line). Note: Only one S/PDIF transmitter pin is available in the 128-pin package. 4.2.3 Serial Control Port 1 & 2 (I2C® or SPI™) There are two on-chip serial control ports that are capable of operating as master or slave in either I2C or SPI modes. SCP1 defaults to slave operation. It is dedicated for external host-control and supports an external clock up to 50 MHz in SPI mode. It is present in both the 144- and 128-pin packages. This high clock speed enables very fast code download, control or data delivery. SCP2 defaults to master mode and is dedicated for booting from external serial Flash memory or for audio sub-system control. SCP2 does not include the SCP2_BSY# pin in the 128-pin package. 4.2.4 Parallel Control Port PR EL IM The CS4953xx parallel port supports both Motorola® and Intel® interfaces. It can be used for both control and data delivery. The parallel port pins are multiplexed with serial control port 2 and are available in the 144-pin package. 4.2.5 External Memory Interface The external memory interface controller supports up to 128 Mbits of SDRAM, using a 16-bit data bus. 4.2.6 GPIO Many of the CS4953xx peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high. 4.2.7 PLL-based Clock Generator The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving audio converters. The CS4953xx defaults to running from the external reference frequency and can be switched to use the PLL output after overlays have been loaded and configured, either through master boot from an external serial FLASH or through host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1. 4.3 DSP I/O Description 4.3.1 Multiplexed Pins Many of the CS4953xx pins are multi-functional. For details on pin functionality please refer to the CS4953xx Hardware User’s Manual. 8 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 4.3.2 Termination Requirements Open-drain pins on the CS4953xx must be pulled high for proper operation. Please refer to the CS4953xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up resistor is required for proper operation. Mode select pins on the CS4953xx are used to select the boot mode upon the rising edge of reset. A detailed explanation of termination requirements for each communication mode select pin can be found in the CS4953xx Hardware User’s Manual. 4.3.3 Pads The CS4953xx I/O operates from the 3.3 V supply and is 5V tolerant. 4.4 Application Code Security PR EL IM IN AR Y The external program code may be encrypted by the programmer to protect any intellectual property it may contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the device. DS705PP3 Copyright 2008 Cirrus Logic 9 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5. Characteristics and Specifications Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All data sheet typical parameters are measured under the following conditions: T = 25 °C, CL = 20 pF, VDD = VDDA = 1.8 V, VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V. 5.1 Absolute Maximum Ratings (GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) Parameter Core supply PLL supply I/O supply |VDDA – VDDIO| DC power supplies: Symbol Min Max Unit VDD VDDA VDDIO –0.3 –0.3 –0.3 - 2.0 3.6 3.6 0.3 V V V V Input pin current, any pin except supplies Iin - +/- 10 mA Input voltage on PLL_REF_RES Vfilt -0.3 3.6 V Input voltage on I/O pins Vinio -0.3 IN AR Y Storage temperature Tstg –65 5.0 V 150 °C CAUTION: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 5.2 Recommended Operating Conditions (GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) Parameter Core supply PLL supply I/O supply |VDDA – VDDIO| DC power supplies: Ambient operating temperature Symbol Min Typ Max Unit VDD VDDA VDDIO 1.71 3.13 3.13 1.8 3.3 3.3 0 1.89 3.46 3.46 V V V V 0 - 40 +25 +25 + 70 + 85 °C TA PR EL IM Commercial Grade (CQZ/CVZ) Automotive Grade (DQZ/DVZ) Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply. 5.3 Digital DC Characteristics (Measurements performed under static conditions.) Parameter Symbol Min High-level input voltage VIH 2.0 - - V Low-level input voltage, except XTI VIL - - 0.8 V VILXTI - - 0.6 V Low-level input voltage, XTI Typ Max 0.4 Unit Input Hysteresis Vhys V High-level output voltage (IO = -4mA), except XTI, SDRAM pins VOH VDDIO * 0.9 - - V Low-level output voltage (IO = 4mA), except XTI, SDRAM pins VOL - - VDDIO * 0.1 V SDRAM High-level output voltage (IO = -8mA) VOH VDDIO * 0.9 - - V SDRAM Low-level output voltage (IO = 8mA) VOL - - VDDIO * 0.1 V Input leakage current (all digital pins with internal pull-up resistors disabled) IIN - - 5 μA Input leakage current (all digital pins with internal pull-up resistors enabled, and XTI) IIN-PU - - 50 μA 10 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.4 Power Supply Characteristics (measurements performed under operating conditions) Parameter Min Typ Max Unit - 500 3.5 120 - mA mA mA Power supply current: Core and I/O operating: VDD1 PLL operating: VDDA With external memory and most ports operating: VDDIO 1. Dependent on application firmware and DSP clock speed. 5.5 Thermal Data (144 LQFP) Parameter Symbol Thermal Resistance (Junction to Ambient) Two-layer Board1 Four-layer Board2 Two-layer Board1 Four-layer Board2 5.6 Thermal Data (128 LQFP) Parameter Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Top of Package) Two-layer Board1 Four-layer Board2 2. 3. 4. 5. 6. - 48 40 - Unit °C / Watt ψjt °C / Watt - .39 .33 - Min Typ Max - 53 44 - - .45 .39 - θja Unit °C / Watt ψjt °C / Watt Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20 % of the top & bottom layers. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20 % of the top & bottom layers and 0.5-oz copper covering 90 % of the internal power plane and ground plane layers. To calculate the die temperature for a given power dissipation Τj = Ambient Temperature + [ (Power Dissipation in Watts) * θja ] To calculate the case temperature for a given power dissipation Τc = Τj - [ (Power Dissipation in Watts) * ψ jt ] PR EL IM 1. Max θja Symbol Two-layer Board1 Four-layer Board2 Notes: Typ IN AR Y Thermal Resistance (Junction to Top of Package) Min 5.7 Switching Characteristics— RESET Parameter RESET# minimum pulse width low Symbol Min Max Unit Trstl 1 - μs All bidirectional pins high-Z after RESET# low Trst2z - 100 ns Configuration pins setup before RESET# high Trstsu 50 - ns Configuration pins hold after RESET# high Trsthld 20 - ns DS705PP3 Copyright 2008 Cirrus Logic 11 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family RESET# HS[3:0] All Bidirectional Pins Trstsu Trsthld Trst2z Trstl Figure 1. RESET Timing Parameter External Crystal operating frequency1 XTI period XTI high time XTI low time IN AR Y 5.8 Switching Characteristics — XTI Symbol Min Max Unit Fxtal Tclki 11.2896 27 MHz 33.3 100 ns Tclkih 13.3 - ns Tclkil 13.3 - ns CL 10 18 pF 50 W External Crystal Load Capacitance (parallel resonant)2 External Crystal Equivalent Series Resistance ESR PR EL IM 1. Part characterized with the following crystal frequency values: 11.2896, 12.288, 18.432, 24.576, & 27 MH.z. 2. CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals which require a CL outside this range should be avoided. The crystal oscillator circuit design should follow the crystal manufacturer’s recommendation for load capacitor selection. XTI t clkih t clkil Tclki Figure 2. XTI Timing 12 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.9 Switching Characteristics — Internal Clock Parameter Internal DCLK frequency1 Symbol Min Fdclk - CS49530x-CVZ CS49531x-CQZ CS49531x-CVZ CS49530x-DVZ CS49531x-DQZ CS49531x-DVZ Internal DCLK period1 DCLKP Unit MHz Fxtal Fxtal Fxtal Fxtal Fxtal Fxtal 150 150 150 TBD TBD TBD 6.7 6.7 6.7 TBD TBD TBD 1/Fxtal 1/Fxtal 1/Fxtal 1/Fxtal 1/Fxtal 1/Fxtal ns IN AR Y CS49530x-CVZ CS49531x-CQZ CS49531x-CVZ CS49530x-DVZ CS49531x-DQZ CS49531x-DVZ Max PR EL IM 1. After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk and remains locked until the next power-on reset. DS705PP3 Copyright 2008 Cirrus Logic 13 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.10 Switching Characteristics — Serial Control Port - SPI Slave Mode. Parameter Symbol Min Max Units SCP_CLK frequency fspisck - 25 MHz SCP_CS# falling to SCP_CLK rising SCP_CLK low time tspicss 24 - ns tspickl 20 - ns SCP_CLK high time tspickh 20 - ns Setup time SCP_MOSI input tspidsu 5 - ns Hold time SCP_MOSI input tspidh 5 - ns SCP_CLK low to SCP_MISO output valid tspidov - 11 ns SCP_CLK falling to SCP_IRQ# rising tspiirqh - 20 ns 1 Typical SCP_CS# rising to SCP_IRQ# falling tspiirql 0 SCP_CLK low to SCP_CS# rising tspicsh 24 ns SCP_CS# rising to SCP_MISO output high-Z tspicsdz - 20 ns SCP_CLK rising to SCP_BSY# falling tspicbsyl - 3*DCLKP+20 ns - ns tspicss SCP_CS# IN AR Y 1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is Fxtal/3. tspickl 1 0 SCP_CLK 6 7 0 SCP_MOSI A0 R/W MSB 5 6 7 tspicsh tspickh PR EL IM fspisck 2 A6 A5 LSB tspidsu tspidh SCP_MISO tspidov tspicsdz MSB LSB tspiirqh tspiirql SCP_IRQ# tspibsyl SCP_BSY# Figure 3. Serial Control Port - SPI Slave Mode Timing 14 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.11 Switching Characteristics — Serial Control Port - SPI Master Mode Parameter Symbol 1 Min Typical Max Fxtal /22 Units fspisck - tspicss - tspickl SCP_CLK high time Setup time SCP_MISO input Hold time SCP_MISO input tspidh 5 - ns SCP_CLK low to SCP_MOSI output valid tspidov - 11 ns SCP_CLK low to SCP_CS# falling tspicsl 7 SCP_CLK low to SCP_CS# rising tspicsh - Bus free time between active SCP_CS# tspicsx SCP_CLK frequency SCP_CS# falling to SCP_CLK rising 3 SCP_CLK falling to SCP_MOSI output high-Z - ns 18 - ns tspickh 18 - ns tspidsu 11 - ns 11*DCLKP + (SCP_CLK PERIOD)/2 3*DCLKP IN AR Y SCP_CLK low time 11*DCLKP + (SCP_CLK PERIOD)/2 MHz tspidz - - ns - ns - ns 20 ns 1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. 2. See Section 5.8. 3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter . tspicss PR EL IM EE_CS# tspickl tspicsl 1 0 2 6 7 0 A0 R/W MSB 5 6 7 tspicsx tspicsh SCP_CLK fspisck SCP_MISO tspickh A6 A5 LSB tspidsu tspidh SCP_MOSI tspidov tspidz MSB LSB Figure 4. Serial Control Port - SPI Master Mode Timing DS705PP3 Copyright 2008 Cirrus Logic 15 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.12 Switching Characteristics — Serial Control Port - I2C Slave Mode Parameter Symbol 1 Min Typical Max Units SCP_CLK frequency fiicck - 400 kHz SCP_CLK low time tiicckl 1.25 - µs SCP_CLK high time tiicckh 1.25 - µs tiicckcmd 1.25 START condition to SCP_CLK falling tiicstscl 1.25 - µs SCP_CLK falling to STOP condition tiicstp 2.5 - µs Bus free time between STOP and START conditions tiicbft 3 - µs Setup time SCP_SDA input valid to SCP_CLK rising tiicsu 100 SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition µs ns tiich 20 - ns SCP_CLK low to SCP_SDA out valid tiicdov - 18 ns SCP_CLK falling to SCP_IRQ# rising tiicirqh - 3*DCLKP + 40 ns NAK condition to SCP_IRQ# low IN AR Y Hold time SCP_SDA input after SCP_CLK falling tiicirql SCP_CLK rising to SCB_BSY# low - tiicbsyl 3*DCLKP + 20 ns 3*DCLKP + 20 ns 1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of the input data buffer. tiicckcmd tiicckl 0 1 6 SCP_CLK tiicckh tiicf 7 SCP_SDA A6 tiicsu 8 0 tiicdov PR EL IM tiicstscl tiicr A0 R/W 1 6 7 tiicckcmd 8 fiicck ACK MSB LSB tiicstp tiicbft ACK tiicirqh tiicirql tiich SCP_IRQ# tiiccbsyl SCP_BSY# Figure 5. Serial Control Port - I2C Slave Mode Timing 16 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.13 Switching Characteristics — Serial Control Port - I2C Master Mode Parameter Symbol 1 Min Max Units SCP_CLK frequency fiicck - 400 kHz SCP_CLK low time tiicckl 1.25 - µs SCP_CLK high time tiicckh 1.25 - µs tiicckcmd 1.25 START condition to SCP_CLK falling tiicstscl 1.25 - µs SCP_CLK falling to STOP condition tiicstp 2.5 - µs Bus free time between STOP and START conditions tiicbft 3 - µs Setup time SCP_SDA input valid to SCP_CLK rising tiicsu 100 tiich 20 - ns tiicdov - 18 ns SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition Hold time SCP_SDA input after SCP_CLK falling SCP_CLK low to SCP_SDA out valid µs ns tiicckcmd tiicckl 0 1 tiicckh A6 tiicf 7 8 0 tiicdov A0 R/W 1 6 7 tiicckcmd 8 tiicstp fiicck ACK MSB LSB tiicbft ACK PR EL IM SCP_SDA tiicr 6 SCP_CLK tiicstscl IN AR Y 1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. tiicsu tiich Figure 6. Serial Control Port - I2C Master Mode Timing DS705PP3 Copyright 2008 Cirrus Logic 17 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.14 Switching Characteristics — Parallel Control Port - Intel® Slave Mode Parameter Symbol Min Typical Max Unit Address setup before PCP_CS# and PCP_RD# low or PCP_CS# and PCP_WR# low tias 5 - ns Address hold time after PCP_CS# and PCP_RD# low or PCP_CS# and PCP_WR# high tiah 5 - ns ticdr 0 - ns Read Delay between PCP_RD# then PCP_CS# low or PCP_CS# then PCP_RD# low tidd - 18 ns PCP_CS# and PCP_RD# low for read tirpw 24 - ns Data hold time after PCP_CS# or PCP_RD# high tidhr 8 - ns Data high-Z after PCP_CS# or PCP_RD# high tidis - 18 ns PCP_CS# or PCP_RD# high to PCP_CS# and PCP_RD# low for next read1 tird 30 - ns IN AR Y Data valid after PCP_CS# and PCP_RD# low PCP_CS# or PCP_RD# high to PCP_CS# and PCP_WR# low for next write1 tirdtw 30 - ns tirdirqhl - 12 ns Delay between PCP_WR# then PCP_CS# low or PCP_CS# then PCP_WR# low ticdw 0 - ns Data setup before PCP_CS# or PCP_WR# high tidsu 8 - ns PCP_CS# and PCP_WR# low for write tiwpw 24 - ns tidhw 8 - ns PCP_CS# or PCP_WR# high to PCP_CS# and PCP_RD# low for next read1 tiwtrd 30 - ns PCP_CS# or PCP_WR# high to PCP_CS# and PCP_WR# low for next write1 tiwd 30 - ns tiwrbsyl - - ns PCP_RD# rising to PCP_IRQ# rising Write PR EL IM Data hold after PCP_CS# or PCP_WR# high PCP_WR# rising to PCP_BSY# falling 2*DCLKP + 20 1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the PCP_BSY# pin/bit should be observed to prevent overflowing the input data buffer. AN288 CS4953xx Firmware Uses’s Manual should be consulted for the firmware speed limitations. 18 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family PCP_A[3:0] t iah PCP_D[7:0] LSP t ias t idd PCP_CS# MSP t idhr t icdr t idis PCP_WR# t irpw t ird t irdtw PCP_RD# tirdirqh IN AR Y PCP_IRQ# Figure 7. Parallel Control Port - Intel® Mode Read Cycle PCP_A[3:0] t iah PCP_D[7:0] t ias PCP_CS# t icdw MSP t idhw t idsu t iwpw t iwd PR EL IM PCP_RD# LSP t iwtrd PCP_WR# tiwrbsyl PCP_BSY# Figure 8. Parallel Control Port - Intel Mode Write Cycle DS705PP3 Copyright 2008 Cirrus Logic 19 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.15 Switching Characteristics — Parallel Control Port - Motorola® Slave Mode Parameter Symbol Min Max Unit Address setup before PCP_CS# and PCP_DS# low tmas 5 - ns Address hold time after PCP_CS# and PCP_DS# low tmah 5 - ns Delay between PCP_DS# then PCP_CS# low or PCP_CS# then PCP_DS# low tmcdr 0 - ns Data valid after PCP_CS# and PCP_DS# low with PCP_R/W# high tmdd - 19 ns PCP_CS# and PCP_DS# low for read tmrpw 24 - ns Data hold time after PCP_CS# or PCP_DS# high after read tmdhr 8 - ns Read tmdis - 18 ns tmrd 30 - ns PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for next write1 tmrdtw 30 - ns tmrwirqh - 12 ns tmcdw 0 - ns PCP_RW# rising to PCP_IRQ# falling Write IN AR Y Data high-Z after PCP_CS# or PCP_DS# high after read PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for next read1 Delay between PCP_DS# then PCP_CS# low or PCP_CS# then PCP_DS# low Data setup before PCP_CS# or PCP_DS# high tmdsu 8 - ns PCP_CS# and PCP_DS# low for write tmwpw 24 - ns PCP_R/W# setup before PCP_CS# AND PCP_DS# low tmrwsu 24 - ns PCP_R/W# hold time after PCP_CS# or PCP_DS# high tmrwhld 8 - ns Data hold after PCP_CS# or PCP_DS# high PR EL IM PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low with PCP_R/W# high for next read1 PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for next write1 PCP_RW# rising to PCP_BSY# falling tmdhw 8 - ns tmwtrd 30 - ns tmwd 30 - ns tmrwbsyl - - ns 2*DCLKP + 20 1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the PCP_BSY# pin/bit should be observed to prevent overflowing the input data buffer. AN288 CS4953xx Firmware Uses’s Manual should be consulted for the firmware speed limitations. 20 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family HADDR[3:0] t mas t mah HDATA[7:0] MSP LSP t mdhr HEN t mdd t mrwsu t mcdr HR/W t mdis t mrpw t mrwhld t mrdtw t mrd HDS tmrwirqh IN AR Y HREQ Figure 9. Parallel Control Port - Motorola® Mode Read Cycle Timing HADDR[3:0] t mas HDATA[7:0] tmah LSP t mdsu HEN t mcdw t mdhw t mwpw PR EL IM HR/W MSP t mrwsu t mwd t mrwhld t mwtrd HDS tmrwirql HREQ Figure 10. Parallel Control Port - Motorola Mode Write Cycle Timing DS705PP3 Copyright 2008 Cirrus Logic 21 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.16 Switching Characteristics — UART Parameter 1 UART_CLK period Symbol Min Max Unit tuclki 266 - ns % UART_CLK duty cycle - 40 60 Setup time for UART_RXD tuckrxsu 5 - Hold time for UART_RXD tuckrxdv 5 - ns Delay from CLK transition to TXD transition tucktxdv - 29 ns ttxen ? ? ns ttxhz ? ? ns 1. The minimum clock period is limited to DCLKP/32 or the minimum value, whichever is larger. IN AR Y UART_CLK tucktxdv ttxen ttxhz UART_TXD tuckrxsu tuckrxdv UART_RXD UART_TX_EN PR EL IM Figure 11. UART Timing 22 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.17 Switching Characteristics — Digital Audio Slave Input Port Parameter DAI_SCLK period DAI_SCLK duty cycle Symbol Min Max Unit Tdaiclkp 40 - ns - 45 55 % Setup time DAI_DATAn tdaidsu 10 - ns Hold time DAI_DATAn tdaidh 5 - ns DAI_SCLK tdaidsu tdaidh IN AR Y DAI_DATAn PR EL IM Figure 12. Digital Audio Input (DAI) Port Timing Diagram DS705PP3 Copyright 2008 Cirrus Logic 23 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.18 Switching Characteristics — DSD Slave Input Port Symbol Min Typ Max Unit DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency (64x Oversampled) DSD_A / _B valid to DSD_SCLK rising setup time DSD_SCLK rising to DSD_A or DSD_B hold time DSD clock to data transition (Phase Modulation mode) tsclkl tsclkh tsdlrs tsdh tdpm 78 78 1.024 20 20 -20 - 3.2 20 ns ns MHz ns ns ns IN AR Y Parameter Figure 13. Direct Stream Digital - Serial Audio Input Timing PR EL IM 5.19 Switching Characteristics — Digital Audio Output Port Parameter DAO_MCLK period1 Symbol Min Max Unit Tdaomclk 40 - ns 1 - 40 60 % Tdaosclk 40 - ns - 40 60 % DAO_SCLK delay from DAO_MCLK rising edge, DAO_MCLK as an input tdaomsck - 19 ns DAO_LRCLK delay from DAO_SCLK transition, respectively4 DAO_MCLK duty cycle DAO_SCLK period for Master or Slave mode2 DAO_SCLK duty cycle for Master or Slave mode2 Master Mode (Output A1 Mode)2,3 tdaomstlr - 8 ns transition4 tdaomdv - 10 ns DAO_DATA[3..0] delay from DAO_SCLK transition4 tdaosdv 15 ns DAO_DATA[3:0] delay from DAO_SCLK Slave Mode (Output A0 Mode)5 1. CS4953xx has two Digital Audio Output modules having similar signal names ending in 1 and 2. Both DAO ports share a common MCLK but have independent SCLKs and LRCLKs. 2. Master mode timing specifications are characterized, not production tested. 3. Master mode is defined as the CS4953xx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce DAO_SCLK, DAO_LRCLK. 4. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the data is valid. 5.Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source. 24 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family Tdaomclk DAO_MCLK tdaomsck DAO_SCLK tdaomdv , tdaosdv DAO_DATAn tdaomstlr IN AR Y tdaomstlr DAO_LRCLK Figure 14. Digital Audio Port Timing, MCLK Master Mode 5.20 Switching Characteristics — SDRAM Interface Refer to Figure 15 through Figure 18. PR EL IM (SD_CLKOUT = SD_CLKIN) Parameter Symbol Min SD_CLKIN high time tsdclkh SD_CLKIN low time tsdclkl Max Unit 2.3 - ns 2.3 - ns SD_CLKOUT rise/fall time tsdclkrf - SD_CLKOUT Frequency SD_CLKOUT duty cycle Typical 1 150 ns MHz - 45 55 % SD_CLKOUT rising edge to signal valid tsdcmdv - 3.8 ns Signal hold from SD_CLKOUT rising edge tsdcmdh 1.1 - ns 3.8 - ns SD_CLKOUT rising edge to SD_DQMn valid tsddqv - SD_DQMn hold from SD_CLKOUT rising edge tsddqh 1.38 - ns SD_DATA valid setup to SD_CLKIN rising edge tsddsu 1.3 - ns SD_DATA valid hold to SD_CLKIN rising edge tsddh 1.38 SD_CLKOUT rising edge to ADDRn valid tsdav - DS705PP3 Copyright 2008 Cirrus Logic 3.8 - ns - ns 25 DS705PP3 SD_CLKOUT tsdcmdv tsdclkrf tsdcmdh SD_CS# SD_RAS# SD_CAS# SD_WE# tsddqh tsddqv SD_DQMn 11 00 SD_An tsdav tsddsu CAS=2 Copyright 2008 Cirrus Logic SD_Dn tsddh LSP0 LSP1 MSP0 MSP1 LSP2 MSP2 LSP3 MSP3 SD_CLKIN tsdclkl tsdclkh Figure 15. External Memory Interface - SDRAM Burst Read Cycle SD_CLKOUT tsdcmdv tsdcmdh SD_CS# SD_RAS# SD_CAS# LSP0 SD_Dn MSP0 LSP1 MSP1 LSP2 MSP2 LSP3 tsdav SD_An SD_DQMn 00 tsddqv 11 tsddqh 26 Figure 16. External Memory Interface - SDRAM Burst Write Cycle MSP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family SD_WE# CS4953xx Data Sheet 32-bit Audio Decoder DSP Family SD_CLKOUT tsdcmdv tsdcmdv tsdcmdh SD_CS SD_RAS SD_CAS IN AR Y SD_WE SD_DQMn SD_ADDRn SD_DATAn Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle PR EL IM SD_CLKOUT tsdcmdv tsdcmdh SD_CS SD_RAS SD_CAS SD_WE SD_DQMn SD_ADDRn OPCODE SD_DATAn Figure 18. External Memory Interface - SDRAM Load Mode Register Cycle DS705PP3 Copyright 2008 Cirrus Logic 27 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 6. Ordering Information The CS4953xx family part number is described as follows: CS495NNI-XYZ where NN - Product Number Variant I - ROM ID Number X - Product Grade Y - Package Type Z - Lead (Pb) Free Part No. IN AR Y Table 5. Ordering Information Grade CS495303-CVZ CS495303-DVZ CS495313-CQZ CS495313-DQZ CS495313-CVZ CS495313-DVZ Temp. Range Commercial 0 to +70 °C Automotive -40 to +85 °C Commercial 0 to +70 °C Automotive -40 to +85 °C Commercial 0 to +70 °C Automotive -40 to +85 °C Package 128-pin LQFP 144-pin LQFP 128-pin LQFP Note: Please contact the factory for availability of the -D (automotive grade) package. PR EL IM 7. Environmental, Manufacturing, and Handling Information Table 6. Environmental, Manufacturing, and Handling Information Model Number Peak Reflow Temp MSL Rating* Max Floor Life 260 °C 3 7 Days CS495303-CVZ CS495303-DVZ CS495313-CQZ CS495313-DQZ CS495313-CVZ CS495313-DVZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 28 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 8. Device Pinout Diagrams GPIO38, PCP_WR# / DS#, SCP2_CLK SD_A10, EXT_A10 SD_BA0, EXT_A13 SD_BA1, EXT_A14 105 GNDIO5 SD_WE# SD_CAS# SD_RAS# EXT_A15 110 SD_CS# VDD5 EXT_A16 EXT_A17 EXT_A18 115 GND5 EXT_A19 EXT_OE# EXT_CS1# 120 VDDIO6 GNDIO6 RESET# GPIO33, SCP1_MOSI GPIO34, SCP1__MISO / SDA GPIO35, SCP1_CLK 125 VDD6 GND6 GPIO37, SCP1_BSY#, PCP_BSY# 8.1 128-Pin LQFP Pinout Diagram 1 SD_A0, EXT_A0 GPIO11, PCP_A3, AS#, SCP2_MISO / SDA SD_A1, EXT_A1 100 VDDIO5 GPIO10, PCP_A2 / A10, SCP2_MOSI SD_A2, EXT_A2 GPOI9, SCP1_IRQ# GPIO8, PCP_IRQ#, SCP2_IRQ# GND4 5 SD_A3, EXT_A3 IN AR Y GPIO7, SCP1_CS#, IOWAIT GPIO6, PCP_CS#, SCP2_CS# VDDIO7 GNDIO7 GPIO3, DDAC 10 GPIO2, UART_TXD VDD7 GPIO1, UART_RXD GPIO0, UART_CLK GND7 15 XTAL_OUT XTI XTO SD_A4, EXT_A4 95 VDD4 EXT_CS2# SD_A5, EXT_A5 GNDIO4 SD_A6, EXT_A6 90 SD_A7, EXT_A7 VDDIO4 SD_A8, EXT_A8 SD_A9, EXT_A9 GND3 85 SD_A11, EXT_A11 SD_A12, EXT_A12 128-Pin LQFP GNDA PLL_REF_RES 20 VDDA (3.3V) VDD8 PR EL IM GPIO14, DAI1_DATA3, TM3, DSD3 VDD3 SD_CLKEN SD_CLKIN 80 SD_CLKOUT SD_DQM1 GPIO13, DAI1_DATA2, TM2, DSD2 SD_D8, EXT_D8 GND8 25 SD_D9, EXT_D9 GPIO12, DAI1_DATA1, TM1, DSD1 GNDIO3 DAI1_DATA0, TM0, DSD0 75 SD_D10, EXT_D10 VDDIO8 SD_D11, EXT_D11 DAI1_SCLK, DSD-CLK VDDIO3 DAI1_LRCLK, DSD4 30 SD_D12, EXT_D12 GNDIO8 SD_D13, EXT_D13 GPIO42, BDI_REQ# , DAI2_LRCLK, PCP_IRQ# / BSY# 70 SD_D14, EXT_D14 GPIO43, BDI_CLK, DAI2_SCLK SD_D15, EXT_D15 BDI_DATA, DAI2_DATA, DSD5 SD_D0, EXT_D0 GPIO26, DAO2_DATA3 / XMTB/UART_TX_EN 35 GNDIO2 DBDA EXT_WE# DBCK 65 SD_D1, EXT_D1 SD_D2, EXT_D2 SD_D3, EXT_D3 VDDIO2 SD_D4, EXT_D4 SD_D5, EXT_D5 60 SD_D6, EXT_D6 SD_D7, EXT_D7 SD_DQM0 GND2 VDD2 55 GNDIO1 DAO1_LRCLK DAO1_SCLK DAO1_DATA0, HS0 VDDIO1 50 GPIO15, DAO1_DATA1, HS1 GPIO16, DAO1_DATA2, HS2 GND1 45 GPIO23, DAO2_LRCLK GPIO17, DAO1_DATA3 / XMTA GPIO22, DAO2_SCLK GPIO18, DAO2_DATA0, HS3 VDD1 TEST DAO_MCLK 40 GPIO19, DAO2_DATA1, HS4 GPIO20, DAO2_DATA2, EE_CS# Figure 19. 128-Pin LQFP Pin-Out Drawing DS705PP3 Copyright 2008 Cirrus Logic 29 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family SD_A10, EXT_A10 73 VDDIO5 75 SD_BA0, EXT_A13 SD_BA1, EXT_A14 76 GNDIO5 SD_CAS# SD_WE# 80 SD_RAS# EXT_A15 SD_CS# EXT_A16 83 VDD5 85 EXT_A17 EXT_A18 86 GND5 EXT_A19 EXT_OE# 90 EXT_CS1# GPIO30, XMTB_IN 91 VDDIO6 RESET# 94 GNDIO6 95 GPIO33, SCP1_MOSI GPIO34, SCP1__MISO / SDA GPIO32, SCP1_CS#, IOWAIT GPIO35, SCP1_CLK 98 VDD6 100 GPOI36, SCP1_IRQ# GPIO37, SCP1_BSY#, PCP_BSY# 101 GND6 GPIO38, PCP_WR# / DS#, SCP2_CLK GPIO39, PCP_CS#, SCP2_CS# GPIO10, PCP_A2 / A10, SCP2_MOSI 105 GPIO11, PCP_A3, AS#, SCP2_MISO / SDA GPIO40, PCP_RD# / RW# 108 GPIO41, PCP_IRQ#, SCP2_IRQ# 8.2 144-Pin LQFP Pinout Diagram 72 SD_A0, EXT_A0 GPIO9, PCP_A1 / A9 109 SD_A1, EXT_A1 GPIO8, PCP_A0 / A8 110 GPIO7, PCP_AD7 / D7 70 SD_A2, EXT_A2 GPIO6, PCP_AD6 / D6 69 GND4 SD_A3, EXT_A3 VDDIO7 113 SD_A4, EXT_A4 GPIO5, PCP_AD5 / D5 66 VDD4 GPIO4, PCP_AD4 / D4 115 65 EXT_CS2# GNDIO7 116 SD_A5, EXT_A5 GPIO3, PCP_AD3 / D3 63 GNDIO4 IN AR Y GPIO2, PCP_AD2 / D2 VDD7 119 GPIO1, PCP_AD1 / D1 120 GPIO0, PCP_AD0 / D0 GND7 122 XTAL_OUT XTI XTO 125 GNDA 126 SD_A6, EXT_A6 SD_A7, EXT_A7 60 VDDIO4 SD_A8, EXT_A8 SD_A9, EXT_A9 57 GND3 SD_A11, EXT_A11 55 SD_A12, EXT_A12 144-Pin LQFP NC PLL_REF_RES VDDA (3.3V) 129 VDD8 130 GPIO14, DAI1_DATA3, TM3, DSD3 GPIO13, DAI1_DATA2, TM2, DSD2 GND8 133 GPIO12, DAI1_DATA1, TM1, DSD1 DAI1_DATA0, TM0, DSD0 135 VDDIO8 136 DAI1_SCLK, DSD-CLK PR EL IM DAI1_LRCLK, DSD4 54 VDD3 SD_CLKEN SD_CLKIN SD_CLKOUT 50 SD_DQM1 SD_D8, EXT_D8 SD_D9, EXT_D9 47 GNDIO3 SD_D10, EXT_D10 45 SD_D11, EXT_D11 44 VDDIO3 SD_D12, EXT_D12 SD_D13, EXT_D13 GNDIO8 139 SD_D14, EXT_D14 GPIO42, BDI_REQ# , DAI2_LRCLK, PCP_IRQ# / BSY# 140 40 SD_D15, EXT_D15 GPIO43, BDI_CLK, DAI2_SCLK BDI_DATA, DAI2_DATA, DSD5 SD_D0, EXT_D0 GPIO27 EXT_WE# 37 SD_D1, EXT_D1 GNDIO2 36 SD_D2, EXT_D2 35 SD_D3, EXT_D3 VDDIO2 33 SD_D4, EXT_D4 SD_D5, EXT_D5 SD_D6, EXT_D6 30 GND2 27 SD_DQM0 SD_D7, EXT_D7 GPIO24, UART_RXD VDD2 24 GPIO25, UART_TXD 25 GPIO31, UART_CLK DAO1_LRCLK GNDIO1 21 DAO1_SCLK DAO1_DATA0, HS0 VDDIO1 18 GPIO15, DAO1_DATA1, HS1 GPIO16, DAO1_DATA2, HS2 GPIO23, DAO2_LRCLK GPIO17, DAO1_DATA3 / XMTA 15 GND1 13 GPIO22, DAO2_SCLK GPIO18, DAO2_DATA0, HS3 9 TEST VDD1 10 DAO_MCLK GPIO19, DAO2_DATA1, HS4 5 GPIO20, DAO2_DATA2, EE_CS# GPIO21, DAO2_DATA3 / XMTB, UART_TX_ENABLE DBCK DBDA GPIO28, DDAC GPIO29, XMTA_IN 1 GPIO26 144 Figure 20. 144-Pin LQFP Pin-Out Drawing 30 Copyright 2008 Cirrus Logic DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 9. Package Mechanical Drawings 9.1 128-pin LQFP Package Drawing D D1 IN AR Y E E1 1 e b ∝ A A1 PR EL IM L Figure 21. 128-Pin LQFP Package Drawing Table 7. 128-Pin LQFP Package Characteristics MILLIMETERS INCHES DIM A A1 b D D1 E E1 e q L L1 MIN NOM MAX MIN NOM MAX --0.05 0.17 ----0.22 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.50 BSC 3.5 0.60 1.00 REF 1.60 0.15 0.27 --.002” .007” .063” .006” .011” 7° 0.75 0° .018” ----.009” .866” .787” .630” .551” .020” 3.5 .024” .039” REF 0° 0.45 7° .030” TOLERANCES OF FORM AND POSITION ddd DS705PP3 0.08 Copyright 2008 Cirrus Logic .003” 31 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 9.2 144-Pin LQFP Package Drawing E E1 Notes: 1. Controlling dimension is millimeter. 2. Dimensioning and tolerancing per ASME Y14.5M1994. e θ b PR EL IM L IN AR Y D D1 ddd M B SEATING PLANE B L1 A A1 Figure 22. 144-Pin LQFP Package Drawing Table 8. 144-Pin LQFP Package Characteristics MILLIMETERS INCHES DIM A A1 b D D1 E E1 e q L L1 MIN NOM MAX MIN NOM MAX --0.05 0.17 ----0.22 22.00 BSC 20.00 BSC 22.00 BSC 20.00 BSC 0.50 BSC --0.60 1.00 REF 1.60 0.15 0.27 --.002” .007” .063” .006” .011” 7° 0.75 0° .018” ----.009” .866” .787” .866” .787” .020” --.024” .039” REF 0° 0.45 7° .030” TOLERANCES OF FORM AND POSITION ddd 32 0.08 Copyright 2008 Cirrus Logic .003” DS705PP3 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 10. Revision History Revision Date Changes FEB 2006 Advance release. A2 JUN 2006 Updated part numbers for ordering (Tables 5 & 6), Updated VOH and VOL specification to include the current load used for testing A3 JUL 2006 Updated part numbers for ordering (Tables 5 &6). Updated text in sections 3 and 4. Updated parameter descriptions in sections 5.1 and 5.3. Updated Tspickl, Tspickh, and Tspidov timing. Corrected Figure SPI Master Timing to use EE_CS#. Added footnote to XTI table. Removed SCLK/LRCLK relative timing from DAI port timing. Removed SCLK/LRCLK slave relative timing from DAO port timing. A4 OCT 2007 Updated the Tspidsu, Tspickl, and Tspickh timing parameters for master mode SPI. This applies to both SPI ports. PP1 May 28, 2008 Updated product feature list in Table 2. Updated Figure 19 and Figure 20. PP2 June 20, 2008 Added typical crystal frequency values in Table Footnote 1 and Max and Min values of Fxtalin Section 5.8. Removed DSD Phase Modulation Mode from Section 5.18. Removed reference to MCLK in Section 5.18. Redefined Master mode clock speed for SCP_CLK in Section 5.11.. Redefined DC leakage characterization data in Section 5.3, correcting units of measurement. Modified Footnote 1 under Section 5.10. PP3 September 24, 2008 Removed references to External Parallel Flash / SRAM Interface. PR EL IM IN AR Y A1 DS705PP3 Copyright 2008 Cirrus Logic 33 CS4953xx Data Sheet 32-bit Audio Decoder DSP Family Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com. IMPORTANT NOTICE IN AR Y “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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The product includes technology owned by Microsoft Corporation and cannot be used or distributed without a license from Microsoft Licensing, Inc. , HDCD, High Definition Compatible Digital and Pacific Microsonics Inc. are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. HDCD technology provided under license from Microsoft Corporation. The product's design (and/or software) is covered by one or more of the following: 5,479,168; 5,638,074; 5,640,161; 5,808,574; 5,838,274; 5,854,600; 5,864,311; 5,872,531 with other patents pending. Supply of this product does not convey a license under the relevant intellectual property of Thomson multimedia and/or Fraunhofer Gesellschaft nor imply any right to use this product in any finished end user or ready-to-use final product. An independent license for such use is required. For details, please visit http://www.mp3licensing.com. Motorola and SPI are trademarks of Motorola, Inc. Intel is a registered trademark of Intel Corporation. I2C is a registered trademark of Philips Semiconductor. ARM is a registered trademark of ARM Limited. Logic7 is a registered trademark of Harmon International Industries, Inc. 34 Copyright 2008 Cirrus Logic DS705PP3