CS61304A CS61304A T1/E1 T1/E1 Line Interface Features General Description • The CS61304A combines the complete analog transmit and receive line interface for T1 or E1 applications in a low power, 28-pin device operating from a +5V supply. The CS61304A is a pin-compatible replacement for the LXT304A. The receiver uses a digital Delay-Locked-Loop which is continuously calibrated from a crystal reference to provide excellent stability and jitter tolerance. The CS61304A has a receiver jitter attenuator optimized for T1 CPE applications subject to AT&T 62411 and E1 ISDN PRI applications. The transmitter features internal pulse shaping and a low impedance output stage allowing the use of external resistors for transmitter impedance matching. Provides Analog Transmission Line Interface for T1 and E1 Applications • Provides Line Driver, Jitter Attenuator and Clock Recovery Functions • Fully Compliant with AT&T 62411 Stratum 4, Type II Jitter Requirements • Low Power Consumption • B8ZS/HDB3/AMI Encoder/Decoder • 50 mA Transmitter Short-Circuit Applications • • ( ) = Pin Function in Host Mode [ ] = Pin Function in Extended Hardware Mode 2 TPOS [TDATA] TNEG [TCODE] RCLK RPOS [RDATA] RNEG [BPV] 4 8 AMI, B8ZS, HDB3, CODER L O O P B A C K 7 6 MODE (CLKE) (INT) (SDI) (SDO) TAOS LEN0 LEN1 LEN2 5 R E M O T E 3 Channel Service Units ORDERING INFORMATION See page 31. Current Limiting TCLK Primary Rate ISDN Network/Termination Equipment L O C A L 28 24 25 TV+ 14 15 LINE DRIVER 13 TTIP PULSE SHAPER CONTROL 16 LINE RECEIVER L O O P B A C K JITTER ATTENUATOR 23 TGND CLOCK & DATA RECOVERY 19 9 10 1 17 SIGNAL QUALITY MONITOR RLOOP XTALIN XTALOUT ACLKI (CS) Preliminary Product Information Crystal Semiconductor Corporation http://www.cirrus.com P. O. Box 17847, Austin, Texas, 78760 (512) 445-7222 FAX:(512) 445-7581 27 LLOOP (SCLK) 12 LOS 21 RV+ RTIP 20 DRIVER MONITOR 18 11 26 TRING 22 RRING MTIP [RCODE] MRING [PCS] DPM [AIS] RGND This document contains information for a new product. Crystal Semiconductor reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2005 Crystal Semiconductor Corporation 1996 (AllCopyright Rights Reserved) (All Rights Reserved) MAY ‘05 96 SEP DS156PP2 DS156F1 1 CS61304A CS61304A ABSOLUTE MAXIMUM RATINGS Parameter DC Supply Symbol Min Max Units (referenced to RGND=TGND=0V) RV+ 6.0 V TV+ (RV+) + 0.3 V Input Voltage, Any Pin (Note 1) Vin RGND-0.3 (RV+) + 0.3 V Input Current, Any Pin (Note 2) Iin -10 10 mA Ambient Operating Temperature TA -40 85 °C Storage Temperature Tstg -65 150 °C WARNING:Operations at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Excluding RTIP, RRING, which must stay within -6V to (RV+) + 0.3V. 2. Transient currents of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND can withstand a continuous current of 100 mA. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Units DC Supply (Note 3) RV+, TV+ 4.75 5.0 5.25 V Ambient Operating Temperature TA -40 25 85 °C Power Consumption (Notes 4,5) PC 350 mW Notes: 3. TV+ must not exceed RV+ by more than 0.3V. 4. Power consumption while driving line load over operating temperature range. Includes IC and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load. 5. Assumes 100% ones density, 5.25 V, LEN2/1/0=1/1/1, a 100 Ω load and a 1:1.15 transformer. DIGITAL CHARACTERISTICS Parameter (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V) Symbol Min Typ Max High-Level Input Voltage (Notes 6, 7) VIH 2.0 PINS 1-4, 17, 18, 23-28 Low-Level Input Voltage (Notes 6, 7) VIL 0.8 PINS 1-4, 17, 18, 23-28 High-Level Output Voltage (Notes 6, 7, 8) VOH 2.4 IOUT = -400 µA PINS 6-8, 11, 12, 25 Low-Level Output Voltage (Notes 6, 7, 8) VOL 0.4 IOUT = 1.6 mA PINS 6-8, 11, 12, 23, 25 Input Leakage Current (Except Pin 5) ±10 Low-Level Input Voltage, PIN 5 VIL 0.2 High-Level Input Voltage, PIN 5 VIH (RV+) - 0.2 Mid-Level Input Voltage, PIN 5 (Note 9) VIM 2.3 2.7 Notes: 6. In Extended Hardware Mode, pins 17 and 18 are digital inputs. In Host Mode, pin 23 is an open drain output and pin 25 is a tristate digital output. 7. This specification guarantees TTL compatibility (VOH = 2.4V @ IOUT = -40µA). 8. Output drivers will drive CMOS logic levels into a CMOS load. 9. As an alternative to supplying a 2.3-to-2.7V input, this pin may be left floating. 2 Units V V V V µA V V V DS156F1 DS156PP2 CS61304A CS61304A ANALOG SPECIFICATIONS Parameter (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V) Min Typ Max Units Transmitter AMI Output Pulse Amplitudes (Note 10) 2.14 2.37 2.6 V E1, 75 Ω (Note 11) 2.7 3.0 3.3 V E1, 120 Ω (Note 12) 2.7 3.0 3.3 V T1, FCC Part 68 (Note 13) 2.4 3.0 3.6 V T1, DSX-1 (Note 14) E1 Zero (space) level (LEN2/1/0 = 0/0/0) -0.237 0.237 V 1:1 transformer and 75Ω load -0.3 0.3 V 1:1.26 transformer and 120Ω load Load Presented To Transmitter Output (Note 10) 75 Ω Jitter Added by the Transmitter (Note 15) 10Hz - 8kHz 0.01 UI 8kHz - 40kHz 0.025 UI 0.025 UI 10Hz - 40kHz 0.05 UI Broad Band Power in 2kHz band about 772kHz (Notes 10, 16) 12.6 15 17.9 dBm Power in 2kHz band about 1.544MHz (Notes 10, 16) -29 -38 dB (referenced to power in 2kHz band at 772kHz) Positive to Negative Pulse Imbalance (Notes 10, 16) T1, DSX-1 0.2 0.5 dB E1 amplitude at center of pulse -5 5 % -5 5 % E1 pulse width at 50% of nominal amplitude E1 Transmitter Return Loss (Notes 10, 16, 17) 51 kHz to 102 kHz 20 28 dB 102 kHz to 2.048 MHz 20 28 dB 2.048 MHz to 3.072 MHz 20 24 dB E1 Transmitter Short Circuit Current (Notes 10, 18) 50 mA RMS Notes: 10. Using a 0.47 µF capacitor in series with the primary of a transformer recommended in the Applications Section. 11. Pulse amplitude measured at the output of a 1:1 transformer across a 75 Ω load for line length setting LEN2/1/0 = 0/0/0. 12. Pulse amplitude measured at the output of a 1:1.26 transformer across a 120 Ω load for line length setting LEN2/1/0 = 0/0/0 or at the output of a 1:1 transformer across a 120 Ω load for LEN2/1/0=0/0/1. 13. Pulse amplitude measured at the output of a 1:1.15 transformer across a 100 Ω load for line length setting LEN2/1/0 = 0/1/0. 14. Pulse amplitude measured at the DSX-1 Cross-Connect across a 100 Ω load for all line length settings from LEN2/1/0 = 0/1/1 to LEN2/1/0 = 1/1/1 using a 1:1.5 transformer. 15. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK. 16. Not production tested. Parameters guaranteed by design and characterization. 17. Return loss = 20 log10 ABS((z1 +z0)/(z1-z0)) where z1 = impedance of the transmitter, and z0 = impedance of line load. Measured with a repeating 1010 data pattern with LEN2/1/0 = 0/0/0 and a 1:2 transformer with two 9.4 Ω series resistors terminated by a 75Ω load, or for LEN2/1/0 = 0/0/1 with a 1:2 transformer and two 15 Ω series resistors terminated by a 120Ω load. 18. Measured broadband through a 0.5 Ω resistor across the secondary of the transmitter transformer during the transmission of an all ones data pattern for LEN2/1/0 = 0/0/0 or 0/0/1with a 1:2 transformer and the series resistors specified in Table A1. DS156F1 DS156PP2 33 CS61304A CS61304A ANALOG SPECIFICATIONS Parameter Receiver RTIP/RRING Input Impedance Sensitivity Below DSX (0dB = 2.4V) (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V) Min Typ Max Units -13.6 500 50k - - Ω dB mV Data Decision Threshold T1, DSX-1 (Note 19) 60 65 70 % of peak 53 65 77 % of peak T1, DSX-1 (Note 20) 45 50 55 % of peak T1, FCC Part 68 and E1 (Note 21) Allowable Consecutive Zeros before LOS 160 175 190 bits Receiver Input Jitter Tolerance (Note 22) 10kHz - 100kHz 0.4 UI 6.0 UI 2kHz 300 UI 10Hz and below Loss of Signal Threshold (Note 23) 0.25 0.30 0.50 V Jitter Attenuator Jitter Attenuation Curve Corner Frequency (Notes 16, 24) 3 Hz Attenuation at 10kHz Jitter Frequency (Notes 16, 24) 50 dB Attenuator Input Jitter Tolerance (Notes 16, 24) 138 UI (Before Onset of FIFO Overflow or Underflow Protection) Notes: 19. For input amplitude of 1.2 Vpk to 4.14 Vpk. 20. For input amplitude of 0.5 Vpk to 1.2 Vpk and from 4.14 Vpk to RV+. 21. For input amplitude of 1.05 Vpk to 3.3 Vpk. 22. Jitter tolerance increases at lower frequencies. See Figure 11. 23. The analog input squelch circuit shall operate when the input signal amplitude above ground on the RTIP and RRING pins falls within the range of 0.25V to 0.50V. Operation of the squelch results in the recovery of zeros. During receive LOS, the RPOS, RNEG or RDATA outputs are forced low. 24. Attenuation measured with input jitter equal to 3/4 of measured jitter tolerance. Circuit attenuates jitter at 20 dB/decade above the corner frequency. See Figure 12. Output jitter can increase significantly when more than 138 UI’s are input to the attenuator. See discussion in the text section. 4 DS156F1 DS156PP2 CS61304A CS61304A T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) Parameter Symbol Min Typ Crystal Frequency (Note 25) fc 6.176000 TCLK Frequency ftclk 1.544 TCLK Pulse Width (Note 26) tpwh2 150 ACLKI Duty Cycle tpwh3/tpw3 40 ACLKI Frequency (Note 27) faclki 1.544 RCLK Duty Cycle (Note 28) tpwh1/tpw1 45 50 Rise Time, All Digital Outputs (Note 29) tr Fall Time, All Digital Outputs (Note 29) tf TPOS/TNEG (TDATA) to TCLK Falling Setup Time tsu2 25 TCLK Falling to TPOS/TNEG (TDATA) Hold Time th2 25 RPOS/RNEG Valid Before RCLK Falling (Note 30) tsu1 150 274 RDATA Valid Before RCLK Falling (Note 31) tsu1 150 274 RPOS/RNEG Valid Before RCLK Rising (Note 32) tsu1 150 274 RPOS/RNEG Valid After RCLK Falling (Note 30) th1 150 274 RDATA Valid After RCLK Falling (Note 31) th1 150 274 RPOS/RNEG Valid After RCLK Rising (Note 32) th1 150 274 Notes: 25. Crystal must meet specifications described in CXT6176/CXT8192 data sheet. 26. The transmitted pulse width does not depend on the TCLK duty cycle. 27. ACLKI provided by an external source or TCLK. 28. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator limits are reached. 29. At max load of 1.6 mA and 50 pF. 30. Host Mode (CLKE = 1). 31. Extended Hardware Mode. 32. Hardware Mode, or Host Mode (CLKE = 0). E1 SWITCHING CHARACTERISTICS Max Units 500 60 55 85 85 - MHz MHz ns % MHz % ns ns ns ns ns ns ns ns ns ns (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) Parameter Crystal Frequency (Note TCLK Frequency TCLK Pulse Width (Note ACLKI Duty Cycle ACLKI Frequency (Note RCLK Duty Cycle (Note Rise Time, All Digital Outputs (Note Fall Time, All Digital Outputs (Note TPOS/TNEG (TDATA) to TCLK Falling Setup Time TCLK Falling to TPOS/TNEG (TDATA) Hold Time RPOS/RNEG Valid Before RCLK Falling (Note RDATA Valid Before RCLK Falling (Note RPOS/RNEG Valid Before RCLK Rising (Note RPOS/RNEG Valid After RCLK Falling (Note RDATA Valid After RCLK Falling (Note RPOS/RNEG Valid After RCLK Rising (Note DS156F1 DS156PP2 25) 26) 27) 28) 29) 29) 30) 31) 32) 30) 31) 32) Symbol Min Typ Max Units fc 150 40 45 25 25 100 100 100 100 100 100 8.192000 2.048 2.048 50 194 194 194 194 194 194 340 60 55 85 85 - MHz MHz ns % MHz % ns ns ns ns ns ns ns ns ns ns ftclk tpwh2 tpwh3/tpw3 faclki tpwh1/tpw1 tr tf tsu2 th2 tsu1 tsu1 tsu1 th1 th1 th1 55 CS61304A CS61304A SWITCHING CHARACTERISTICS (TA = -40° to 85°C; TV+, RV+ = ±5%; Inputs: Logic 0 = 0V, Logic 1 = RV+) Parameter SDI to SCLK Setup Time SCLK to SDI Hold Time SCLK Low Time SCLK High Time SCLK Rise and Fall Time CS to SCLK Setup Time SCLK to CS Hold Time CS Inactive Time SCLK to SDO Valid CS to SDO High Z Input Valid To PCS Falling Setup Time PCS Rising to Input Invalid Hold Time PCS Active Low Time Notes: 33. Output load capacitance = 50pF. (Note 33) Symbol Min Typ Max Units tdc tcdh tcl tch tr, tf tcc tcch tcwh tcdv tcdz tsu4 th4 tpcsl 50 50 240 240 50 50 250 50 50 250 100 - 50 200 - ns ns ns ns ns ns ns ns ns ns ns ns ns tf tr Any Digital Output 90% 10% 90% 10% Figure 1. Signal Rise and Fall Characteristics tpw1 RCLK t pwl1 RPOS RNEG RDATA BPV t su1 t pwh1 EXTENDED HARDWARE MODE OR HOST MODE (CLKE = 1) t h1 HARDWARE MODE OR HOST MODE (CLKE = 0) RCLK Figure 2. Recovered Clock and Data Switching Characteristics 6 DS156F1 DS156PP2 CS61304A CS61304A t pw2 t pw3 t pwh3 t pwh2 ACLKI TCLK t su2 t h2 TPOS/TNEG Figure 3b. Alternate External Clock Characteristics Figure 3a. Transmit Clock and Data Switching Characteristics t cwh CS t cc t cch t ch t cl SCLK t dc SDI t cdh LSB t cdh LSB CONTROL BYTE MSB DATA BYTE Figure 4. Serial Port Write Timing Diagram CS t cdz SCLK t cdv SDO HIGH Z CLKE = 1 Figure 5. Serial Port Read Timing Diagram PCS t su4 LEN0/1/2, TAOS, RLOOP, LLOOP, RCODE, TCODE th4 t pcsl VALID INPUT DATA Figure 6. Extended Hardware Mode Parallel Chip Select Timing Diagram DS156F1 DS156PP2 77 CS61304A CS61304A THEORY OF OPERATION Key Enhancements of the CS61304A Relative to the LXT304A • • • • • • 12.5% Lower Power Consumption, 50 mARMS transmitter short-circuit current limiting for E1 (per OFTEL OTR-001), Optional AMI, B8ZS, HDB3 encoder/decoder or external line coding support, Receiver AIS (unframed all ones) detection, Improved receiver Loss of Signal handling (LOS set at power-up, reset upon receipt of 3 ones in 32 bit periods with no more than 15 consecutive zeros), Transmitter TTIP and TRING outputs are forced low when TCLK is static, Hardware Mode Control Method Control Pins MODE Pin Level Line Coding <0.2 V AIS Detection Driver Performance Monitor External Extended Host Hardware Mode Mode Control Pins Serial with Parallel Interface Chip Select Floating or >(RV+)-0.2 2.5 V V External No InternalAMI, B8ZS, or HDB3 Yes Yes No Yes No Table 1. Differences Between Operating Modes Introduction to Operating Modes The CS61304A supports three operating modes which are selected by the level of the MODE pin as shown in Tables 1 and 2, Figure 7, and Figures A1-A3 of the Applications section. The modes are Hardware Mode, Extended Hardware Mode, and Host Mode. In Hardware and Extended Hardware Modes, discrete pins are used to configure and monitor the device. The Extended Hardware Mode provides a parallel chip select input which latches the control inputs allowing individual ICs to be configured using a common set of control lines. In the Host Mode, an external processor monitors and configures the device through a serial interface. There are thirteen multi-function pins whose functionality is determined by the operating mode. (see Table 2). MODE EXTENDED FUNCTION PIN HARDWARE HARDWARE 3 TPOS TDATA TRANSMITTER TCODE 4 TNEG 6 RNEG BPV 7 RPOS RDATA RECEIVER/DPM 11 DPM AIS RCODE 17 MTIP 18 MRING PCS 18 23 LEN0 LEN0 24 LEN1 LEN1 CONTROL 25 LEN2 LEN2 26 RLOOP RLOOP 27 LLOOP LLOOP 28 TAOS TAOS HOST TPOS TNEG RNEG RPOS DPM MTIP MRING INT SDI SDO CS SCLK CLKE Table 2. Pin Definitions 8 DS156F1 DS156PP2 CS61304A CS61304A HARDWARE MODE TAOS LLOOP RLOOP LEN0/1/2 CONTROL TPOS TTIP LINE DRIVER TNEG CS62180B FRAMER CIRCUIT CS61304A TRING MRING MTIP DRIVER MONITOR DPM RTIP RPOS JITTER ATTENUATOR RNEG TRANSMIT TRANSFORMER LINE RECEIVER RRING RECEIVE TRANSFORMER EXTENDED HARDWARE MODE TCODE RCODE TAOS LLOOP RLOOP PCS LEN0/1/2 CONTROL TTIP TDATA LINE DRIVER AMI B8ZS, HDB3, CODER T1 or E1 REPEATER OR MUX BPV RTIP JITTER ATTENUATOR LINE RECEIVER RRING RECEIVE TRANSFORMER AIS HOST MODE µP SERIAL PORT 5 CONTROL TRANSMIT TRANSFORMER CS61304A AIS DETECT RDATA TRING CLKE CONTROL TTIP TPOS LINE DRIVER TNEG CS62180B FRAMER CIRCUIT CS61304A DRIVER MONITOR TRING MRING MTIP DPM RTIP RPOS RNEG JITTER ATTENUATOR TRANSMIT TRANSFORMER LINE RECEIVER RRING RECEIVE TRANSFORMER Figure 7. Overview of Operating Modes DS156F1 DS156PP2 99 CS61304A CS61304A Transmitter The transmitter takes digital T1 or E1 input data and drives appropriately shaped bipolar pulses onto a transmission line. The transmit data (TPOS & TNEG or TDATA) is supplied synchronously and sampled on the falling edge of the input clock, TCLK. Either T1 (DSX-1 or Network Interface) or E1 CCITT G.703 pulse shapes may be selected. Pulse shaping and signal level are controlled by "line length select" inputs as shown in Table 3. The output options in Table 3 are specified with a 1:1.15 transmitter transformer turns ratio for T1 and a 1:1 turns ratio for E1 without external series resistors. Other turns ratios may be used if approriate resistors are placed in series with the TTIP and TRING pins. Table A1 in the applications section lists other combinations which can be used to provide transmitter impedance matching. For T1 DSX-1 applications, line lengths from 0 to 655 feet (as measured from the transmitter to the DSX-1 cross connect) may be selected. The five partition arrangement in Table 3 meets ANSI T1.102 and AT&T CB-119 requirements when using #22 ABAM cable. A typical output pulse is shown in Figure 8. These pulse settings can also be used to meet CCITT pulse shape requirements for 1.544 MHz operation. For T1 Network Interface applications, two additional options are provided. Note that the optimal pulse width for Part 68 (324 ns) is narrower than the optimal pulse width for DSX-1 (350 ns). The CS61304A automatically adjusts the pulse width based upon the "line length" selection made. The E1 G.703 pulse shape is supported with line length selections LEN2/1/0 = 0/0/0 and 0/0/1. The pulse width will meet the G.703 pulse shape template shown in Figure 9, and specified in Table 4. 10 LEN2 LEN1 LEN0 Option Selected Application 0 1 1 0-133 ft DSX-1 1 0 0 133-266 ft ABAM 1 0 1 266-399 ft (AT&T 600B 1 1 0 399-533 ft or 600C) 1 1 1 533-655 ft 0 0 0 E1 75Ω coax CCITT G.703 0 0 1 120Ω twisted-pair 0 1 0 FCC PART 68, OPT. A Network Interface 0 1 1 ANSI T1.403 Table 3. Line Length Selection The CS61304A transmitter provides short-circuit current limiting protection and meets OFTEL OTR-001 short-circuit current limiting requirements for E1 applications. The CS61304A will detect a static TCLK, and will force TTIP and TRING low to prevent transmission when data is not present. When any transmit control pin (TAOS, LEN0-2 or LLOOP) is toggled, the transmitter outputs will require approximately 22 bit periods to stabilize. The transmitter will take longer to stabilize when RLOOP is selected because the timing circuitry must adjust to the new frequency. NORMALIZED AMPLITUDE ANSI T1.102, AT&T CB 119 SPECIFICATIONS 1.0 0.5 0 OUTPUT PULSE SHAPE -0.5 0 250 500 750 1000 TIME (nanoseconds) Figure 8. Typical Pulse Shape at DSX-1 Cross Connect DS156F1 DS156PP2 CS61304A CS61304A Percent of nominal peak voltage Receiver 269 ns 120 110 244 ns 100 194 ns 90 80 50 10 Nominal Pulse 0 -10 -20 219 ns 488 ns Figure 9. Mask of the Pulse at the 2048 kbps Interface Transmit All Ones Select The transmitter provides for all ones insertion at the frequency of TCLK. Transmit all ones is selected when TAOS goes high, and causes continuous ones to be transmitted on the line (TTIP and TRING). In this mode, the TPOS and TNEG (or TDATA) inputs are ignored. If Remote Loopback is in effect, any TAOS request will be ignored. The receiver extracts data and clock from an AMI (Alternate Mark Inversion) coded signal and outputs clock and synchronized data. The receiver is sensitive to signals over the entire range of ABAM cable lengths and requires no equalization or ALBO (Automatic Line Build Out) circuits. The signal is received on both ends of a centertapped, center-grounded transformer. The transformer is center tapped on the IC side. The clock and data recovery circuit exceeds the jitter tolerance specifications of Publications 43802, 43801, AT&T 62411, TR-TSY-000170, and CCITT REC. G.823. A block diagram of the receiver is shown in Figure 10. The two leads of the transformer (RTIP and RRING) have opposite polarity allowing the receiver to treat RTIP and RRING as unipolar signals. Comparators are used to detect pulses on RTIP and RRING. The comparator thresholds are dynamically established at a percent of the peak level (50% of peak for E1, 65% of peak for T1; with the slicing level selected by LEN2/1/0 inputs). The leading edge of an incoming data pulse triggers the clock phase selector. The phase selector chooses one of the 13 available phases which the delay line produces for each bit period. The outFo r c o ax i al c abl e, For shielded twisted 75Ω load a nd pair, 120Ω load and transformer specified transformer specified in Application Section. in Application Section. 2.37 V 3V 0 ±0.237 V 0 ±0.30 V 244 ns Nominal peak voltage of a mark (pulse) Peak voltage of a space (no pulse) Nominal pulse width Ratio of the amplitudes of positive and negative 0.95 to 1.05* pulses at the center of the pulse interval Ratio of the widths of positive and negative 0.95 to 1.05* pulses at the nominal half amplitude * When configured with a 0.47 µF nonpolarized capacitor in series with the TX transformer primary as shown in Figures A1, A2 and A3. Table 4. CCITT G.703 Specifications DS156F1 DS156PP2 11 11 CS61304A CS61304A RTIP 1:2 Data Level Slicer Data Sampling & Clock Extraction Edge Detector Clock Phase Selector RRING RPOS Jitter Attenuator RNEG RCLK Continuously Calibrated Delay Line Figure 10. Receiver Block Diagram put from the phase selector feeds the clock and data recovery circuits which generate the recovered clock and sample the incoming signal at appropriate intervals to recover the data. Data sampling will continue at the periods selected by the phase selector until an incoming pulse deviates enough to cause a new phase to be selected for data sampling. The phases of the delay line are selected and updated to allow as much as 0.4 UI of jitter from 10 kHz to 100 kHz, without error. The jitter tolerance of the receiver exceeds that shown in Figure 11. Additionally, this method of clock and data recovery is tolerant of long strings of consecutive zeros. The data sampler will continuously sample data based on its last input until a new pulse arrives to update the clock phase selector. The delay line is continuously calibrated using the crystal oscillator reference clock. The delay line produces 13 phases for each cycle of the reference clock. In effect, the 13 phases are analogous to a 20 MHz clock when the reference clock is 1.544 MHz. This implementation utilizes the benefits of a 20 MHz clock for clock recovery without actually having the clock present to impede analog circuit performance. 12 Minimum Performance 300 138 100 AT&T 62411 28 10 PEAK-TO-PEAK JITTER (unit intervals) 1 .4 .1 1 10 100 300 700 1k 10k 100k JITTER FREQUENCY (Hz) Figure 11. Minimum Input Jitter Tolerance of Receiver (Clock Recovery Circuit and Jitter Attenuator) In the Hardware Mode, data at RPOS and RNEG should be sampled on the rising edge of RCLK, the recovered clock. In the Extended Hardware Mode, data at RDATA should be sampled on the falling edge of RCLK. In the Host Mode, CLKE determines the clock polarity for which output data should be sampled as shown in Table 5. DS156F1 DS156PP2 CS61304A CS61304A MODE (pin 5) CLKE (pin 28) DATA CLOCK Clock Edge for Valid Data LOW (<0.2V) X RPOS RNEG RCLK RCLK Rising Rising HIGH (>(V+) - 0.2V) LOW RPOS RNEG SDO RCLK RCLK SCLK Rising Rising Falling HIGH (>(V+) - 0.2V) HIGH RPOS RNEG SDO RCLK RCLK SCLK Falling Falling Rising MIDDLE (2.5V) X RDATA RCLK Falling recovered clock and the ACLKI reference clock. This means that RCLK will smoothly transition to the new frequency. If ACLKI is not present, then the crystal oscillator of the jitter attenuator is forced to its center frequency. Table 6 shows the status of RCLK upon LOS. Crystal ACLKI present? present? X = Don’t care Table 5. Data Output/Clock Relationship No Yes ACLKI Yes No Centered Crystal Yes Yes ACLKI via the Jitter Attenuator Table 6. RCLK Status at LOS Loss of Signal The receiver reports loss of signal by setting the Loss of Signal pin, LOS, high. If the serial interface is used, the LOS bit will be set and an interrupt will be issued on INT (unless disabled). LOS will return low (asserting the INT pin again in Host Mode) upon receipt of 3 ones in 32 bit periods with no more than 15 consecutive zeros. Note that in the Host Mode, LOS is simultaneously available from both the register and pin 12. RPOS/RNEG or RDATA are forced low during LOS unless the jitter attenuator is disabled. (See "Jitter Attenuator") Jitter Attenuator The jitter attenuator reduces wander and jitter in the recovered clock signal. It consists of a FIFO, a crystal oscillator, a set of load capacitors for the crystal, and control logic. The jitter attenuator exceeds the jitter attenuation requirements of Publications 43802 and REC. G.742. A typical jitter attenuation curve is shown in Figure 12. The CS61304A fully meets AT&T 62411 jitter attenuation requirements. 0 a) Minimum Attenuation Limit 10 Attenuation in dB The receiver will indicate loss of signal after power-up, reset or upon receiving 175 consecutive zeros. A digital counter counts received zeros, based on RCLK cycles. A zero is received when the RTIP and RRING inputs are below the input comparator slicing threshold level established by the peak detector. After the signal is removed for a period of time the data slicing th resho ld level decays to ap proximately 300 mVpeak. Source of RCLK 62411 Requirements 20 30 40 b) Maximum Attunuation Limit 50 Measured Performance 60 If ACLKI is present during the LOS state, ACLKI is switched into the input of the jitter attenuator, resulting in RCLK matching the frequency of ACLKI. The jitter attenuator buffers any instantaneous changes in phase between the last DS156F1 DS156PP2 1 10 100 1k 10 k Frequency in Hz Figure 12. Typical Jitter Transfer Function 13 13 CS61304A CS61304A The jitter attenuator works in the following manner. The recovered clock and data are input to the FIFO with the recovered clock controlling the FIFO’s write pointer. The crystal oscillator controls the FIFO’s read pointer which reads data out of the FIFO and presents it at RPOS and RNEG (or RDATA). The update rate of the read pointer is analogous to RCLK. By changing the load capacitance that the IC presents to the crystal, the oscillation frequency is adjusted to the average frequency of the recovered signal. Logic determines the phase relationship between the read and write pointers and decides how to adjust the load capacitance of the crystal. Jitter is absorbed in the FIFO. The FIFO in the jitter attenuator is designed to prevent overflow and underflow. If the jitter amplitude becomes very large, the read and write pointers may get very close together. Should they attempt to cross, the oscillator’s divide by four circuit adjusts by performing a divide by 3 1/2 or divide by 4 1/2 to prevent data loss from overflow or underflow. The jitter attenuator may be bypassed by pulling XTALIN to RV+ through a 1 kΩ resistor and providing a 1.544 MHz (or 2.048 MHz) clock on ACLKI. RCLK may exhibit quantization jitter of approximately 1/13 UIpp and a duty cycle of approximately 30% (70%) when the attenuator is disabled. mitted on TTIP and TRING, unless TAOS has been selected in which case, AMI-coded continuous ones are transmitted at the TCLK frequency. The receiver RTIP and RRING inputs are ignored when local loopback is in effect. Remote Loopback Remote loopback is selected by taking RLOOP, pin 26, high or by setting the RLOOP register bit via the serial interface. In remote loopback, the recovered clock and data input on RTIP and RRING are sent through the jitter attenuator and back out on the line via TTIP and TRING. Selecting remote loopback overrides any TAOS request (see Table 7). The recovered incoming signals are also sent to RCLK, RPOS and RNEG (or RDATA). A remote loopback occurs in response to RLOOP going high. Simultaneous selection of local and remote loopback modes is not valid (see Reset). In the Extended Hardware Mode the transmitted data is looped before the AMI/B8ZS/HDB3 encoder/decoder during remote loopback so that the transmitted signal matches the received signal, even in the presence of received bipolar violations. Data output on RDATA is decoded, however, if RCODE is low. Local Loopback Local loopback is selected by taking LLOOP, pin 27, high or by setting the LLOOP register bit via the serial interface. The local loopback mode takes clock and data presented on TCLK, TPOS, and TNEG (or TDATA), sends it through the jitter attenuator and outputs it at RCLK, RPOS and RNEG (or RDATA). If the jitter attenuator is disabled, it is bypassed. Inputs to the transmitter are still trans14 RLOOP TAOS Input Input Signal Signal Source of Data for TTIP & TRING Source of Clock for TTIP & TRING 0 0 TDATA TCLK 0 1 all 1s TCLK 1 X RTIP & RRING RTIP & RRING (RCLK) Notes: 1. X = Don’t Care. The identified All Ones Select input is ignored when the indicated loopback is in effect. 2. Logic 1 indicates that Loopback or All Ones option is selected. Table 7. Interaction of RLOOP with TAOS DS156F1 DS156PP2 CS61304A CS61304A Driver Performance Monitor To aid in early detection and easy isolation of non-functioning links, the IC is able to monitor transmit drive performance and report when the driver is no longer operational. This feature can be used to monitor either the device’s performance or the performance of a neighboring driver. The driver performance monitor indicator is normally low, and goes high upon detecting a driver failure. The driver performance monitor consists of an activity detector that monitors the transmitted signal when MTIP is connected to TTIP and MRING is connected to TRING. DPM will go high if the absolute difference between MTIP and MRING does not transition above or below a threshold level within a time-out period. In the Host Mode, DPM is available from both the register and pin 11. LEN 2/1/0 TCODE (Transmit Encoder Selection) RCODE (Receiver Decoder Selection) LOW HIGH LOW HIGH 000 010-111 HDB3 Encoder B8ZS Encoder AMI Encoder HDB3 Decoder B8ZS Decoder AMI Decoder Table 8. Encoder/Decoder Selection Parallel Chip Select Whenever more than one line interface IC resides on the same circuit board, the effectiveness of the driver performance monitor can be maximized by having each IC monitor performance of a neighboring IC, rather than having it monitor its own performance. In the Extended Hardware Mode, PCS can be used to gate the digital control inputs: TCODE, RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP and TAOS. Inputs are accepted on these pins only when PCS is low and will immediately change the operating state of the device. Therefore, when cycling PCS to update the operating state, the digital control inputs should be stable for the entire PCS low period. The digital control inputs are ignored when PCS is high. Alarm Indication Signal Power On Reset / Reset In the Extended Hardware Mode, the receiver sets the output pin AIS high when less than 3 zeros are detected out of 2048 bit periods. AIS returns low when 4 or more zeros, out of 2048 bits, are detected. Upon power-up, the IC is held in a static state until the supply crosses a threshold of approximately 3 Volts. When this threshold is crossed, the device will delay for about 10 ms to allow the power supply to reach operating voltage. After this delay, calibration of the delay lines used in the transmit and receive sections commences. The delay lines can be calibrated only if a reference clock is present. The reference clock for the receiver is provided by the crystal oscillator, or ACLKI if the oscillator is disabled. The reference clock for the transmitter is provided by TCLK. The initial calibration should take less than 20 ms. Line Code Encoder/Decoder In the Extended Hardware Mode, three line codes are available: AMI, B8ZS and HDB3. The input to the encoder is TDATA. The outputs from the decoder are RDATA and BPV (Bipolar Violation Strobe). The encoder and decoder are selected using the LEN2, LEN1, LEN0, TCODE and RCODE pins as shown in Table 8. DS156F1 DS156PP2 15 15 CS61304A CS61304A In operation, the delay lines are continuously calibrated, making the performance of the device independent of power supply or temperature variations. The continuous calibration function forgoes any requirement to reset the line interface when in operation. However, a reset function is available which will clear all registers. output data is stable and valid is determined by CLKE as shown in Table 5. Data transfers are terminated by setting CS high. CS may go high no sooner than 50 ns after the rising edge of the SCLK cycle corresponding to the last write bit. For a serial data read, CS may go high any time to terminate the output. In the Hardware and Extended Hardware Modes, a reset request is made by simultaneously setting both the RLOOP and LLOOP pins high for at least 200 ns. Reset will initiate on the falling edge of the reset request (falling edge of RLOOP and LLOOP). In the Host Mode, a reset is initiated by simultaneously writing RLOOP and LLOOP to the register. In either mode, a reset will set all registers to 0 and force the oscillator to its center frequency before initiating calibration. A reset will also set LOS high. Figure 13 shows the timing relationships for data transfers when CLKE = 1. When CLKE = 1, data bit D7 is held until the falling edge of the 16th clock cycle. When CLKE = 0, data bit D7 is held until the rising edge of the 17th clock cycle. SDO goes High-Z after CS goes high or at the end of the hold period of data bit D7. Serial Interface In the Host Mode, pins 23 through 28 serve as a microprocessor/microcontroller interface. One on-board register can be written to via the SDI pin or read from via the SDO pin at the clock rate determined by SCLK. Through this register, a host controller can be used to control operational characteristics and monitor device status. The serial port read/write timing is independent of the system transmit and receive timing. An address/command byte, shown in Table 9, precedes a data register. The first bit of the address/command byte determines whether a read or a write is requested. The next six bits contain the address. The line interface responds to address 16 (0010000). The last bit is ignored. LSB, first bit 0 1 2 3 4 5 6 7 MSB, last bit R/W ADD0 ADD1 ADD2 ADD3 ADD4 X Read/Write Select; 0 = write, 1 = read LSB of address, Must be 0 Must be 0 Must be 0 Must be 0 Must be 1 Reserved - Must be 0 Don’t Care Table 9. Address/Command Byte Data transfers are initiated by taking the chip select input, CS, low (CS must initially be high). Address and input data bits are clocked in on the rising edge of SCLK. The clock edge on which CS SCLK SDI R/W 0 0 0 0 1 0 0 D0 D1 D2 D3 D4 D5 Data Input/Output D6 D0 D1 D2 D6 Address/Command Byte SDO D3 D4 D5 D7 D7 Figure 13. Input/Output Timing 16 DS156F1 DS156PP2 CS61304A CS61304A The data register, shown in Table 10, can be written to the serial port. Data is input on the eight clock cycles immediately following the address/command byte. Bits 0 and 1 are used to clear an interrupt issued from the INT pin, which occurs in response to a loss of signal or a problem with the output driver. LSB: first bit in 0 1 2 3 4 5 6 MSB: last bit in 7 clr LOS clr DPM LEN0 LEN1 LEN2 RLOOP LLOOP TAOS Clear Loss of Signal Clear Driver Performance Monitor Bit 0 - Line Length Select Bit 1 - Line Length Select Bit 2 - Line Lenght Select Remote Loopback Local Loopback Transmit All Ones Select Table 10. Input Data Register Writing a "1" to either "Clear LOS" or "Clear DPM" over the serial interface has three effects: 1) The current interrupt on the serial interface will be cleared. (Note that simply reading the register bits will not clear the interrupt). 2) Output data bits 5, 6 and 7 will be reset as appropriate. 3) Future interrupts for the corresponding LOS or DPM will be prevented from occurring. Writing a "0" to either "Clear LOS" or "Clear DPM" enables the corresponding interrupt for LOS or DPM. LSB: first bit in 0 1 2 3 4 LOS DPM LEN0 LEN1 LEN2 Loss of Signal Driver Performance Monitor Bit 0 - Line Length Select Bit 1 - Line Length Select Bit 2 - Line Lenght Select Table 11. Output Data Bits 0 - 4 Bits 5 6 0 0 0 0 0 1 0 1 1 0 1 0 7 0 1 0 1 0 1 Status Reset has occurred or no program input. TAOS in effect. LLOOP in effect. TAOS/LLOOP in effect. RLOOP in effect DPM changed state since last "clear DPM" occured. 1 1 0 LOS changed state since last "clear LOS" occured. 1 1 1 LOS and DPM have changed state since last "clear LOS" and "clear DPM". Table 12. Coding for Serial Output bits 5,6,7 Output data from the serial interface is presented as shown in Tables 11 and 12. Bits 2, 3 and 4 can be read to verify line length selection. Bits 5, 6 and 7 must be decoded. Codes 101, 110 and 111 (Bits 5, 6 and 7) indicate intermittent loss of signal and/or driver problems. SDO goes to a high impedance state when not in use. SDO and SDI may be tied together in applications where the host processor has a bi-directional I/O port. DS156F1 DS156PP2 17 17 CS61304A CS61304A Power Supply The device operates from a single +5 Volt supply. Separate pins for transmit and receive supplies provide internal isolation. These pins should be connected externally near the device and decoupled to their respective grounds. TV+ must not exceed RV+ by more than 0.3V. Decoupling and filtering of the power supplies is crucial for the proper operation of the analog circuits in both the transmit and receive paths. A 1.0 µF capacitor should be connected between TV+ and TGND, and a 0.1 µF capacitor should be connected between RV+ and RGND. Use mylar or ceramic capacitors and place them as closely as possible to their respective power supply pins. A 68 µF tantalum capacitor should be added close to the RV+/RGND supply. Wire-wrap breadboarding of the line interface is not recommended because lead resistance and inductance serve to defeat the function of the decoupling capacitors. 18 Schematic & Layout Review Service Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering. C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2 DS156F1 DS156PP2 CS61304A CS61304A PIN DESCRIPTIONS Hardware Mode ACLKI TCLK TPOS TNEG MODE RNEG RPOS RCLK XTALIN XTALOUT DPM LOS TTIP TGND 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 TAOS LLOOP RLOOP LEN2 LEN1 LEN0 RGND RV+ RRING RTIP MRING MTIP TRING TV+ ACLKI TCLK TAOS TPOS LLOOP TNEG RLOOP MODE LEN2 RNEG RPOS RCLK XTALIN XTALOUT 5 4 3 2 1 28 27 26 25 24 6 23 7 8 top view 22 9 21 10 20 19 11 LEN1 LEN0 RGND RV+ RRING 12 13 14 15 16 17 18 DPM RTIP LOS MRING TTIP MTIP TGND TRING TV+ DS156F1 DS156PP2 19 19 CS61304A CS61304A Extended Hardware Mode ACLKI TCLK TDATA TCODE MODE BPV RDATA RCLK XTALIN XTALOUT AIS LOS TTIP TGND 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 TAOS LLOOP RLOOP LEN2 LEN1 LEN0 RGND RV+ RRING RTIP PCS RCODE TRING TV+ ACLKI TCLK TAOS TDATA LLOOP TCODE RLOOP MODE BPV RDATA RCLK XTALIN XTALOUT LEN2 5 4 3 2 1 28 27 26 25 24 6 23 7 8 top view 22 9 21 10 20 19 11 LEN1 LEN0 RGND RV+ RRING 12 13 14 15 16 17 18 AIS RTIP LOS PCS TTIP RCODE TGND TRING TV+ 20 DS156F1 DS156PP2 CS61304A CS61304A Host Mode ACLKI TCLK TPOS TNEG MODE RNEG RPOS RCLK XTALIN XTALOUT DPM LOS TTIP TGND 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 CLKE SCLK CS SDO SDI INT RGND RV+ RRING RTIP MRING MTIP TRING TV+ ACLKI TCLK CLKE TPOS SCLK TNEG CS MODE SDO RNEG RPOS RCLK XTALIN XTALOUT 5 4 3 2 1 28 27 26 25 24 6 23 7 8 top view 22 9 21 10 20 19 11 SDI INT RGND RV+ RRING 12 13 14 15 16 17 18 DPM RTIP LOS MRING TTIP MTIP TGND TRING TV+ DS156F1 DS156PP2 21 21 CS61304A CS61304A Power Supplies RGND - Ground, Pin 22. Power supply ground for all subcircuits except the transmit driver; typically 0 Volts. RV+ - Power Supply, Pin 21. Power supply for all subcircuits except the transmit driver; typically +5 Volts. TGND - Ground, Transmit Driver, Pin 14. Power supply ground for the transmit driver; typically 0 Volts. TV+ - Power Supply, Transmit Driver, Pin 15. Power supply for the transmit driver; typically +5 Volts. TV+ must not exceed RV+ by more than 0.3 V. Oscillator XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10. A 6.176 MHz (or 8.192 MHz) crystal should be connected across these pins. If a 1.544 MHz (or 2.048 MHz) clock is provided on ACLKI (pin 1), the jitter attenuator may be disabled by tying XTALIN, Pin 9 to RV+ through a 1 kΩ resistor, and floating XTALOUT, Pin 10. Overdriving the oscillator with an external clock is not supported. Control ACLKI - Alternate External Clock Input, Pin 1. A 1.544 MHz (or 2.048 MHz) clock may be input to ACLKI, or this pin must be tied to ground. During LOS, the ACLKI input signal, if present, is output on RCLK through the jitter attenuator. CLKE - Clock Edge, Pin 28. (Host Mode) Setting CLKE to logic 1 causes RPOS and RNEG to be valid on the falling edge of RCLK, and SDO to be valid on the rising edge of SCLK. Conversely, setting CLKE to logic 0 causes RPOS and RNEG to be valid on the rising edge of RCLK, and SDO to be valid on the falling edge of SCLK. CS - Chip Select, Pin 26. (Host Mode) This pin must transition from high to low to read or write the serial port. INT - Receive Alarm Interrupt, Pin 23. (Host Mode) Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing "clear LOS" or "clear DPM" to the register. INT is an open drain output and should be tied to the power supply through a resistor. 22 DS156F1 DS156PP2 CS61304A CS61304A LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended Hardware Modes) Determines the shape and amplitude of the transmitted pulse to accommodate several cable types and lengths. See Table 3 for information on line length selection. Also controls the receiver slicing level and the line code in Extended Hardware Mode. LLOOP - Local Loopback, Pin 27. (Hardware and Extended Hardware Modes) Setting LLOOP to a logic 1 routes the transmit clock and data through the jitter attenuator to the receive clock and data pins. TCLK and TPOS/TNEG (or TDATA) are still transmitted unless overridden by a TAOS request. Inputs on RTIP and RRING are ignored. MODE - Mode Select, Pin 5. Driving the MODE pin high puts the line interface in the Host Mode. In the host mode, a serial control port is used to control the line interface and determine its status. Grounding the MODE pin puts the line interface in the Hardware Mode, where configuration and status are controlled by discrete pins. Floating the MODE pin or driving it to +2.5 V selects the Extended Hardware Mode, where configuration and status are controlled by discrete pins. When floating MODE, there should be no external load on the pin. MODE defines the status of 13 pins (see Table 2). PCS - Parallel Chip Select, Pin 18. (Extended Hardware Mode) Setting PCS high causes the line interface to ignore the TCODE, RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP and TAOS inputs. RCODE - Receiver Decoder Select, Pin 17. (Extended Hardware Mode) Setting RCODE low enables B8ZS or HDB3 zero substitution in the receiver decoder. Setting RCODE high enables the AMI receiver decoder (see Table 8). RLOOP - Remote Loopback, Pin 26. (Hardware and Extended Hardware Modes) Setting RLOOP to a logic 1 causes the recovered clock and data to be sent through the jitter attenuator (if active) and through the driver back to the line. The recovered signal is also sent to RCLK and RPOS/RNEG (or RDATA). Any TAOS request is ignored. Simultaneously taking RLOOP and LLOOP high for at least 200 ns initiates a device reset. SCLK - Serial Clock, Pin 27. (Host Mode) Clock used to read or write the serial port registers. SCLK can be either high or low when the line interface is selected using the CS pin. SDI - Serial Data Input, Pin 24. (Host Mode) Data for the on-chip register. Sampled on the rising edge of SCLK. SDO - Serial Data Output, Pin 25. (Host Mode) Status and control information from the on-chip register. If CLKE is high SDO is valid on the rising edge of SCLK. If CLKE is low SDO is valid on the falling edge of SCLK. This pin goes to a high-impedance state when the serial port is being written to or after bit D7 is output. DS156F1 DS156PP2 23 23 CS61304A CS61304A TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes) Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined by TCLK. TCODE - Transmitter Encoder Select, Pin 4. (Extended Hardware Mode) Setting TCODE low enables B8ZS or HDB3 zero substitution in the transmitter encoder. Setting TCODE high enables the AMI transmitter encoder . Data RCLK - Recovered Clock, Pin 8. The receiver recovered clock generated by the jitter attenuator is output on this pin.When in the loss of signal state ACLKI (if present) is output on RCLK via the jitter attenuator. If ACLKI is not present during LOS, RCLK is forced to the center frequency of the crystal oscillator. RDATA - Receive Data - Pin 7. (Extended Hardware Mode) Data recovered from the RTIP and RRING inputs is output at this pin, after being decoded by the line code decoder. RDATA is NRZ. RDATA is stable and valid on the falling edge of RCLK. RPOS, RNEG - Receive Positive Data, Receive Negative Data, Pins 6 and 7. (Hardware and Host Modes) The receiver recovered NRZ digital data is output on these pins. In the Hardware Mode, RPOS and RNEG are stable and valid on the rising edge of RCLK. In the Host Mode, CLKE determines the clock edge for which RPOS and RNEG are stable and valid. See Table 5. A positive pulse (with respect to ground) received on the RTIP pin generates a logic 1 on RPOS, and a positive pulse received on the RRING pin generates a logic 1 on RNEG. RTIP, RRING - Receive Tip, Receive Ring, Pins 19 and 20. The AMI receive signal is input to these pins. A center-tapped, center-grounded, 2:1, step-up transformer is required on these inputs, as shown in Figure A1 in the Applications section. Data and clock are recovered and output on RCLK and RPOS/RNEG or RDATA. TCLK - Transmit Clock, Pin 2. The1.544 MHz (or 2.048 MHz) transmit clock is input on this pin. TPOS/TNEG or TDATA are sampled on the falling edge of TCLK. TDATA - Transmit Data, Pin 3. (Extended Hardware Mode) Transmitter NRZ input data which passes through the line code encoder, and is then driven on to the line through TTIP and TRING. TDATA is sampled on the falling edge of TCLK. TPOS, TNEG - Transmit Positive Data, Transmit Negative Data, Pins 3 and 4. (Hardware and Host Modes) Inputs for clock and data to be transmitted. The signal is driven on to the line through TTIP and TRING. TPOS and TNEG are sampled on the falling edge of TCLK. A TPOS input causes a positive pulse to be transmitted, while a TNEG input causes a negative pulse to be transmitted. 24 DS156F1 DS156PP2 CS61304A CS61304A TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16. The AMI signal is driven to the line through these pins. The transmitter output is designed to drive a 75 Ω load between TTIP and TRING. A transformer is required as shown in Table A1. Status AIS - Alarm Indication Signal, Pin 11. (Extended Hardware Mode) AIS goes high when unframed all-ones condition (blue alarm) is detected, using the detection criteria of less than three zeros out of 2048 bit periods. BPV- Bipolar Violation Strobe, Pin 6. (Extended Hardware Mode) BPV strobes high when a bipolar violation is detected in the received signal. B8ZS (or HDB3) zero substitutions are not flagged as bipolar violations if the B8ZS (or HDB3) decoder has been enabled. DPM - Driver Performance Monitor, Pin 11. (Hardware and Host Modes) DPM goes high if no activity is detected on MTIP and MRING. LOS - Loss of Signal, Pin 12. LOS goes high when 175 consecutive zeros have been received. LOS returns low when 3 ones are received within 32 bit periods with no more than 15 consecutive zeros. When in the loss of signal state RPOS/RNEG or RDATA are forced low, and ACLKI (if present) is output on RCLK via the jitter attenuator. If ACLKI is not present during LOS, RCLK is forced to the center frequency of the crystal oscillator. MTIP, MRING - Monitor Tip, Monitor Ring, Pins 17 and 18. (Hardware and Host Modes) These pins are normally connected to TTIP and TRING and monitor the output of a line interface IC. If the INT pin in the Host mode is used, and the monitor is not used, writing a 1 to the "clear DPM" bit will prevent an interrupt from the driver performance monitor. DS156F1 DS156PP2 25 25 CS61304A CS61304A 15 28 28 pin Plastic DIP E1 1 DIM A A1 B B1 C D E1 e1 eA L 14 D A SEATING PLANE A1 L ∝ e1 B1 B C eA ∝ NOTES: 1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN 0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH. MILLIMETERS MIN NOM MAX 3.94 4.32 5.08 0.51 0.76 1.02 0.36 0.46 0.56 1.02 1.27 1.65 0.20 0.25 0.38 36.45 36.83 37.21 13.72 13.97 14.22 2.41 2.54 2.67 15.87 15.24 3.18 3.81 0° 15° MIN 0.155 0.020 0.014 0.040 0.008 1.435 0.540 0.095 0.600 0.125 0° INCHES NOM 0.170 0.030 0.018 0.050 0.010 1.450 0.550 0.100 - MAX 0.200 0.040 0.022 0.065 0.015 1.465 0.560 0.105 0.625 0.150 15° 28-pin PLCC 28 MILLIMETERS E1 E MIN NOM MAX A 4.20 4.45 4.57 0.165 0.175 0.180 A1 2.29 2.79 3.04 0.090 0.110 0.120 B 0.33 0.41 0.53 0.013 0.016 0.021 D/E D1 D INCHES DIM MIN NOM MAX 12.32 12.45 12.57 0.485 0.490 0.495 D1/E1 11.43 11.51 11.58 0.450 0.453 0.456 D2/E2 9.91 10.41 10.92 0.390 0.410 0.430 e 1.19 1.27 1.35 0.047 0.050 0.053 e B A1 A D2/E2 26 DS156F1 DS156PP2 CS61304A APPLICATIONS +5V + 68 µF RGND Control & Monitor + 0.1 µF 21 28 CLKE 1 RV+ 1.0 µF TGND 15 TV+ SCLK 27 ACLKI CS 26 12 LOS INT 23 11 DPM SDI 24 SDO 25 RTIP 19 +5V 100 k Ω µP Serial Port RV+ Frame Format Encoder/ Decoder 5 MODE 7 RPOS 6 RNEG 8 RCLK 3 TPOS 4 TNEG 2 TCLK 9 XTL 10 CS61304A IN HOST MODE RGND 22 2 R1 RRING 20 MTIP 17 MRING 18 TRING 16 TTIP 13 XTALIN XTALOUT 1 TGND 14 RECEIVE 6 LINE 3 R2 5 2CT:1 PE-65351 0.47 µF R3 R4 2 1 6 TRANSMIT 5 LINE 1:1.15 PE-65388 Figure A1. T1 Host Mode Configuration Frequency Crystal MHz XTL 1.544 (T1) CXT6176 Cable Ω 100 2.048 (E1) CXT8192 120 75 R1 and R2 LEN2/1/0 Transmit R3 and R4 Typical TX Transformer Return Loss dB Ω Ω 200 0/1/1 - 1/1/1 1:1.15 0 0.5 1:2 9.4 20 1:2.3 9.4 28 240 0/0/0 1:1.26 0 0.5 0/0/0 1:2 8.7 12 0/0/1 1:1 0 0.5 0/0/1 1:2 15 30 150 0/0/0 1:1 0 0.5 0/0/0 1:2 9.4 24 0/0/1 1:1 10 5 0/0/1 1:2 14.3 12 Table A1. External Component Values Line Interface Figures A1-A3 show typical T1 and E1 line interface application circuits. Table A1 shows the external components which are specific to each application. Figure A1 illustrates a T1 interface in DS156PP2 the Host Mode. Figure A2 illustrates a 120 Ω E1 interface in the Hardware Mode. Figure A3 illustrates a 75 Ω E1 interface in the Extended Hardware Mode. 27 CS61304A +5V + 68 µF RGND Control & Monitor 28 TAOS 1 ACLKI RV+ TGND 15 TV+ RLOOP LEN0 23 27 LLOOP LEN1 24 12 LOS LEN2 25 RTIP 19 5 7 Line Length Setting DPM MODE CS61304A IN HARDWARE MODE RPOS 6 RNEG 8 RCLK 3 1 R1 RRING 20 R2 2 3 2CT:1 PE-65351 17 TPOS MTIP TNEG MRING 18 2 TCLK TRING 16 0.47 µF 2 TTIP 13 6 10 XTALIN XTALOUT RGND 22 RECEIVE 6 LINE 5 4 9 XTL 21 1.0 µF 26 11 Frame Format Encoder/ Decoder + 0.1 µF 1 TRANSMIT 5 LINE 1:1.26 PE-65389 TGND 14 Figure A2. 120 Ω, E1 Hardware Mode Configuration +5V + 68 µF RGND Control & Monitor 17 RCODE 18 PCS 6 RV+ TGND 15 TV+ BPV LEN0 23 TAOS LEN1 24 1 ACLKI LEN2 25 RTIP 19 27 LLOOP LOS 11 AIS 5 MODE 4 TCODE RCLK 3 TDATA 9 10 CS61304A IN EXTENDED HARDWARE MODE RRING 20 R2 2 3 RECEIVE 6 LINE 5 2CT:1 PE-65351 TCLK TRING 16 0.47 µF 2 TTIP 13 6 XTALIN XTALOUT 1 R1 RDATA 8 2 Line Length Setting RLOOP 12 7 XTL 21 1.0 µF 28 26 Frame Format Encoder/ Decoder + 0.1 µF RGND 22 3 TRANSMIT 5 LINE 1:1 PE-65389 TGND 14 Figure A3. 75 Ω, E1 Extended Hardware Mode Configuration 28 DS156PP2 CS61304A Parameter Turns Ratio Receiver Transmitter 1:2 CT ± 5% Primary Inductance 600 µH min. @ 772 kHz 1:1 ± 1.5 % for 75 Ω E1 1:1.15 ± 5 % for 100 Ω T1 1:1.26 ± 1.5 % for 120 Ω E1 1.5 mH min. @ 772 kHz Primary Leakage Inductance 1.3 µH max. @ 772 kHz 0.3 µH max. @ 772 kHz Secondary Leakage Inductance 0.4 µH max. @ 772 kHz 23 pF max. 0.4 µH max. @ 772 kHz 18 pF max. 16 V-µs min. for T1 12 V-µs min. for E1 16 V-µs min. for T1 12 V-µs min. for E1 Interwinding Capacitance ET-constant Table A2. Transformer Specifications The receiver transformer has a grounded center tap on the IC side. Resistors between the RTIP and RRING pins to ground provide the termination for the receive line. CXT6176 crystal be used for T1 applications and the CXT8192 crystal be used for E1 applications. The transmitter transformer matches the 75 Ω transmitter output impedance to the line impedance. Figures A1-A3 show a 0.47 µF capacitor in series with the transmit transformer primary. This capacitor is needed to prevent any output stage imbalance from resulting in a DC current through the transformer primary. This current might saturate the transformer producing an output offset level shift. For additional information on the requirements of AT&T 62411 and the design of an appropriate system synchronizer, please refer to the Crystal Semiconductor Application Notes: "AT&T 62411 Design Considerations – Jitter and Synchronization" and "Jitter Testing Procedures for Compliance with AT&T 62411". Transformers In some applications it is desirable to attenuate jitter from the signal to be transmitted. A CS61304A in local loopback mode can be used as a jitter attenuator. The inputs to the jitter attenuator are TPOS, TNEG, TCLK. The outputs from the jitter attenuator are RPOS, RNEG and RCLK. Recommended transmitter and receiver transformer specifications are shown in Table A2. The transformers in Table A3 are recommended for use with the CS61304A. Refer to the "Telecom Transformer Selection Guide" for detailed schematics which show how to connect the line interface IC with a particular transformer. Selecting an Oscillator Crystal Specific crystal parameters are required for proper operation of the jitter attenuator. It is recommended that the Crystal Semiconductor DS156PP2 Designing for AT&T 62411 Transmit Side Jitter Attenuation Line Protection Secondary protection components can be added to provide lightning surge and AC power-cross immunity. Refer to the "Telecom Line Protection Application Note" for detailed information on the different electrical safety standards and specific application circuit recommendations. 29 CS61304A Application RX: T1 & E1 Turns Ratio(s) 1:2CT TX: T1 1:1.15 TX: E1 (75 & 120 Ω) 1:1.26 1:1 RX &TX: T1 RX &TX: E1 (75 & 120 Ω) 1:2CT 1:1.15 1:2CT 1:1.26 1:1 1:2CT 1:1.15 1:2CT 1:1.26 1:1 1:2CT RX &TX: T1 RX &TX: E1 (75 & 120 Ω) RX : T1 & E1 TX: E1 (75 & 120 Ω) 1:1.26 1:1 Manufacturer Part Number Package Type Pulse Engineering Schott Bel Fuse Pulse Engineering Schott Bel Fuse Pulse Engineering Schott Bel Fuse Pulse Engineering Bel Fuse Pulse Engineering Bel Fuse PE-65351 67129300 0553-0013-HC PE-65388 67129310 0553-0013-RC PE-65389 67129320 0553-0013-SC PE-65565 0553-0013-7J PE-65566 0553-0013-8J 1.5 kV through-hole, single Pulse Engineering Bel Fuse Pulse Engineering Bel Fuse PE-65765 S553-0013-06 PE-65766 S553-0013-07 Pulse Engineering PE-65835 Pulse Engineering PE-65839 1.5 kV through-hole, single 1.5 kV through-hole, single 1.5 kV through-hole, dual 1.5 kV through-hole, dual 1.5 kVsurface-mount, dual 1.5 kV surface-mount, dual 3 kV through-hole, single EN60950, EN41003 approved 3 kV through-hole, single EN60950, EN41003 approved Table A3. Recommended Transformers Interfacing The CS61304A With the CS62180B T1 Transceiver TO HOST CONTROLLER To interface with the CS62180B, connect the devices as shown in Figure A4. In this case, the line interface and CS62180B are in Host Mode controlled by a microprocessor serial interface. If the line interface is used in Hardware Mode, then the line interface RCLK output must be inverted before being input to the CS62180B. If the CS61304A is used in Extended Hardware Mode, the RCLK output does not have to be inverted before being input to the CS62180B. 1.544 MHz CLOCK SIGNAL ACLK SCLK TCLK SDO TPOS TPOS SDI TNEG TNEG SCLK TCLK SDO SDI 100k CS INT CS RNEG RNEG CLKE RPOS RPOS MODE RCLK RCLK CS62180B V+ 22k V+ CS61304A Figure A4. Interfacing the CS61304A with a CS62180B (Host Mode) 30 DS156PP2 CS61304A ORDERING INFORMATION • Notes • Model Package Temperature 28-pin PLCC -40 to +85 °C CS61304A-IL ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp MSL Rating* Max Floor Life 225 °C 2 365 Days CS61304A-IL * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. REVISION HISTORY Revision Date Changes PP2 MAY 1996 Initial Release F1 SEP 2005 Updated device ordering info. Updated legal notice. Added MSL data.. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). 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