DIX 419 2 DIX4192 SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Integrated Digital Audio Interface Receiver and Transmitter FEATURES • • • Digital Audio Interface Transmitter (DIT) – Supports Sampling Rates Up to 216kHz – Includes Differential Line Driver and CMOS Buffered Outputs – Block-Sized Data Buffers for Both Channel Status and User Data – Status Registers and Interrupt Generation for Flag and Error Conditions Digital Audio Interface Receiver (DIR) – PLL Lock Range Includes Sampling Rates from 20kHz to 216kHz – Includes Four Differential Input Line Receivers and an Input Multiplexer – Bypass Multiplexer Routes Line Receiver Outputs to Line Driver and Buffer Outputs – Block-Sized Data Buffers for Both Channel Status and User Data – Automatic Detection of Non-PCM Audio Streams (DTS CD/LD and IEC 61937 formats) – Audio CD Q-Channel Sub-Code Decoding and Data Buffer – Status Registers and Interrupt Generation for Flag and Error Conditions – Low Jitter Recovered Clock Output User-Selectable Serial Host Interface: SPI™ or I2C™ – Provides Access to On-Chip Registers and Data Buffers • • • • • Two Audio Serial Ports (Ports A and B) – Synchronous Serial Interface to External Signal Processors, Data Converters, and Logic – Slave or Master Mode Operation with Sampling Rates up to 216kHz – Supports Left-Justified, Right-Justified, and Philips I2S™ Data Formats – Supports Audio Data Word Lengths Up to 24 Bits Four General-Purpose Digital Outputs – Multifunction Programmable Via Control Registers Extensive Power-Down Support – Functional Blocks May Be Disabled Individually When Not In Use Operates From +1.8V Core and +3.3V I/O Power Supplies Small TQFP-48 Package, Compatible with the SRC4382 and SRC4392 APPLICATIONS • • • • • • • DIGITAL AUDIO RECORDERS AND MIXING DESKS DIGITAL AUDIO INTERFACES FOR COMPUTERS DIGITAL AUDIO ROUTERS AND DISTRIBUTION SYSTEMS BROADCAST STUDIO EQUIPMENT DVD/CD RECORDERS SURROUND SOUND DECODERS AND A/V RECEIVERS CAR AUDIO SYSTEMS Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Dolby is a registered trademark of Dolby Laboratories, Inc. I2C, I2S are trademarks of Koninklijke Philips Electronics N.V. SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 DESCRIPTION The DIX4192 is a highly-integrated CMOS device designed for use in professional and broadcast digital audio systems. The DIX4192 combines a digital audio interface receiver (DIR) and transmitter (DIT), two audio serial ports, and flexible distribution logic for interconnection of the function block data and clocks. The DIR and DIT are compatible with the AES3, S/PDIF, IEC 60958, and EIAJ CP-1201 interface standards. The audio serial ports and DIT may be operated at sampling rates up to 216kHz. The DIR lock range includes sampling rates from 20kHz to 216kHz. The DIX4192 is configured using on-chip control registers and data buffers, which are accessed through either a 4-wire serial peripheral interface (SPI) port, or a 2-wire Philips I2C bus interface. Status registers provide access to a variety of flag and error bits, which are derived from the various function blocks. An open-drain interrupt output pin is provided, and is supported by flexible interrupt reporting and mask options via control register settings. A master reset input pin is provided for initialization by a host processor or supervisory functions. The DIX4192 requires a +1.8V core logic supply, in addition to a +3.3V supply for powering portions of the DIR, DIT, and line driver and receiver functions. A separate logic I/O supply supports operation from +1.65V to +3.6V, providing compatibility with low voltage logic interfaces typically found on digital signal processors and programmable logic devices. The DIX4192 is available in a lead-free, TQFP-48 package, and is pin- and register-compatible with the Texas Instruments SRC4382 and SRC4392 products. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (1) PRODUCT PACKAGE PACKAGE DESIGNATOR DIX4192 TQFP-48 PFB SPECIFIED TEMPERATURE RANGE PACKAGE MARKING –40°C to +85°C DIX4192I ORDERING NUMBER TRANSPORT MEDIA, QUANTITY DIX4192IPFBT Tape and Reel, 250 DIX4192IPFBR Tape and Reel, 2000 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Power supplies VDD18 –0.3V to +2.0V VDD33 –0.3V to +4.0V VIO –0.3V to +4.0V VCC –0.3V to +4.0V Digital input voltage: Digital logic RXCKI, CPM, CS, CCLK, CDIN, CDOUT, INT, RST, MCLK, BLS, SYNC, BCKA, BCKB, LRCKA, LRCKB, SDINA, SDINB Line receiver input voltage (per pin) RX1+, RX1–, RX2+, RX2–, RX3+, RX3–, RX4+, RX4– Input current (all pins except power and ground) –40°C to +85°C Storage temperature 2 (VDD33 + 0.3) VPP ±10mA Ambient operating temperature (1) –0.3V to (VIO + 0.3V) –65°C to +150°C These limits are stress ratings only. Stresses beyond these limits may result in permanent damage. Extended exposure to absolute maximum ratings may degrade device reliability. Normal operation or performance at or beyond these limits is not specified or ensured. Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 ELECTRICAL CHARACTERISTICS: General, DIR, and DIT All specifications are at TA = +25°C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted. DIX4192 PARAMETER CONDITIONS MIN TYP MAX UNITS VIO V DIGITAL I/O CHARACTERISTICS (All I/O pins except line receivers and line driver) High-level input voltage, VIH 0.7 × VIO Low-level input voltage, VIL 0 High-level input current, IIH 0.5 0.3 × VIO V 10 µA 10 µA High-level output voltage, VOH IO = –4mA 0.8 × VIO VIO V Low-level output voltage, VOL IO = +4mA 0 0.2 × VIO Low-level input current, VIL 0.5 Input capacitance, CIN 3 V pF LINE RECEIVER INPUTS (RX1+, RX1–, RX2+, RX2–, RX3+, RX3–, RX4+, RX4–) Differential input sensitivity, VTH Voltage across a given differential input pair Input hysteresis, VHY 150 200 mV 150 mV 5.4 VPP LINE DRIVER OUTPUTS (TX+, TX–) Differential output voltage, VTXO RL = 110Ω Across TX+ and TX– MASTER CLOCK INPUT Master clock input (MCLK) frequency, fMCLK 1 27.7 MHz Master clock input (MCLK) duty cycle, fMCLKD 45 55 % DIGITAL AUDIO INTERFACE RECEIVER (DIR) PLL lock range 20 216 kHz Reference clock input (RXCKI) frequency, fRXCKI 3.5 27.7 MHz Reference clock input (RXCKI) duty cycle, fRXCKID 45 55 % Recovered clock output (RXCKO) frequency, fRXCKO 3.5 27.7 MHz Recovered clock output (RXCKO) duty cycle, fRXCKOD 45 55 Recovered clock output (RXCKO) intrinsic jitter % Measured cycle-to-cycle 250 ps RMS Measured cycle-to-cycle 200 ps RMS DIGITAL AUDIO INTERFACE TRANSMITTER (DIT) Intrinsic output jitter Submit Documentation Feedback 3 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 ELECTRICAL CHARACTERISTICS: Audio Serial Ports All specifications are at TA = +25°C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted. DIX4192 PARAMETER CONDITIONS MIN TYP MAX UNITS 216 kHz 13.824 MHz AUDIO SERIAL PORTS (Port A and Port B) LRCK clock frequency, fLRCK 0 LRCK clock duty cycle, tLRCKD 50 % BCK clock frequency, fBCK 0 BCK high pulse width, tBCKH 10 ns BCK low pulse width, tBCKL 10 ns Audio data Input (SDIN) setup time, tAIS 10 ns Audio data input (SDIN) hold time, tAISH 10 ns Audio data output (SDOUT) delay, tADD 10 ns ELECTRICAL CHARACTERISTICS: SPI Interface All specifications are at TA = +25°C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted. DIX4192 PARAMETER CONDITIONS MIN TYP MAX UNITS 40 MHz HOST INTERFACE: SPI Mode 4 Serial clock (CCLK) frequency, fCCLK 0 CS falling to CCLK rising, tCSCR 8 ns CCLK falling to CS rising, tCFCS 7 ns CDIN data setup time, tCDS 7 ns CDIN data hold time, tCDH 6 ns CCLK falling to CDOUT data valid, tCFDO 3 ns CS rising to CDOUT high-impedance, tCSZ 3 ns Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 ELECTRICAL CHARACTERISTICS: I2C Standard and Fast Modes All specifications are at TA = +25°C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted. DIX4192 PARAMETER HOST INTERFACE: I2C Standard CONDITIONS MIN TYP MAX UNITS 100 kHz Mode (1) SCL clock frequency, fSCL 0 Hold time repeated START condition, tHDSTA 4 µs Low period of SCL clock, tLOW 4.7 µs High period of SCL clock, tHIGH 4 µs Setup time repeated START condition, tSUSTA 4.7 Data hold time, tHDDAT 0 (2) Data setup time, tSUDAT 250 µs 3.45 (3) ns Rise time for Both SDA and SDL, tR 1000 Fall time for Both SDA and SDL, tF 300 Setup time for STOP condition, tSUSTO ns µs 4.7 Capacitive load for each bus Line, CB ns µs 4 Bus free time between START and STOP, tBUF µs 400 pF Noise margin at low level (including hysteresis), VNL 0.1 × VIO V Noise margin at high level (including hysteresis), VNH 0.2 × VIO V HOST INTERFACE: I2C Fast Mode (1) SCL clock frequency, fSCL 0 400 kHz Hold time repeated START condition, tHDSTA 0.6 µs Low period of SCL clock, tLOW 1.3 µs High period of SCL clock, tHIGH 0.6 µs Setup time repeated START condition, tSUSTA 0.6 Data hold time, tHDDAT 0 (2) Data setup time, tSUDAT 100 (4) µs 0.9 (3) ns Rise time for both SDA and SDL, tR 20 + 0.2CB (5) 300 Fall time for both SDA and SDL, tF 20 + 0.2CB (5) 300 Setup time for STOP condition, tSUSTO 0.6 Bus free time between START and STOP, tBUF 1.3 Spike pulse width suppressed by input filter, tSP 0 Capacitive load for Each bus Line, CB µs ns ns µs µs 50 ns 400 pF Noise margin at low level (including hysteresis), VNL 0.1 × VIO V Noise margin at high level (including hysteresis), VNH 0.2 × VIO V (1) (2) (3) (4) (5) All values referred to the VIH minimum and VIL maximum levels listed in the Digital I/O Characteristics section of the Electrical Characteristics: General, DIR, and DIT table. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH minimum input level) to bridge the undefined region of the falling edge of SCL. The maximum tHDDAT has only to be met if the device does not stretch the Low period (tLOW) of the SCL signal. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement that tSUDAT be 250ns (minimum) must then be met. For the DIX4192, this condition is automatically the case, since the device does not stretch the Low period of the SCL signal. CB is defined as the total capacitance of one bus line in picofarads (pF). If mixed with High-Speed mode devices, faster fall times are allowed. Submit Documentation Feedback 5 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 ELECTRICAL CHARACTERISTICS: Power Supplies All specifications are at TA = +25°C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted. DIX4192 PARAMETER CONDITIONS MIN TYP MAX UNITS VDD18 +1.65 +1.8 +1.95 V VDD33 +3.0 +3.3 +3.6 V VIO +1.65 +3.3 +3.6 V VCC +3.0 +3.3 +3.6 V POWER SUPPLIES Recommended supply voltage range Supply current: initial startup IDD18S VDD18 = +1.8V 10 µA IDD33S VDD33 = +3.3V 10 µA IIOS VIO = +3.3V 300 µA ICCS VCC = +3.3V 10 µA Supply current: quiescent All blocks powered up with no clocks applied IDD18Q VDD18 = +1.8V 2.3 mA IDD33Q VDD33 = +3.3V 0.6 mA IIOQ VIO = +3.3V 0.3 mA ICCQ VCC = +3.3V 6.3 mA Supply current: dynamic All blocks powered up, fS = 48kHz IDD18D VDD18 = +1.8V 5.1 mA IDD33D VDD33 = +3.3V 14.1 mA IIOD (1) VIO = +3.3V 46 mA ICCD VCC = +3.3V 7.4 mA Supply current: high sampling rate All blocks powered up, fS = 192kHz IDD18H VDD18 = +1.8V 6.7 mA IDD33H VDD33 = +3.3V 15 mA IIOH (1) VIO = +3.3V 47 mA ICCH VCC = +3.3V 7.5 mA All blocks powered down by default 1 mW Total power dissipation: initial startup Total power dissipation: quiescent All blocks powered up with no clocks applied 28 mW Total power dissipation: dynamic All blocks powered up, fS = 48kHz 233 mW Total power dissipation: high sampling Rate All blocks powered up, fS = 192kHz 242 mW (1) 6 All blocks powered down by default The typical VIO supply current is measured using the DIX4192EVM evaluation module with loading from the DAIMB mother-board circuitry. VIO supply current is dependent upon the loading on the logic output pins. Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 TIMING DIAGRAMS LRCK tBCKH BCK tAIS tBCKL SDIN tAIH tAOD SDOUT Figure 1. Audio Serial Port Timing tCFCS CS tCSCR tCDS CCLK tCDH CDIN Hi Z Hi Z CDOUT tCFDO tCSZ Figure 2. SPI Interface Timing tF SDA tLOW tSUDAT tR tHDSTA tSP tR tBUF tF SCL tHDSTA S S = Start Condition tSUSTA tHDDAT tHIGH tSUSTO R P R = Repeated Start Condition P = Stop Condition S Figure 3. I2C Standard and Fast Mode Timing Submit Documentation Feedback 7 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 BCKA SDINA TQFP LRCKA NC SDOUTA DGND3 VIO SDINB SDOUTB BCKB LRCKB Top View BGND PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 RX1+ 1 36 SYNC RX1- 2 35 BLS RX2+ 3 34 AESOUT RX2- 4 33 VDD33 RX3+ 5 32 TX+ RX3- 6 31 TX- DIX4192 RX4+ 7 30 DGND2 RX4- 8 29 GPO4 VCC 9 28 GPO3 AGND 10 27 GPO2 LOCK 11 26 GPO1 RXCKO 12 25 MCLK RST INT CDOUT/SDA CDIN/A1 CCLK/SCL CPM CS/A0 VDD18 NC DGND1 NC RXCKI 13 14 15 16 17 18 19 20 21 22 23 24 NC = No Connection PIN DESCRIPTIONS 8 NAME PIN NUMBER I/O RX1+ 1 Input DESCRIPTION Line receiver 1, noninverting input RX1– 2 Input Line receiver 1, inverting input RX2+ 3 Input Line receiver 2, noninverting input RX2– 4 Input Line receiver 2, inverting input RX3+ 5 Input Line receiver 3, noninverting input RX3– 6 Input Line receiver 3, inverting input RX4+ 7 Input Line receiver 4, noninverting input RX4– 8 Input Line receiver 4, inverting input VCC 9 Power DIR comparator and PLL power supply, +3.3V nominal AGND 10 Ground DIR comparator and PLL power-supply ground LOCK 11 Output DIR PLL lock flag (active low) RXCKO 12 Output DIR recovered master clock (tri-state output) RXCKI 13 Input NC 14, 15, 41 — DGND1 16 Ground Digital core ground VDD18 17 Power Digital core supply, +1.8V nominal CPM 18 Input Control port mode, 0 = SPI mode, 1 = I2C mode CS or A0 19 Input Chip select (active low) for SPI mode or programmable slave address for I2C mode CCLK or SCL 20 Input Serial data clock for SPI mode or I2C mode CDIN or A1 21 Input SPI port serial data input or programmable slave address for I2C mode CDOUT or SDA 22 I/O DIR reference clock No internal signal connection, internally bonded to ESD pad SPI port serial data output (tri-state output) or serial data I/O for I2C mode Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PIN DESCRIPTIONS (continued) NAME PIN NUMBER I/O INT 23 Output DESCRIPTION RST 24 Input Reset (active low) MCLK 25 Input Master clock GPO1 26 Output General-purpose output 1 GPO2 27 Output General-purpose output 2 GPO3 28 Output General-purpose output 3 GPO4 29 Output General-purpose output 4 DGND2 30 Ground DIR line receiver bias and DIT line driver digital ground TX– 31 Output DIT line driver inverting output TX+ 32 Output DIT line driver noninverting output VDD33 33 Power DIR line receiver bias and DIT line driver supply, +3.3V nominal AESOUT 34 Output DIT buffered AES3-encoded data BLS 35 I/O SYNC 36 Output BCKA 37 I/O Audio serial Port A bit clock LRCKA 38 I/O Audio serial Port A Left/Right clock SDINA 39 Input SDOUTA 40 Output Audio serial Port A data output VIO 42 Power Logic I/O supply, +1.65V to +3.6V DGND3 43 Ground Logic I/O ground BGND 44 Ground Substrate ground, connect to AGND (pin 10) SDOUTB 45 Output Audio serial Port B data output SDINB 46 Input LRCKB 47 I/O Audio serial Port B left/right clock BCKB 48 I/O Audio serial Port B bit clock Interrupt flag (open-drain, active low) DIT block start clock DIT internal sync clock Audio serial Port A data input Audio serial Port B data input Submit Documentation Feedback 9 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW The DIX4192 is an integrated digital audio interface receiver and transmitter (DIR and DIT). Two audio serial ports, Port A and Port B, support input and output interfacing to external data converters, signal processors, and logic devices. On-chip routing logic provides for flexible interconnection between the four functional blocks. The audio serial ports and DIT may be operated at sampling rates up to 216kHz. The DIR is specified for a PLL lock range that includes sampling rates from 20kHz to 216kHz. All function blocks support audio data word lengths up to 24 bits. The DIX4192 requires an external host processor or logic for configuration control. The DIX4192 includes a user-selectable serial host interface, which operates as either a 4-wire serial peripheral interface (SPI) port or a 2-wire Philips I2C bus interface. The SPI port operates at bit rates up to 40MHz. The I2C bus interface may be operated in standard or fast modes, supporting operation at 100kbps and 400kbps, respectively. The SPI and I2C interfaces provide access to internal control and status registers, as well as the buffers utilized for the DIR and DIT channel status and user data. The digital interface receiver (DIR) includes four differential input line receiver circuits, suitable for balanced or unbalanced cable interfaces. Interfacing to optical receiver modules and CMOS logic devices is also supported. The outputs of the line receivers are connected to a 1-of-4 data selector, referred to as the receiver input multiplexer, which is utilized to select one of the four line receiver outputs for processing by the DIR core. The outputs of the line receivers are also connected to a second data selector, the bypass multiplexer, which may be used to route input data streams to the DIT CMOS output buffer and differential line driver functions. This configuration provides a bypass signal path for AES3-encoded input data streams. The DIR core decodes the selected input stream data and separates the audio, channel status, user, validity, and parity data. Channel status and user data is stored in block-sized buffers, which may be accessed via the SPI or I2C serial host interface, or routed directly to the general-purpose output pins (GPO1 through GPO4). The validity and parity bits are processed to determine error status. The DIR core recovers a low jitter master clock, which may be utilized to generate word and bit clocks using on-chip or external logic circuitry. The digital interface transmitter (DIT) encodes digital audio input data into an AES3-formatted output data stream. Two DIT outputs are provided, including a differential line driver and a CMOS output buffer. Both the line driver and buffer include 1-of-2 input data selectors, which are utilized to choose either the output of the DIT AES3 encoder, or the output of the bypass multiplexer. The line driver output is suitable for balanced or unbalanced cable interfaces, while the CMOS output buffer supports interfacing to optical transmitter modules and external logic or line drivers. The DIT includes block-sized data buffers for both channel status and user data. These buffers are accessed via either the SPI or I2C host interface, or may be loaded directly from the DIR channel status and user data buffers. The DIX4192 includes four general-purpose digital outputs, or GPO pins. The GPO pins may be configured as simple logic outputs, which may be programmed to either a low or high state. Alternatively, the GPO pins may be connected to one of 13 internal logic nodes, allowing them to serve as functional, status, or interrupt outputs. The GPO pins provide added utility in applications where hardware access to selected internal logic signals may be necessary. 10 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) Figure 4 shows a simplified functional block diagram for the DIX4192. Additional details for each function block will be covered in respective sections of this datasheet. DIX4192 SDINA SDOUTA LRCKA Host Interface 2 (SPI or I C) and GeneralPurpose Outputs Audio Serial Port A BCKA SDINB SDOUTB LRCKB Audio Serial Port B Control and Status Registers BCKB RXCKO DIR C and U Data Buffers LOCK RX1+ RX1RX2+ Master Clock Distribution MCLK RXCKI From RXCKO PORT A PORT B DIR DIT PORT_B_IN PORT_A_IN Digital Interface Transmitter (DIT) DIR_OUT RX3RX4+ AESOUT DIT C and U Data Buffers Digital Interface Receiver (DIR) RX2RX3+ RX4TX+ TX- CPM CS or A0 CCLK or SCL CDIN or A1 CDOUT or SDA INT RST GPO1 GPO2 GPO3 GPO4 BLS SYNC Power Internally Tied to Substrate VDD18 DGND1 VDD33 DGND2 VIO DGND3 VCC AGND BGND Figure 4. Functional Block Diagram RESET OPERATION The DIX4192 includes an asynchronous active low reset input, RST (pin 24), which may be used to initialize the internal logic at any time. The reset sequence forces all registers and buffers to their default settings. The reset low pulse width must be a minimum of 500ns in length. The user should not attempt a write or read operation using either the SPI or I2C port for at least 500µs after the rising edge of RST. See Figure 5 for the reset timing sequence of the DIX4192. In addition to reset input, the RESET bit in control register 0x01 may be used to force an internal reset, whereby all registers and buffers are forced to their default settings. Refer to the Control Registers section for details regarding the RESET bit function. Upon reset initialization, all functional blocks of the DIX4192 default to the power-down state, with the exception of the SPI or I2C host interface and the corresponding control registers. The user may then program the DIX4192 to the desired configuration, and release the desired function blocks from the power-down state utilizing the corresponding bits in control register 0x01. Submit Documentation Feedback 11 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) Write or Read via 2 SPI or I C 1 RST 0 500ns (min) 500ms (min) Figure 5. Reset Sequence Timing MASTER AND REFERENCE CLOCKS The DIX4192 includes two clock inputs, MCLK (pin 25) and RXCKI (pin 13). The MCLK clock input is typically used as the master clock source for the audio serial ports and/or the DIT. The MCLK may also be utilized as the reference clock for the DIR. The RXCKI clock input is typically used for the DIR reference clock source, although it may also be used as the master or reference clock source for the audio serial ports. In addition to the MCLK and RXCKI clock sources, the DIR core recovers a master clock from the AES3-encoded input data stream. This clock is suitable for use as a master or system clock source in many applications. The recovered master clock output, RXCKO (pin 12), may be utilized as the master or reference clock source for the audio serial ports and/or the DIT, as well as external audio devices. The master clock frequency for the audio serial ports (Port A and Port B) depends on the Slave or Master mode configuration of the port. In Slave mode, the ports do not require a master clock because the left/right word and bit clocks are inputs, sourced from an external audio device serving as the serial bus timing master. In Master mode, the serial ports derive the left/right word and bit clock outputs from the selected master clock source, MCLK, RXCKI, or RXCKO. The left/right word clock rate is derived from the selected master clock source using one of four clock divider settings (divide by 128, 256, 384, or 512). Refer to the Audio Serial Port Operation section for additional details. The DIT always requires a master clock source, which may be either the MCLK input, or the DIR recovered clock output, RXCKO. Like the audio serial ports, the DIT output frame rate is derived from the selected master clock using one of four clock divider settings (divide-by-128, -256, -384, or -512). Refer to the Digital Interface Transmitter (DIT) Operation section for additional details. The DIR reference clock may be any frequency that meets the PLL1 setup requirements, described in the Control Registers section. Typically, a common audio system clock rate, such as 11.2896MHz, 12.288MHz, 22.5792MHz, or 24.576MHz, may be used for this clock. It is recommended that the clock sources for MCLK and RXCKI input be generated by low-jitter crystal oscillators for optimal performance. In general, phase-locked loop (PLL) clock synthesizers should be avoided, unless they are designed and/or specified for low clock jitter. 12 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) AUDIO SERIAL PORT OPERATION The DIX4192 includes two audio serial ports, Port A and Port B. Both ports are 4-wire synchronous serial interfaces, supporting simultaneous input and output operation. Since each port has only one pair of left/right word and bit clocks, the input and output sampling rates are identical. A simplified block diagram is shown in Figure 6. The audio serial ports may be operated at sampling rates up to 216kHz, and support audio data word lengths up to 24 bits. Philips I2S, Left-Justified, and Right-Justified serial data formats are supported. Refer to Figure 7. The left/right word clock (LRCKA or LRCKB) and the bit clock (BCKA or BCKB) may be configured for either Master or Slave mode operation. In Master mode these clocks are outputs, derived from the selected master clock source using internal clock dividers. The master clock source may be 128, 256, 384, or 512 times the audio input/output sampling rate, with the clock divider being selected using control register bits for each port. In Slave mode the left/right word and bit clocks are inputs, and are sourced from an external audio device acting as the serial bus master. The LRCKA or LRCKB clocks operate at the input/output sampling rate, fS. The BCKA and BCKB clock rates are fixed at 64 times the left/right word clock rate in Master mode. For Slave mode, the minimum BCKA and BCKB clock rate is determined by the audio data word length multiplied by two, since there are two audio data channels per left/right word clock period. For example, if the audio data word length is 24 bits, the bit clock rate must be at least 48 times the left/right word clock rate, allowing one bit clock period for each data bit in the serial bit stream. Serial audio data is clocked into the port on the rising edge of the bit clock, while data is clocked out of the port on the falling edge of the bit clock. Refer to the Electrical Characteristics: Audio Serial Ports table for parametric information and Figure 1 for a timing diagram related to audio serial port operation. The audio serial ports are configured using control registers 0x03 through 0x06. Refer to the Control Registers section for descriptions of the control register bits. CLK[1:0] Master Clock Source MCLK M/S DIV[1:0] Master Mode Clock Generation RXCKI RXCKO SDINA (pin 39) or SDINB (pin 46) Audio Data Serial Input Internal Clocks Data Source LRCKA (pin 38) or LRCKB (pin 47) BCKA (pin 37) or BCKB (pin 48) Port A Port B DIR Serial Output SDOUTA (pin 40) or SDOUTB (pin 45) OUTS[1:0] MUTE FMT[1:0] Figure 6. Audio Serial Port Block Diagram Submit Documentation Feedback 13 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) Channel 1 (Left Channel) Channel 2 (Right Channel) LRCKA LRCKB BCKA BCKB Audio Data MSB LSB MSB LSB (a) Left-Justified Data Format LRCKA LRCKB BCKA BCKB Audio MSB Data LSB MSB LSB (b) Right-Justified Data Format LRCKA LRCKB BCKA BCKB Audio Data MSB LSB MSB LSB 2 (c) I S Data Format 1/fs Figure 7. Audio Data Formats OVERVIEW OF THE AES3 DIGITAL AUDIO INTERFACE PROTOCOL This section introduces the basics of digital audio interface protocols pertaining to the transmitter (DIT) and receiver (DIR) blocks of the DIX4192. Emphasis is placed upon defining the basic terminology and characteristics associated with the AES3-2003 standard protocol, the principles of which may also be applied to a number of consumer-interface variations, including S/PDIF, IEC-60958, and EIAJ CP-1201. It is assumed that the reader is familiar with the AES3 and S/PDIF interface formats. Additional information is available from the sources listed in the Reference Documents section. The AES3-2003 standard defines a technique for two-channel linear PCM data transmission over 110Ω shielded twisted-pair cable. The AES-3id document extends the AES3 interface to applications employing 75Ω coaxial cable connections. In addition, consumer transmission variants, such as those defined by the S/PDIF, IEC 60958, and CP-1201 standards, utilize the same encoding techniques but with different physical interfaces or transmission media. Channel status data definitions also vary between professional and consumer interface implementations. 14 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) For AES3 transmission, data is encoded into frames, with each frame containing two subframes of audio and status data, corresponding to audio Channels 1 and 2 (or Left and Right, respectively, for stereophonic audio). Figure 8 shows the AES3 frame and subframe formatting. Each subframe includes four bits for the preamble, up to 24 bits for audio and/or auxiliary data, one bit indicating data validity (V), one bit for channel status data (C), one bit for user data (U), and one bit for setting parity (P). The 4-bit preamble is used for synchronization and identification of blocks and subframes. The X and Y preamble codes are used to identify the start of the Channel 1 and Channel 2 subframes, as shown in Figure 8. However, the X preamble for the first subframe of every 192 frames is replaced by the Z preamble, which identifies the start of a new block of channel status and user data. Block Start Frame 191 X Channel 1 Y Frame 0 Channel 2 Z Channel 1 Y Frame 1 Channel 2 X Channel 1 Y Channel 2 One Sub Frame Bits: 0 3 4 Preamble 7 8 Audio or Aux Data 27 28 29 30 31 Audio Data MSB V U C P Validity Bit User Data Channel Status Data Parity Bit Figure 8. AES3 Frame and Subframe Encoding One block is comprised of 192 frames of data. This format translates to 192 bits each for channel status and user data for each channel. The 192 bits are organized into 24 data bytes, which are defined by the AES3-2003 and consumer standards documents. The AES18 standard defines recommended usage and formatting of the user data bits, while consumer applications may utilize the user data for other purposes. The DIX4192 also includes block-sized transmitter and receiver channel status and user data buffers, which have 24 bytes each for the channel status and user data assigned to audio Channels 1 and 2. Refer to the Channel Status and User Data Buffer Maps section for the organization of the buffered channel status and user data for the receiver and transmitter functions. The audio data for Channel 1 and Channel 2 may be up to 24 bits in length, and occupies bits 4 through 27 of the corresponding subframe. Bit 4 is the LSB while bit 27 is the MSB. If only 20 bits are required for audio data, then bits 8 through 27 are utilized for audio data, while bits 4 though 7 are utilized for auxiliary data bits. The validity (V) bit indicates whether or not the audio sample word being transmitted is suitable for digital-to-analog (D/A) conversion or further digital processing at the receiver end of the connection. If the validity bit is 0, then the audio sample is suitable for conversion or additional processing. If the validity bit is 1, then the audio sample is not suitable for conversion or additional processing. The parity (P) bit is set to either a 0 or 1, such that bits 4 through 31 carry an even number of ones and zeros for even parity. The DIT block in the DIX4192 automatically manages the parity bit, setting it to a 0 or 1 as needed. The DIR block checks the parity of bits 4 though 31 and generates a parity error if odd parity is detected. Submit Documentation Feedback 15 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) The binary non-return to zero (NRZ) formatted audio and status source data for bits 4 through 31 of each subframe are encoded utilizing a Biphase Mark format for transmission. This format allows for clock recovery at the receiver end, as well as making the interface insensitive to the polarity of the balanced cable connections. The preambles at the start of each subframe are encoded to intentionally violate the Biphase Mark formatting, making their detection by the receiver reliable, as well as avoiding the possibility of audio and status data imitating the preambles. Figure 9 shows the Biphase Mark and preamble encoding. Although the AES3 standard originally defined transmission for sampling rates up to 48kHz, the interface is capable of handling higher sampling rates, given that attention is paid to cable length and impedance matching. Equalization at the receiver may also be required, depending on the cable and matching factors. It is also possible to transmit and decode more than two channels of audio data utilizing the AES3 or related consumer interfaces. Special encoding and/or compression algorithms are utilized to support multiple channels, including the Dolby® AC-3, DTS, MPEG-1/2, and other data reduced audio formats. Clock (2x Source Bit Rate) Source Data Coding 1 (NRZ) 0 Insert Preamble Code Below AES3 Channel Coding 1 (Biphase Mark) 0 Preamble Z (Block Start) Preamble Coding Preceding state: Preamble: X Y Z Preceding state, from the Parity bit of the previous frame. 0 Channel coding: 11100010 11100100 11101000 1 Channel coding: 00011101 00011011 00010111 Description: Channel 1 subframe Channel 2 subframe Channel 1 subframe and block start Figure 9. Biphase Mark Encoding DIGITAL INTERFACE TRANSMITTER (DIT) OPERATION The DIT encodes a given two-channel or data-reduced audio input stream into an AES3-encoded output stream. In addition to the encoding function, the DIT includes differential line driver and CMOS-buffered output functions. The line driver is suitable for driving balanced or unbalanced line interfaces, while the CMOS-buffered output is designed to drive external logic or line drivers, as well as optical transmitter modules. Figure 10 illustrates the functional block diagram for the DIT. The input of the DIT receives the audio data for Channels 1 and 2 from one of three possible sources: Port A, Port B, or the DIR. By default, Port A is selected as the source. The DIT also requires a master clock source, which may be provided by either the MCLK input (pin 25) or RXCKO (the DIR recovered master clock output). A master clock divider is utilized to select the frame rate for the AES3-encoded output data. The TXDIV[1:0] bits in control register 0x07 are utilized to select divide by 128, 256, 384, or 512 operation. Channel status and user data for Channels 1 and 2 are input to the AES3 encoder via the corresponding Transmitter Access (TA) data buffers. The TA data buffers are in turn loaded from the User Access (UA) buffers, which are programmed via the SPI or I2C host interface, or loaded from the DIR Receiver Access (RA) data buffers. The source of the channel status and user data is selected utilizing the TXCUS[1:0] bits in control register 0x09. When the DIR is selected as the input source, the channel status and user data output from the DIT is delayed by one block in relation to the audio data. The validity (V) bit may be programmed using one of two sources. The VALSEL bit in control register 0x09 is utilized to select the validity data source for the DIT block. The default source is the VALID bit in control register 0x07, which is written via the SPI or I2C host interface. The validity bit may also be transferred from the AES3 decoder output of the DIR, where the V bit for the DIT subframes tracks the decoded DIR value frame by frame. 16 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) The Parity (P) bit will always be generated by the AES3 encoder internal parity generator logic, such that bits 4 through 31 of the AES3-encoded subframe are even parity. The AES3 encoder output is connected to the output line driver and CMOS buffer source multiplexers. As shown in Figure 10, the source multiplexers allow the line driver or buffer to be driven by the AES3-encoded data from the DIT, or by the bypass multiplexer, which is associated with the outputs of the four differential input line receivers preceding the DIR core. The bypass multiplexer allows for one of the four line receiver outputs to be routed to the line driver or buffer output, thereby providing a bypass mode of operation. Both the line driver and CMOS output buffer include output disables, set by the TXOFF and AESOFF bits in control register 0x08. When the outputs are disabled, they are forced to a low logic state. The AES3 encoder includes an output mute function that sets all bits for both the Channel 1 and 2 audio and auxiliary data to zero. The preamble, V, U, and C bits are unaffected, while the P bit is recalculated. The mute function is controlled using the TXMUTE bit in control register 0x08. TXCLK Master Clock Source TXDIV[1:0] MCLK AESMUX RXCKO AESOFF AESOUT (pin 34) TXIS[1:0] Data Source From Receiver Access (RA) Buffer 2 To/From SPI or I C Host Interface From Receiver Access (RA) Buffer 2 To/From SPI or I C Host Interface Port A Port B DIR LDMUX TXOFF User Access (UA) Buffers Transmitter Access (TA) Buffers Channel Status Channel Status User Data User Data TX+ (pin 32) AES3 Encoder TX- (pin 31) From Bypass Multiplexer Output BLS (pin 35) TXCUS[1:0] TXBTD SYNC (pin 36) TXMUTE BLSM Figure 10. Digital Interface Transmitter (DIT) Functional Block Diagram The AES3 encoder includes a block start input/output pin, BLS (pin 35). The BLS pin may be programmed as an input or output. The input/output state of the BLS pin is programmed using the BLSM bit in control register 0x07. By default, the BLS pin is configured as an input. As an input, the BLS pin may be utilized to force a block start condition, whereby the start of a new block of channel status and user data is initiated by generating a Z preamble for the next frame of data. The BLS input must be synchronized with the DIT internal SYNC clock. This clock is output on SYNC (pin 36). The SYNC clock rising edge is aligned with the start of each frame for the AES3-encoded data output by the DIT. Figure 11 illustrates the format required for an external block start signal, as well as indicating the format when the BLS pin is configured as an output. When the BLS pin is an output, the DIT generates the block start signal based upon the internal SYNC clock. For details regarding DIT control and status registers, as well as channel status and user data buffers, refer to the Control Registers and Channel Status and User Data Buffer Maps sections. Submit Documentation Feedback 17 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) Block Start (Frame 0 starts here) SYNC BLS (input) BLS (output) Figure 11. DIT Block Start Timing DIGITAL INTERFACE RECEIVER (DIR) OPERATION The DIR performs AES3 decoding and clock recovery and provides the differential line receiver functions. The lock range of the DIR includes frame/sampling rates from 20kHz to 216kHz. Figure 12 shows the functional block diagram for the DIR. Four differential line receivers are utilized for signal conditioning the encoded input data streams. The receivers can be externally configured for either balanced or unbalanced cable interfaces, as well as interfacing with CMOS logic level inputs from optical receivers or external logic circuitry. See Figure 13 for a simplified schematic for the line receiver. External connections are discussed in the Receiver Input Interfacing section. 2 To SPI or I C Host Interface Reference Clock Source MCLK To DIT RXCLK RX1+ (pin 1) RX1- (pin 2) RXMUX[1:0] User Data Channel Status PLL1 RXCKI AES3 Decoder To DIT User Data Channel Status RX2+ (pin 3) RX2- (pin 4) RX3+ (pin 5) RX3- (pin 6) Pulse Generator RX4+ (pin 7) RX4- (pin 8) BYPMUX[1:0] LOCK (pin 11) To DIT Buffer and Line Driver PLL2 128fS 256fS 512fS Clock Divider Divide by 1, 2, 4, or 8 RXCKO (pin 12) User Access (UA) Buffers Data Stream De-Mux Ch.1 (Left) Audio RXCKOF[1:0] Receiver Access (RA) Buffers Error and Status Outputs Ch.2 (Right) Audio Receiver Sync Generator RCV_SYNC RXCKO Figure 12. Digital Interface Receiver (DIR) Functional Block Diagram 18 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) VDD33 24kW 24kW 3kW RX+ To Receiver Input and Bypass Multiplexers RX3kW 24kW 24kW DGND2 Figure 13. Differential Line Receiver Circuit The outputs of the four line receivers are connected to two 1-of-4 data selectors: the receiver input multiplexer and the bypass multiplexer. The input multiplexer selects one of the four line receiver outputs as the source for the AES3-encoded data stream to be processed by the DIR core. The bypass multiplexer is utilized to route a line receiver output to either the DIT line driver or CMOS-buffered outputs, thereby bypassing all other internal circuitry. The bypass function is useful for simple signal distribution and routing applications. The DIR requires a reference clock, supplied by an external source applied at either the RXCKI (pin 13) or MCLK (pin 25) clock inputs. PLL1 multiplies the reference clock to a higher rate, which is utilized as the oversampling clock for the AES3 decoder. The decoder samples the AES3-encoded input stream in order to extract all of the audio and status data. The decoded data stream is sent on to a de-multiplexer, where audio and status data are separated for further processing and buffering. The pulse generator circuitry samples the encoded input data stream and generates a clock that is 16 times the frame/sampling rate (or fS). The 16fS clock is then processed by PLL2, which further multiplies the clock rate and provides low-pass filtering for jitter attenuation. The available PLL2 output clock rates include 512fS, 256fS, and 128fS. The maximum available PLL2 output clock rate for a given input sampling rate is estimated by internal logic and made available for readback via status register 0x13. The output of PLL2 may be divided by a factor of two, four, or eight, or simply passed through to the recovered master clock output, RXCKO (pin 12). The RXCKO clock may also be routed internally to other function blocks, where it may be further divided to create left/right word and bit clocks. The RXCKO output may be disabled and forced to a high-impedance state by means of a control register bit, allowing other tri-state buffered clocks to be tied to the same external circuit node, if needed. By default, the RXCKO output (pin 12) is disabled and forced to a high-impedance state. Figure 14 illustrates the frequency response of PLL2. Jitter attenuation starts at approximately 50kHz. Peaking is nominally 1dB, which is within the 2dB maximum allowed by the AES3 standard. The receiver jitter tolerance plot for the DIR is illustrated in Figure 15, along with the required AES3 jitter tolerance template. The DIR jitter tolerance satisfies the AES3 requirements, as well as the requirements set forth by the IEC60958-3 specification. Figure 15 was captured using a full-scale 24-bit, two-channel, AES3-encoded input stream with a 48kHz frame rate. The decoded audio data, along with the internally-generated sync clocks, may be routed to other function blocks, including Port A, Port B, and/or the DIT. The decoded channel status and user data are buffered in the corresponding Receiver Access (RA) data buffers, then transferred to the corresponding User Access (UA) data buffers, where it may be read back through either the SPI or I2C serial host interface. The contents of the RA buffers may also be transferred to the DIT UA data buffers; this transfer is illustrated in Figure 10. The channel status and user data bits may also be output serially through the general-purpose output pins, GPO[4:1]. Figure 16 illustrates the output format for the GPO pins when used for this purpose, along with the DIR block start (BLS) and frame synchronization (SYNC) clocks. The rising edges of the DIR SYNC clock output are aligned with the start of each frame for the received AES3 data. Submit Documentation Feedback 19 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) The DIR includes a dedicated, active low AES3 decoder and PLL2 lock output, named LOCK (pin 11). The lock output is active only when both the AES3 decoder and PLL2 indicate a lock condition. Additional DIR status flags may be output at the general-purpose output (GPO) pins, or accessed through the status registers via the SPI or I2C host interface. Refer to the General-Purpose Digital Outputs and Control Registers sections for additional information regarding the DIR status functions. 2 0 Jitter Attenuation (dB) -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 10 0 10 1 10 2 10 3 10 4 10 5 10 6 Jitter Frequency (Hz) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 5 2 Input Jitter Amplitude 1 Output Jitter Amplitude 500m 200m Peak Jitter (UI) THD+N Ratio (dB) Figure 14. DIR Jitter Attenuation Characteristics 100m 50m 20m 10m 5m THD+N 20 2m 100 1k 1m 100k 10k Sinusoidal Jitter Frequency (Hz) Figure 15. DIR Jitter Tolerance Plot Block Start (Frame 0 Starts Here) BLS (output) SYNC (output) C or U data (output) Ch. 1 Ch. 2 Bit 0 Ch. 1 Ch. 2 Ch. 1 Bit 1 Ch. 2 Bit 2 Ch. 1 Ch. 2 Bit 4 ¼ Figure 16. DIR Channel Status and User Data Serial Output Format Via the GPO Pins 20 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) GENERAL-PURPOSE DIGITAL OUTPUTS The DIX4192 includes four general-purpose digital outputs, GPO1 through GPO4 (pins 26 through 29, respectively). A GPO pin may be programmed to a static high or low state. Alternatively, a GPO pin may be connected to one of 13 internal logic nodes, allowing the GPO pin to inherit the function of the selected signal. Control registers 0x1B through 0x1E are utilized to select the function of the GPO pins. For details regarding GPO output configuration, refer to the Control Registers section. Table 1 summarizes the available output options for the GPO pins. Table 1. General-Purpose Output Pin Configurations GPOn3 GPOn2 GPOn1 GPOn0 GPOn FUNCTION 0 0 0 0 GPOn is forced low (default) 0 0 0 1 GPOn is forced high 0 0 1 0 Reserved 0 0 1 1 DIT interrupt flag; active low 0 1 0 0 DIR interrupt flag; active low 0 1 0 1 DIR 50/15µs emphasis flag; active low 0 1 1 0 DIR non-audio data flag; active high 0 1 1 1 DIR non-valid data flag; active high 1 0 0 0 DIR channel status data serial output 1 0 0 1 DIR user data serial output 1 0 1 0 DIR block start clock output 1 0 1 1 DIR COPY bit output (0 = copyright asserted, 1 = copyright not asserted) 1 1 0 0 DIR L (or origination) bit output (0 = 1st generation or higher, 1 = original) 1 1 0 1 DIR Parity error flag; active high 1 1 1 0 DIR internal sync clock output; may be used as the data clock for the channel status and user data serial outputs. 1 1 1 1 DIT internal sync clock HOST INTERFACE OPERATION: SERIAL PERIPHERAL INTERFACE (SPI) MODE The DIX4192 supports a 4-wire SPI port when the CPM input (pin 18) is forced low or tied to ground. The SPI port supports high-speed serial data transfers up to 40Mbps. Register and data buffer write and read operations are supported. The CS input (pin 19) serves as the active low chip select for the SPI port. The CS input must be forced low in order to write or read registers and data buffers. When CS is forced high, the data at the CDIN input (pin 21) is ignored, and the CDOUT output (pin 22) is forced to a high-impedance state. The CDIN input serves as the serial data input for the port; the CDOUT output serves as the serial data output. The CCLK input (pin 20) serves as the serial data clock for both the input and output data. Data is latched at the CDIN input on the rising edge of CCLK, while data is clocked out of the CDOUT output on the falling edge of CCLK. Figure 17 illustrates the SPI port protocol. Byte 0 is referred to as the command byte, where the most significant bit (or MSB) is the read/write bit. For the R/W bit, a 0 indicates a write operation, while a 1 indicates a read operation. The remaining seven bits of the command byte are utilized for the register address targeted by the write or read operation. Byte 1 is a don’t care byte, and may be set to all zeroes. This byte is included in order to retain protocol compatibility with earlier Texas Instruments digital audio interface and sample rate converter products, including the DIT4096, DIT4192, the SRC418x series devices, and the SRC419x series devices. Submit Documentation Feedback 21 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 The SPI port supports write and read operations for multiple sequential register addresses through the implementation of an auto-increment mode. As shown in Figure 17, the auto-increment mode is invoked by simply holding the CS input low for multiple data bytes. The register address is automatically incremented after each data byte transferred, starting with the address specified by the command byte. Refer to the Electrical Characteristics: SPI Interface table and Figure 2 for specifications and a timing diagram that highlight the key parameters for SPI interface operation. Set CS = 1 here to write/read one register location. Hold CS = 0 to enable auto-increment mode. CS Header CDIN Byte 0 Register Data Byte 1 Byte 2 Byte 3 Byte N Register Data CDOUT Hi Z Hi Z Data for A[6:0] Data for A[6:0]+1 Data for A[2:0]+N CCLK Byte Definition Byte 0: MSB LSB R/W A6 A5 A4 A3 A2 A1 A0 Register Address Set to 0 for Write; Set to 1 for Read. Byte 1: Don’t Care Byte 2 through Byte N: Register Data Figure 17. Serial Peripheral Interface (SPI) Protocol for the DIX4192 HOST INTERFACE OPERATION: PHILIPS I2C MODE The DIX4192 supports a 2-wire Philips I2C bus interface when CPM (pin 18) is forced high or pulled up to the VIO supply rail. The DIX4192 functions as a Slave-only device on the bus. Standard and Fast modes of operation are supported. Standard mode supports data rates up to 100kbps, while Fast mode supports data rates up to 400kbps. Fast mode is downward compatible with Standard mode, and these modes are sometimes referred to as Fast/Standard, or F/S mode. The I2C Bus Specification (Version 2.1, January 2000), available from Philips Semiconductor, provides the details for the bus protocol and implementation. It is assumed that the reader is familiar with this specification. Refer to the Electrical Characteristics: I2C Standard and Fast Modes table and Figure 3 for specifications and a timing diagram that highlight the key parameters for I2C interface operation. When the I2C mode is invoked, pin 20 becomes SCL (which serves as the bus clock) and pin 22 becomes SDA (which carries the bi-directional serial data for the bus). Pins 19 and 21 become A0 and A1, respectively, and function as the hardware configurable portion of the 7-bit slave address. The DIX4192 utilizes a 7-bit Slave address; see Figure 18(a). Bits A2 through A6 are fixed and bits A0 and A1 are hardware programmable using pins 19 and 21, respectively. The programmable bits allow for up to four DIX4192 devices to be connected to the same bus. The slave address is followed by the Register Address Byte, which points to a specific register or data buffer location in the DIX4192 register map. The register address byte is comprised of seven bits for the address, and one bit for enabling or disabling auto-increment operation; see Figure 18(b). Auto-increment mode allows multiple sequential register locations to be written to or read back in a single operation, and is especially useful for block write and read operations. Figure 19 illustrates the protocol for Standard and Fast mode Write operations. When writing a single register address, or multiple non-sequential register addresses, the single register write operation of Figure 19(a) may be used one or more times. When writing multiple sequential register addresses, the auto-increment mode of Figure 19(b) improves efficiency. The register address is automatically incremented by one for each successive byte of data transferred. 22 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Figure 20 illustrates the protocol for Standard and Fast mode Read operations. The current address read operation of Figure 20(a) assumes the value of the register address from the previously executed write or read operation, and is useful for polling a register address for status changes. Figure 20(b) and Figure 20(c) illustrate read operations for one or more random register addresses, with or without auto-increment mode enabled. First Byte After the START/RESTART Condition Slave Address LSB MSB A6 A5 A4 A3 A2 A1 A0 1 1 1 0 0 A1 A0 R/W Set by Pin 19 Set by Pin 21 (a) DIX4192 Slave Address MSB LSB INC A6 Auto-Increment 0 = Disabled 1 = Enabled A5 A4 A3 A2 A1 A0 (b) Register Address Byte Figure 18. DIX4192 Slave Address and Register Address Byte Definitions Byte 3 Register Data Byte 2 Register Address Byte with INC = 0 Byte 1 Slave Address with R/W = 0 S A A A P (a) Writing a Single Register Byte 2 Register Address Byte with INC = 1 Byte 1 Slave Address with R/W = 0 S A A Byte N Register Data for Address + N Byte 4 Register Data for Address + 1 Byte 3 Register Data A A A P (b) Writing Multiple Sequential Registers Using Auto-Increment Operation Legend S = START Condition A = Acknowledge P = STOP Condition Transfer from Master to Slave Transfer from Slave to Master Figure 19. Fast/Standard Mode Write Operations Submit Documentation Feedback 23 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Byte 2 Register Address Byte with INC = 0 Byte 1 Slave Address with R/W = 1 S A A P (a) Current Address Read, Assumes the Register Address of the Previous Byte 1 Slave Address with R/W = 0 S Byte 2 Register Address Byte with INC = 0 A Byte 3 Slave Address with R/W = 1 Byte 4 Register Data A A R A P (b) Random Read Operation, Auto-Increment Disabled S Byte 3 Slave Address with R/W = 1 Byte 2 Register Address Byte with INC = 1 Byte 1 Slave Address with R/W = 0 A A R Byte N Register Data for Address + N Byte 4 Register Data A A A P (c) Random Read Operation, Auto-Increment Enabled Legend S = START Condition A = Acknowledge A = Not Acknowledge R = Repeated START P = STOP Condition Transfer from Master to Slave Transfer from Slave to Master Figure 20. Fast/Standard Mode Read Operations INTERRUPT OUTPUT The DIX4192 includes multiple internal status bits, many of which may be set to trigger an interrupt signal. The interrupt signal is output at INT (pin 23), which is an active low, open-drain output. The INT pin requires a pull-up resistor to the VIO supply rail. The value of the pull-up is not critical, but a 10kΩ device should be sufficient for most applications. Figure 21 shows the interrupt output pin connection. The open-drain output allows interrupt pins from multiple DIX4192 devices to be connected in a wired OR configuration. MCU, DSP, or Logic DIX4192 VIO Interrupt Logic 10kW INT 23 Interrupt Input To the INT outputs for additional DIX4192 devices Figure 21. Interrupt Output Pin Connections 24 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 APPLICATIONS INFORMATION Typical application diagrams and power-supply connections are presented in this section to aid the customer in hardware designs employing the DIX4192 device. Figure 22 illustrates typical application connections for the DIX4192 using an SPI host interface. The SPI host will typically be a microcontroller, digital signal processor, or a programmable logic device. In addition to providing the SPI bus master, the host may be utilized to process interrupt and flag outputs from the DIX4192. The audio serial ports are connected to external digital audio devices, which may include data converters, digital signal processors, digital audio interface receivers/transmitters, or other logic devices. The DIR inputs and DIT outputs are connected to line, optical, or logic interfaces (see the Receiver Input Interfacing and Transmitter Output Interfacing sections). Master and DIR reference clock sources are also shown. Figure 23 illustrates typical application connections for the DIX4192 using an I2C bus interface. The I2C bus master will typically be a microcontroller, digital signal processor, or a programmable logic device. In addition to providing the I2C bus master, the host may be used to process interrupt and flag outputs from the DIX4192. Pull-up resistors are connected from SCL (pin 20) and SDA (pin 22) to the VIO supply rail. These resistors are required for the open drain outputs of the I2C interface. All other connections to the DIX4192 are the same as the SPI host case discussed previously. Figure 24 illustrates the recommended power-supply connections and bypassing for the DIX4192. In this case, it is assumed that the VIO, VDD33, and VCC supplies are powered from the same +3.3V power source. The VDD18 core supply is powered from a separate supply, or derived from the +3.3V supply using a linear voltage regulator, as illustrated with the optional regulator circuitry of Figure 24. The 0.1µF bypass capacitors are surface-mount X7R ceramic, and should be located as close to the device as possible. These capacitors should be connected directly between the supply and corresponding ground pins of the DIX4192. The ground pin is then connected directly to the ground plane of the printed circuit board (PCB). The larger value capacitors, shown connected in parallel to the 0.1µF capacitors, are recommended. At a minimum, there should at least be footprints on the PCB for installation of these larger capacitors, so that experiments can be run with and without the capacitors installed, in order to determine the effect on the measured performance of the DIX4192. The larger value capacitors can be surface-mount X7R multilayer ceramic or tantalum chip. The substrate ground, BGND (pin 44), should be connected by a PCB trace to AGND (pin 10). The AGND pin is then connected directly to the ground plane. This connection helps to reduce noise in the DIR section of the device, aiding the overall jitter and noise tolerance for the receiver. A series resistor is shown between the +3.3V supply and VCC (pin 9) connection. This resistor combines with the bypass capacitors to create a simple RC filter to remove higher frequency components from the VCC supply. The series resistor should be a metal film type for best filtering characteristics. As a substitute for the resistor, a ferrite bead can be utilized, although it may have to be physically large in order to contribute to the filtering. Submit Documentation Feedback 25 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 APPLICATIONS INFORMATION (continued) DIX4192IPFB 37 38 39 40 41 42 43 44 45 46 47 48 Audio I/O Device Audio I/O Device 1 2 3 4 5 6 7 8 9 10 11 12 From Digital Inputs (Line, Optical, Logic) DIR Recovered Clock SYNC BLS AESOUT VDD33 TX+ TXDGND2 GPO4 GPO3 GPO2 GPO1 MCLK BCKA LRCKA SDINA SDOUTA NC VIO DGND3 BGND SDOUTB SDINB LRCKB BCKB RX1+ RX1RX2+ RX2RX3+ RX3RX4+ RX4VCC AGND LOCK RXCKO RST INT CDOUT CDIN CCLK CS CPM VDD18 DGND1 NC NC RXCKI 36 35 34 33 32 31 30 29 28 27 26 25 To Host or External Logic To Digital Outputs (Line, Optical, Logic) To Host or External Logic 24 23 22 21 20 19 18 17 16 15 14 13 SPI Host Controller Master Clock 10kW VIO DIR Ref Clock Figure 22. Typical Application Diagram Using SPI Host Interface (See Figure 24 for Power-Supply Connections.) DIX4192IPFB Audio I/O Device Audio I/O Device From Digital Inputs (Line, Optical, Logic) DIR Recovered Clock 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 BCKA LRCKA SDINA SDOUTA NC VIO DGND3 BGND SDOUTB SDINB LRCKB BCKB RX1+ RX1RX2+ RX2RX3+ RX3RX4+ RX4VCC AGND LOCK RXCKO SYNC BLS AESOUT VDD33 TX+ TXDGND2 GPO4 GPO3 GPO2 GPO1 MCLK RST INT SDA A1 SCL A0 CPM VDD18 DGND1 NC NC RXCKI 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 To Host or External Logic To Digital Outputs (Line, Optical, Logic) To Host or External Logic 2 IC Host Controller Tie LO or HI 10kW Master Clock 2.7kW VIO DIR Ref Clock Figure 23. Typical Application Diagram Using I2C Host Interface (See Figure 24 for Power-Supply Connections.) 26 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 APPLICATIONS INFORMATION (continued) +3.3V 10mF + 44 R 0.1mF 43 42 DIX4192IPFB 33 9 10mF + 0.1mF 0.1mF 10 + 10mF 30 Connect pin 44 to pin 10. Pin 10 is then connected to the ground plane. +3.3V TPS79318DBVR 1 IN 3 EN 0.1mF GND 2 OUT NR 16 17 0.1mF 5 4 C 0.01mF 2.2mF + +1.8V Optional Regulator Circuit R may be set from 2W to 10W, or replaced by a ferrite bead. C may be set to 10mF, or not installed when using the optional regulator circuit. Figure 24. Recommended Power-Supply Connections DIGITAL AUDIO TRANSFORMER VENDORS Transformers are shown in this data sheet for both receiver and transmitter balanced and unbalanced line interface implementations. For the Texas Instruments Pro Audio evaluation modules, transformers from Scientific Conversion are utilized. In addition to Scientific Conversion, there are other vendors that offer transformer products for digital audio interface applications. Please refer to the following manufacturer web sites for details regarding their products and services. Other transformer vendors may also be available by searching catalog and/or Internet resources. • Scientific Conversion: http://scientificonversion.com • Schott Corporation: http://schottcorp.com • Pulse Engineering: http://pulseeng.com Submit Documentation Feedback 27 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 APPLICATIONS INFORMATION (continued) RECEIVER INPUT INTERFACING This section details the recommended interfaces for the DIX4192 line receiver inputs. Balanced and unbalanced line interfaces, in addition to optical receiver and external logic interfacing, are discussed. For professional digital audio interfaces, 110Ω balanced line interfaces are either required or preferred. Transformer coupling is commonly employed to provide isolation and to improve common-mode noise rejection. Figure 25 shows the recommended transformer-coupled balanced line receiver interface for the DIX4192. The transformer is specified for a 1:1 turn ratio, and should exhibit low inter-winding capacitance for best performance. Due to the DC bias on the line receiver inputs, 0.1µF capacitors are utilized for AC-coupling the transformer to the line receiver inputs. On the line side of the transformer, an optional 0.1µF capacitor is shown for cases where a DC bias may be applied at the transmitter side of the connection. The coupling capacitors should be surface-mount ceramic chip type with an X7R or C0G dielectric. C Digital Input 110W Balanced (1) 1:1 0.1mF To RX+ 3 1 110W XLR To RX- 2 0.1mF (1) Insert a 0.1mF capacitor when blocking common-mode DC voltage. Figure 25. Transformer-Coupled Balanced Input Interface Unbalanced 75Ω coaxial cable interfaces are commonly employed in consumer and broadcast audio applications. Designs with and without transformer line coupling may be utilized. Figure 26(a) shows the recommended 75Ω transformer-coupled line interface, which shares many similarities to the balanced design shown in Figure 25. Once again, the transformer provides isolation and improved noise rejection. Figure 26(b) shows the transformer-free interface, which is commonly used for S/PDIF consumer connections. C (1) 1:1 0.1mF To RX+ Digital Input 75W Unbalanced (RCA or BNC Connector) 75W To RX0.1mF (a) Transformer-Coupled Unbalanced Line Interface 0.1mF Digital Input 75W Unbalanced (RCA or BNC Connector) To RX+ 75W To RX0.1mF (b) Unbalanced Line Interface Without Transformer (1) Insert a 0.1mF capacitor when blocking common-mode DC components. Figure 26. Unbalanced Line Input Interfaces 28 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 APPLICATIONS INFORMATION (continued) Optical interfaces utilizing all-plastic fiber are commonly employed for consumer audio equipment where interconnections are less than 10m in length. Optical receiver modules utilized for a digital audio interface operate from either a single +3.3V or +5V supply and have a TTL-, CMOS-, or low-voltage CMOS-compatible logic output. Interfacing to +3.3V optical receivers is straightforward when the optical receiver supply is powered from the DIX4192 VDD33 power source, as shown in Figure 27. For the +5V optical receivers, the output high logic level may exceed the DIX4192 line receiver absolute maximum input voltage. A level translator is required, placed between the optical receiver output and the DIX4192 line receiver input. Figure 28 shows the recommended input circuit when interfacing a +5V optical receiver to the DIX4192 line receiver inputs. The Texas Instruments SN74LVC1G125 single buffer IC is operated from the same +3.3V supply used for DIX4192 VDD33 supply. This buffer includes a +5V tolerant digital input, and provides the logic level translation required for the interface. VDD33 All-Plastic (5 or 10 meters maximum) Optical (1) Receiver To RX+ To RX0.1mF (1) Toshiba TORX141 or equivalent. Figure 27. Interfacing to a +3.3V Optical Receiver Module SN74LVC1G125 or Equivalent +5V VDD33 5 All-Plastic (5 or 10 meters maximum) Optical (1) Receiver 2 4 3 To RX+ To RX- 1 0.1mF (1) Toshiba TORX173, TORX176, TORX179, or equivalent. Figure 28. Interfacing to a +5V Optical Receiver Module Submit Documentation Feedback 29 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 APPLICATIONS INFORMATION (continued) The DIX4192 line receivers may also be driven directly from external logic or line receiver devices with TTL or CMOS outputs. If the logic driving the line receiver is operated from +3.3V, then logic level translation will not be required. However, if the external logic is operated from a power-supply voltage that exceeds the maximum VDD33 supply voltage of the DIX4192, or operates from a supply voltage lower than +3.3V, then level translation is required. Figure 29 shows the recommended logic level translation methods, utilizing buffers and level translators available from Texas Instruments. SN74LVC1G125 or Equivalent VDD33 5 2 From +5V Logic (TTL or CMOS) 4 3 To RX+ To RX- 1 0.1mF SN74AVC1T45 or Equivalent +1.8V or +2.5V 1 3 From +1.8V or +2.5V CMOS Logic VDD33 5 6 4 To RX+ To RX- 2 0.1mF Figure 29. CMOS/TTL Input Logic Interface TRANSMITTER OUTPUT INTERFACING This section details the recommended interfaces for the DIX4192 transmitter line driver and CMOS-buffered outputs. Balanced and unbalanced line interfaces, in addition to optical transmitter and external logic interfacing, will be discussed. For professional digital audio interfaces, 110Ω balanced line interfaces are either required or preferred. Transformer coupling is commonly employed to provide isolation and to improve common-mode noise performance. Figure 30 shows the recommended transformer-coupled balanced line driver interface for the DIX4192. The transformer is specified for a 1:1 turn ratio, and should exhibit low inter-winding capacitance for best performance. To eliminate residual DC bias, a 0.1µF capacitor is utilized for AC-coupling the transformer to the line driver outputs. The coupling capacitor should be a surface-mount ceramic chip type with an X7R or C0G dielectric. 110W TX+ 1:1 3 1 TX- 2 0.1mF Digital Output 110W Balanced XLR Figure 30. Transformer-Coupled Balanced Output Interface Unbalanced 75Ω coaxial cable interfaces are commonly employed in consumer and broadcast audio applications. Designs with and without transformer line coupling may be utilized. Figure 31(a) illustrates the recommended 75Ω transformer-coupled line driver interface, which shares many similarities to the balanced design shown in Figure 30. Figure 31(b) illustrates the transformer-free line driver interface, which is commonly used for S/PDIF consumer connections. 30 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 APPLICATIONS INFORMATION (continued) 0.1mF 1:1 R1 TX+ Digital Output 75W Unbalanced (RCA or BNC connector) R2 (a) Transformer-Coupled Unbalanced Output 0.1mF R1 TX+ Digital Output 75W Unbalanced (RCA or BNC connector) R2 (b) Unbalanced Output Without Transformer R1 and R2 are selected to achieve the desired output voltage level while maintaining the required 75W transmitter output impedance. The TX+ output impedance is negligible. Figure 31. Unbalanced Line Output Interfaces Optical interfaces utilizing all-plastic fiber are commonly employed for consumer audio equipment where interconnections are less than 10m in length. Most optical transmitter modules utilized for a digital audio interface operate from a single +3.3V or +5V supply and have a TTL-compatible logic input. The CMOS-buffered transmitter output of the DIX4192, AESOUT (pin 34), is capable of driving the optical transmitter with VIO supply voltages down to +3.0V. If the VIO supply voltage is less than +3.0V, then level translation logic is required to drive the optical transmitter input. A good choice for this application is the Texas Instruments SN74AVC1T45 single bus transceiver. This device features two power-supply rails, one for the input side and one for the output side. For this application, the input side supply is powered from the VIO supply, while the output side is powered from a +3.3V supply. This configuration will boost the logic high level to a voltage suitable for driving the TTL-compatible input configuration. Figure 32 shows the recommended optical transmitter interface circuits. Optical (1) Transmitter AESOUT VIO 1 +3.3V 5 6 3 SN74AVC1T45 or Equivalent All-Plastic Fiber (5 or 10 meters maximum) If VIO < +3.0V. 4 2 (1) Toshiba TOTX141, TOTX173, TOTX176, TOTX179, or equivalent. Figure 32. Interfacing to an Optical Transmitter Module The AESOUT output may also be used to drive external logic or line driver devices directly. Figure 33 illustrates the recommended logic interface techniques, including connections with and without level translation. Figure 34 illustrates an external line driver interface utilizing the Texas Instruments SN75ALS191 dual differential line driver. If the VIO supply of the DIX4192 is set from +3.0V to +3.3V, no logic level translation will be required between the AESOUT output and the line driver input. If the VIO supply voltage is below this range, then the optional logic level translation logic of Figure 34 will be required. The SN75ALS191 dual line driver is especially useful in applications where simultaneous 75Ω and 110Ω line interfaces are required. Submit Documentation Feedback 31 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 APPLICATIONS INFORMATION (continued) Direct to external logic operating from the VIO supply. AESOUT +5V 5 2 4 3 To +5V Logic (VIO supply = +3.0V to +3.3V) 1 SN74AHCT1G125 or Equivalent Figure 33. CMOS/TTL Output Logic Interface +5V SN75ALS191 1 8 2 AESOUT 7 VIO +3.3V 1 5 6 3 6 If VIO < +3.0V. 3 4 5 SN74AVC1T45 or Equivalent To Balanced or Unbalanced Line Interface To Balanced or Unbalanced Line Interface 2 1 Figure 34. External Line Driver Interface REGISTER AND DATA BUFFER ORGANIZATION The DIX4192 organizes the on-chip registers and data buffers into four pages. The currently active page is chosen by programming the Page Selection Register to the desired page number. The Page Selection Register is available on every register page at address 0x7F, allowing easy movement between pages. Table 2 indicates the page selection corresponding to the Page Selection Register value. Table 2. Register Page Selection Page Selection Register Value (Hex) Selected Register Page 00 Page 0, control and status registers 01 Page 1, DIR channel status and user data buffers 02 Page 2, DIT channel status and user data buffers 03 Page 3, reserved Register Page 0 contains the control registers utilized to configure the various function blocks within the DIX4192. In addition, status registers are provided for flag and error conditions, with many of the status bits capable of generating an interrupt signal when enabled. See Table 3 for the control and status register map. Register Page 1 contains the digital interface receiver (or DIR) channel status and user data buffers. These buffers correspond to the data contained in the C and U bits of the previously received block of the AES3-encoded data stream. The contents of these buffers may be read through the SPI or I2C serial host interface and processed as needed by the host system. See Table 5 for the DIR channel status buffer map, and Table 6 for the DIR user data buffer map. 32 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register Page 2 contains the digital interface transmitter (or DIT) channel status and user data buffers. These buffers correspond to the data contained in the C and U bits of the transmitted AES3-encoded data stream. The contents of these buffers may be written through the SPI or I2C serial host interface to configure the C and U bits of the transmitted AES3 data stream. The buffers may also be read for verification by the host system. See Table 7 for the DIT channel status buffer map, and Table 8 for the DIT user data buffer map. Register Page 3 is reserved for factory test and verification purposes, and cannot be accessed without an unlock code. The unlock code remains private; the test modes disable normal operation of the device, and are not useful in customer applications. Submit Documentation Feedback 33 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 CONTROL REGISTERS See Table 3 for the control and status register map of the DIX4192. Register addresses 0x00 and 0x2D through 0x7E are reserved for factory or future use. All register addresses are expressed as hexadecimal numbers. The following pages provide detailed descriptions for each control and status register. Table 3. Control and Status Register Map (Register Page 0) ADDRESS (Hex) D7 (MSB) D6 D5 D4 D3 D2 D1 D0 REGISTER GROUP 01 RESET 0 PDALL PDPA PDPB PDTX PDRX 0 Power-down and reset 02 0 0 0 0 0 TX RX 0 Global interrupt status 03 0 AMUTE AOUTS1 AOUTS0 AM/S AFMT2 AFMT1 AFMT0 Port A control 04 0 0 0 0 ACLK1 ACLK0 ADIV1 ADIV0 Port A control 05 0 BMUTE BOUTS1 BOUTS0 BM/S BFMT2 BFMT1 BFMT0 Port B control 06 0 0 0 0 BCLK1 BCLK0 BDIV1 BDIV0 Port B control 07 TXCLK TXDIV1 TXDIV0 TXIS1 TXIS0 BLSM VALID BSSL Transmitter control 08 BYPMUX1 BYPMUX0 AESMUX LDMUX TXBTD AESOFF TXMUTE TXOFF Transmitter control 09 0 0 0 0 0 VALSEL TXCUS1 TXCUS0 Transmitter control 0A 0 0 0 0 0 0 TSLIP TBTI DIT status 0B 0 0 0 0 0 0 MTSLIP MTBTI DIT interrupt mask 0C 0 0 0 0 TSLIPM1 TSLIPM0 TBTIM1 TBTIM0 DIT interrupt mode 0D 0 0 0 RXBTD RXCLK 0 RXMUX1 RXMUX Receiver control 0E 0 0 0 LOL RXAMLL RXCKOD1 RXCKOD0 RXCKOE Receiver control 0F P3 P2 P1 P0 J5 J4 J3 J2 Receiver PLL configuration 34 10 J1 J0 D13 D12 D11 D10 D9 D8 Receiver PLL configuration 11 D7 D6 D5 D4 D3 D2 D1 D0 Receiver PLL configuration 12 0 0 0 0 0 0 DTS CD/LD IEC61937 Non-PCM audio detection 13 0 0 0 0 0 0 RXCKR1 RXCKR0 Receiver status 14 CSCRC PARITY VBIT BPERR QCHG UNLOCK QCRC RBTI Receiver status 15 0 0 0 0 0 0 0 OSLIP Receiver status 16 MCSCRC MPARITY MVBIT MBPERR MQCHG MUNLOCK MQCRC MRBTI Receiver interrupt mask 17 0 0 0 0 0 0 0 MOSLIP Receiver interrupt mask 18 QCHGM1 QCHGM0 UNLOCKM1 UNLOCKM0 QCRCM1 QCRCM0 RBTIM1 RBTIM0 Receiver interrupt mode Receiver interrupt mode 19 CSCRCM1 CSCRCM0 PARITYM1 PARITYM0 VBITM1 VBITM0 BPERRM1 BPERRM0 1A 0 0 0 0 0 0 OSLIPM1 OSLIPM0 Receiver interrupt mode 1B 0 0 0 0 GPO13 GPO12 GPO11 GPO10 General-purpose out (GPO1) 1C 0 0 0 0 GPO23 GPO22 GPO21 GPO20 General-purpose out (GPO2) 1D 0 0 0 0 GPO33 GPO32 GPO31 GPO30 General-purpose out (GPO3) 1E 0 0 0 0 GPO43 GPO42 GPO41 GPO40 General-purpose out (GPO4) 1F Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Audio CD Q-channel sub-code 20 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Audio CD Q-channel sub-code 21 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Audio CD Q-channel sub-code 22 Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Audio CD Q-channel sub-code 23 Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Audio CD Q-channel sub-code 24 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Audio CD Q-channel sub-code 25 Q48 Q49 Q50 Q51 Q52 Q53 Q54 Q55 Audio CD Q-channel sub-code 26 Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Audio CD Q-channel sub-code 27 Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Audio CD Q-channel sub-code 28 Q72 Q73 Q74 Q75 Q76 Q77 Q78 Q79 Audio CD Q-channel sub-code 29 PC15 PC14 PC13 PC12 PC11 PC10 PC09 PC08 PC burst preamble, high byte 2A PC07 PC06 PC05 PC04 PC03 PC02 PC01 PC00 PC burst preamble, low byte 2B PD15 PD14 PD13 PD12 PD11 PD10 PD09 PD08 PD burst preamble, high byte 2C PD07 PD06 PD05 PD04 PD03 PD02 PD01 PD00 PD burst preamble, low byte 7F 0 0 0 0 0 0 PAGE1 PAGE0 Page selection Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 01: Power-Down and Reset Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) RESET 0 PDALL PDPA PDPB PDTX PDRX 0 PDRX Power-Down for the Receiver Function Block This bit is utilized to power-down the DIR and associated functions. All receiver outputs are forced low. PDRX PDTX Receiver Power-Down Mode 0 Enabled (default) 1 Disabled; the Receiver function block will operate normally based upon the applicable control register settings. Power-Down for the Transmitter Function Block This bit is utilized to power-down the DIT and associated functions. All transmitter outputs are forced low. PDTX PDPB Transmitter Power-Down Mode 0 Enabled (default) 1 Disabled; the Transmitter function block will operate normally based upon the applicable control register settings. Power-Down for Serial Port B This bit is utilized to power-down the audio serial I/O Port B. All port outputs are forced low. PDPB PDPA Port B Power-Down Mode 0 Enabled (default) 1 Disabled; Port B will operate normally based upon the applicable control register settings. Power-Down for Serial Port A This bit is utilized to power-down the audio serial I/O Port A. All port outputs are forced low. PDPA PDALL Port A Power-Down Mode 0 Enabled (default) 1 Disabled; Port A will operate normally based upon the applicable control register settings. Power-Down for All Functions This bit is utilized to power-down all function blocks except the host interface port and the control and status registers. PDALL RESET All Function Power-Down Mode 0 Enabled (default) 1 Disabled; all function blocks will operate normally based upon the applicable control register settings. Software Reset This bit is used to force a reset initialization sequence, and is equivalent to forcing an external reset via the RST input (pin 24). RESET Reset Function 0 Disabled (default) 1 Enabled; all control registers will be reset to the default state. Register 02: Global Interrupt Status (Read-Only) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 0 TX RX 0 RX Receiver Function Block Interrupt Status (Active High) When set to 1, this bit indicates an active interrupt from the DIR function block. This bit is active high. The user should then read status registers 0x14 and 0x15 in order to determine which of the sources has generated an interrupt. TX Transmitter Function Block Interrupt Status (Active High) When set to 1, this bit indicates an active interrupt from the DIT function block. This bit is active high. The user should then read status register 0x0A in order to determine which of the sources has generated an interrupt. Submit Documentation Feedback 35 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 03: Port A Control Register 1 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 AMUTE AOUTS1 AOUTS0 AM/S AFMT2 AFMT1 AFMT0 AFMT[2:0] Port A Audio Data Format These bits are used to set the audio input and output data format for Port A. Refer to the Audio Serial Port Operation section for illustrations of the supported data formats. Refer to the Electrical Characteristics: Audio Serial Ports table and Figure 1 for an applicable timing diagram and parameters. AM/S AFMT2 AFMT1 AFMT0 0 0 0 Audio Data Format 24-Bit Left-Justified (default) 0 0 1 24-Bit Philips I2S 0 1 0 Unused 0 1 1 Unused 1 0 0 16-Bit Right-Justified 1 0 1 18-Bit Right-Justified 1 1 0 20-Bit Right-Justified 1 1 1 24-Bit Right-Justified Port A Slave/Master Mode This bit is used to set the audio clock mode for Port A to either Slave or Master. AM/S AOUTS[1:0] Slave/Master Mode 0 Slave mode; the LRCK and BCK clocks are inputs generated by an external digital audio source. (default) 1 Master mode; the LRCK and BCK clocks are outputs, derived from the Port A master clock source. Port A Output Data Source These bits are used to select the output data source for Port A. The data is output at SDOUTA (pin 40). AMUTE AOUTS1 AOUTS0 Output Data Source 0 0 Port A input, for data loop back. (default) 0 1 Port B input 1 0 DIR 1 1 Reserved Port A Output Mute This bit is used to mute the Port A audio data output. AMUTE Output Mute 0 Disabled; SDOUTA is driven by the output data source. (default) 1 Enabled; SDOUTA is forced low. Register 04: Port A Control Register 2 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 ACLK1 ACLK0 ADIV1 ADIV0 ADIV[1:0] Port A Master Clock Divider These bits are used to set the master clock divider for generating the LRCKA clock for Port A when configured for Master mode operation. BCKA is always set to 64 times the LRCKA clock rate in Master mode. 36 ADIV1 ADIV0 0 0 Master Mode Clock Divider Divide-by-128 (default) 0 1 Divide-by-256 1 0 Divide-by-384 1 1 Divide-by-512 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 ACLK[1:0] Port A Master Clock Source These bits are used to set the master clock source for Port A when configured for Master mode operation. ACLK1 ACLK0 0 0 Master Clock Source MCLK (default) 0 1 RXCKI 1 0 RXCKO 1 1 Reserved Register 05: Port B Control Register 1 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 BMUTE BOUTS1 BOUTS0 BM/S BFMT2 BFMT1 BFMT0 BFMT[2:0] Port B Audio Data Format These bits are used to set the audio input and output data format for Port B. Refer to the Audio Serial Port Operation section for illustrations of the supported data formats. Refer to the Electrical Characteristics: Audio Serial Ports table and Figure 1 for an applicable timing diagram and parameters. BM/S BFMT2 BFMT1 BFMT0 0 0 0 Audio Data Format 24-Bit Left-Justified (default) 0 0 1 24-Bit Philips I2S 0 1 0 Unused 0 1 1 Unused 1 0 0 16-Bit Right-Justified 1 0 1 18-Bit Right-Justified 1 1 0 20-Bit Right-Justified 1 1 1 24-Bit Right-Justified Port B Slave/Master Mode This bit is used to set the audio clock mode for Port B to either Slave or Master. BM/S BOUTS[1:0] Slave/Master Mode 0 Slave mode; the LRCK and BCK clocks are generated by an external source. (default) 1 Master mode; the LRCK and BCK clocks are derived from the Port A master clock source. Port B Output Source These bits are used to select the output data source for Port B. The data is output at SDOUTB (pin 45). BMUTE BOUTS1 BOUTS0 0 0 Output Data Source Port B input, for data loop back. (default) 0 1 Port A input 1 0 DIR 1 1 Reserved Port B Output Mute This bit is used to mute the Port B audio data output. BMUTE Output Mute 0 Disabled; SDOUTB is driven by the output data source. (default) 1 Enabled; SDOUTB is forced low. Submit Documentation Feedback 37 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 06: Port B Control Register 2 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 BCLK1 BCLK0 BDIV1 BDIV0 BDIV[1:0] Port B Master Mode Clock Divider These bits are used to set the master clock divider for generating the LRCKB clock for Port B when configured for Master mode operation. BCKB is always set to 64 times the LRCKB clock rate in Master mode. BCLK[1:0] BDIV1 BDIV0 0 0 Master Mode Clock Divider Divide-by-128 (default) 0 1 Divide-by-256 1 0 Divide-by-384 1 1 Divide-by-512 Port B Master Clock Source These bits are used to set the master clock source for Port B when configured for Master mode operation. BCLK1 BCLK0 0 0 Master Clock Source MCLK (default) 0 1 RXCKI 1 0 RXCKO 1 1 Reserved Register 07: Transmitter Control Register 1 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) TXCLK TXDIV1 TXDIV0 TXIS1 TXIS0 BLSM VALID BSSL BSSL Block Start or Asynchronous Data Slip Interrupt Trigger Selection This bit is used to select the trigger source for the Transmitter TSLIP status and interrupt bit. BSSL VALID TSLIP Interrupt Trigger Source 0 Data slip condition (default) 1 Block start condition Validity (V) Data Bit This bit may be used to set the validity (or V) data bit in the AES3-encoded output. Refer to the VALSEL bit in control register 0x09 for V-bit source selection. VALID BLSM Transmitted Validity (V) Bit Data 0 Indicates that the transmitted audio data is suitable for conversion to an analog signal or for further digital processing. (default) 1 Indicates that the transmitted audio data is not suitable for conversion to an analog signal or for further digital processing. Transmitter Block Start Input/Output Mode This bit is used to select the input/output mode for the DIT block start pin, BLS (pin 35). TXIS[1:0] BLSM BLS Pin Mode 0 Input (default) 1 Output Transmitter Input Data Source These bits are used to select the audio data source for the DIT function block. 38 TXIS1 TXIS0 Output Word Length 0 0 Port A (default) 0 1 Port B 1 0 DIR 1 1 Reserved Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 TXDIV[1:0] Transmitter Master Clock Divider These bits are used to select the Transmitter master clock divider, which determines the output frame rate. TXCLK TXDIV1 TXDIV0 0 0 Clock Divider Divide the master clock by 128. (default) 0 1 Divide the master clock by 256. 1 0 Divide the master clock by 384. 1 1 Divide the master clock by 512. Transmitter Master Clock Source This bit is used to select the master clock source for the Transmitter block. TXCLK Transmitter Master Clock Source 0 MCLK input (default) 1 RXCKO; the recovered master clock from the DIR function block. Register 08: Transmitter Control Register 2 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) BYPMUX1 BYPMUX0 AESMUX LDMUX TXBTD AESOFF TXMUTE TXOFF TXOFF Transmitter Line Driver Output Enable This bit is used to enable or disable the TX+ (pin 32) and TX– (pin 31) line driver outputs. TXOFF TXMUTE Transmitter Line Driver 0 Enabled; the line driver outputs function normally. (default) 1 Disabled; the line driver outputs are forced low. Transmitter Audio Data Mute This bit is used to set the 24 bits of audio and auxiliary data to all zeros for both Channels 1 and 2. TXMUTE AESOFF Transmitter Audio Data Mute 0 Disabled (default) 1 Enabled; the audio data for both channels 1 and 2 are set to all zeros. AESOUT Output Enable This bit is used to enable or disable the AESOUT (pin 34) buffered AES3-encoded CMOS logic level output. AESOFF TXBTD AESOUT Output 0 Enabled; the AESOUT pin functions normally. (default) 1 Disabled; the AESOUT pin is forced low. Transmitter C and U Data Buffer Transfer Disable This bit is used to enable and disable buffer transfers between the DIT User Access (UA) and DIT Transmitter Access (TA) buffers for both channel status (C) and user (U) data. Buffer transfers may be disabled, allowing the user to write new C and U data to the UA buffers via the SPI or I2C serial host interface. Once updated, UA-to-TA buffer transfers may then be re-enabled, allowing the TA buffer to be updated and the new C and U data to be transmitted at the start of the next block. TXBTD User Access (UA) to Transmitter Access (TA) Buffer Transfers 0 Enabled (default) 1 Disabled; allows the user to update DIT C and U data buffers. Note: The TXCUS0 and TXCUS1 bits in control register 0x09 must be set to a non-zero value in order for DIT UA buffer updates to occur. LDMUX Transmitter Line Driver Input Source Selection This bit is used to select the input source for the DIT differential line driver outputs. LDMUX AESMUX Line Driver Input Source 0 DIT AES3 encoder output (default) 1 Bypass multiplexer output AESOUT CMOS Buffer Input Source Selection This bit is used to select the input source for the AESOUT CMOS logic level output. AESMUX AESOUT Buffer Input Source 0 DIT AES3 encoder output (default) 1 Bypass multiplexer output Submit Documentation Feedback 39 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 BYPMUX[1:0] Bypass Multiplexer Source Selection These bits select the line receiver output to be utilized as the bypass multiplexer data source. BYPMUX1 BYPMUX0 0 0 Line Receiver Output Selection RX1 (default) 0 1 RX2 1 0 RX3 1 1 RX4 Register 09: Transmitter Control Register 3 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 0 VALSEL TXCUS1 TXCUS0 TXCUS[1:0] Transmitter Channel Status and User Data Source These bits select the source of the channel status (or C) data and user (or U) data which is used to load the DIT User Access (UA) buffers. VALSEL TXCUS1 TXCUS0 0 0 DIT UA Buffer Source The buffers will not be updated. (default) 0 1 The buffers are updated via the SPI or I2C host interface. 1 0 The buffers are updated via the DIR RA buffers. 1 1 The first 10 bytes of the buffers are updated via the SPI or I2C host, while the remainder of the buffers are updated via the DIR RA buffers. Transmitter Validity Bit Source This bit is utilized to select the source for the validity (or V) bit in the AES3-encoded output data stream. VALSEL Validity (or V) Bit Source Selection 0 The VALID bit in control register 0x07. 1 The V bit is transferred from the DIR block with zero latency. Register 0A: DIT Status (Read-Only) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 0 0 TSLIP TBTI TBTI Transmitter Buffer Transfer Status, Active High When DIT User Access (UA) to Transmitter Access (TA) buffer transfers are enabled (the TXBTD bit in control register 0x08 is set to 0), and the TBTI interrupt is unmasked (the MTBTI bit in control register 0x0B is set to 1), the TBTI bit will be set to 1 when the UA-to-TA buffer transfer has completed. This configuration also causes the INT output (pin 23) to be driven low and the TX bit in status register 0x02 to be set to 1, indicating that an interrupt has occurred. TSLIP Transmitter Source Data Slip Status, Active High The TSLIP bit will be set to 1 when either an asynchronous data slip or block start condition is detected, and the TSLIP interrupt is unmasked (the MTSLIP bit in control register 0x0B is set to 1). The BSSL bit in control register 0x07 is used to set the source for this interrupt. The TSLIP bit being forced to 1 will also cause the INT output (pin 23) to be driven low and the TX bit in status register 0x02 to be set to 1, indicating that an interrupt has occurred. Register 0B: DIT Interrupt Mask Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 0 0 MTSLIP MTBTI MBTI Transmitter Buffer Transfer Interrupt Mask MTBI MTSLIP BTI interrupt is masked. (default) 1 BTI interrupt is enabled. Transmitter TSLIP Interrupt Mask MTSLIP 40 BTI Interrupt Mask 0 TSLIP Interrupt Mask 0 TSLIP interrupt is masked. (default) 1 TSLIP interrupt is enabled. Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 0C: DIT Interrupt Mode Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 TSLIPM1 TSLIPM0 TBTIM1 TBTIM0 TBTIM[1:0] Transmitter Buffer Transfer Interrupt Mode These bits are utilized to select the active trigger state for the BTI interrupt. TSLIPM[1:0] TBTIM1 TBTIM0 0 0 Interrupt Active State Rising edge active (default) 0 1 Falling edge active 1 0 Level active 1 1 Reserved Transmitter Data Source Slip Interrupt Mode These bits are utilized to select the active trigger state for the TSLIP interrupt. TSLIPM1 TSLIPM0 0 0 Interrupt Active State Rising edge active (default) 0 1 Falling edge active 1 0 Level active 1 1 Reserved Register 0D: Receiver Control Register 1 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 RXBTD RXCLK 0 RXMUX1 RXMUX0 RXMUX[1:0] Receiver Input Source Selection These bits are used to select the output of the line receiver to be used as the input data source for the DIR core. RXCLK RXMUX1 RXMUX0 0 0 Input Selection RX1 (default) 0 1 RX2 1 0 RX3 1 1 RX4 Receiver Reference Clock Source This bit is used to select the reference clock source for PLL1 in the DIR core. RXCLK RXBTD Receiver Reference Clock 0 RXCKI (default) 1 MCLK Receiver C and U Data Buffer Transfer Disable This bit is used to enable and disable buffer transfers between the Receiver Access (RA) and User Access (UA) buffers for both channel status (C) and user (U) data. Buffer transfers are typically disabled to allow the customer to read C and U data from the DIR UA buffer via the SPI or I2C serial host interface. Once read, the RA-to-UA buffer transfer can be re-enabled to allow the RA buffer to update the contents of the UA buffer in real time. RXBTD Receiver Access (RA) to User Access (UA) Buffer Transfers 0 Enabled (default) 1 Disabled; the user may read C and U data from the DIR UA buffers. Submit Documentation Feedback 41 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 0E: Receiver Control Register 2 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 LOL RXAMLL RXCKOD1 RXCKOD0 RXCKOE RXCKOE RXCKOE Output Enable This bit is used to enable or disable the recovered clock output, RXCKO (pin 12). When disabled, the output is set to a high-impedance state. RXCKOE RXCKOD[1:0] RXCKO Output State 0 Disabled; the RXCKO output is set to high-impedance. (default) 1 Enabled; the recovered master clock is available at RXCKO. RXCKO Output Clock Divider These bits are utilized to set the clock divider at the output of PLL2. The output of the divider is the RXCKO clock, available internally or at the RXCKO output (pin 12). RXAMLL RXCKOD1 RXCKOD0 0 0 RXCKO Output Divider Passthrough; no division is performed. (default) 0 1 Divide the PLL2 clock output by 2. 1 0 Divide the PLL2 clock output by 4. 1 1 Divide the PLL2 clock output by 8. Receiver Automatic Mute for Loss of Lock This bit is used to set the automatic mute function for the DIR block when a loss of lock is indicated by both the AES3 decoder and PLL2. RXAMLL LOL Receiver Auto-Mute Function 0 Disabled (default) 1 Enabled; audio data output from the DIR block is forced low for a loss of lock condition. Receiver Loss of Lock Mode for the Recovered Clock (output from PLL2) This bit is used to set the mode of operation for PLL2 when a loss of lock condition occurs. LOL Receiver PLL2 Operation 0 The PLL2 output clock is stopped for a loss of lock condition. (default) 1 The PLL2 output clock free runs when a loss of lock condition occurs. Register 0F: Receiver PLL1 Configuration Register 1 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) P3 P2 P1 P0 J5 J4 J3 J2 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) J1 J0 D13 D12 D11 D10 D9 D8 Register 10: Receiver PLL1 Configuration Register 2 42 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 11: Receiver PLL1 Configuration Register 3 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) D7 D6 D5 D4 D3 D2 D1 D0 Registers 0x0F through 0x11 are utilized to program PLL1 in the DIR core. PLL1 multiplies the DIR reference clock source to an oversampling rate which is adequate for AES3 decoder operation. PLL1 is programmed using the following relationship: (CLOCK × K) / P = 98.304MHz where: CLOCK = frequency of the DIR reference clock source. K = J.D, where the integer part J = 1 to 63, and the fractional part D = 0 to 9999. P = the pre-divider value, which may be set to any 4-bit value that meets the conditions stated below. The following conditions must be met for the values of P, J, and D: If D = 0, then: If D ≠ 0, then: 2 MHz ≤ (CLOCK / P) ≤ 20 MHz and 4 ≤ J ≤ 55. 10 MHz ≤ (CLOCK / P) ≤ 20 MHz and 4 ≤ J ≤11. Referring to registers 0x0F through 0x11: P is programmed using bits P[3:0]. J is programmed using bits J[5:0]. D is programmed using bits D[13:0]. Table 4 shows values for P, J, and D for common DIR reference clock rates. Table 4. PLL1 Register Values for Common Reference Clock Rates REFERENCE CLOCK RATE (MHz) P J D ERROR (%) 8.1920 1 12 0 0.0000 11.2896 1 8 7075 0.0002 12.2880 1 8 0 0.0000 16.3840 1 6 0 0.0000 22.5792 2 8 7075 0.0002 24.5760 2 8 0 0.0000 27.0000 2 7 2818 0.0003 Register 12: Non-PCM Audio Detection Status Register (Read-Only) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 0 0 DTS CD/LD IEC61937 IEC61937 This bit is utilized to indicate the detection of an IEC 61937 data reduced audio format (includes Dolby AC-3, DTS, etc.) for DVD playback or general transmission purposes. IEC61937 DTS CD/LD Status 0 Data is not an IEC61937 format. 1 Data is an IEC61937 format. Refer to the PC and PD preamble registers (addresses 0x29 through 0x2C) for data type and burst length. This bit is used to indicate the detection of a DTS encoded audio compact disc (CD) or Laserdisc (LD) playback. DTS CD/LD Status 0 The CD/LD is not DTS-encoded. 1 DTS CD/LD playback detected. Submit Documentation Feedback 43 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 13: Receiver Status Register 1 (Read-Only) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 0 0 RXCKR1 RXCKR0 RXCKR[1:0] Maximum Available Recovered Clock Rate These two bits indicate the maximum available RXCKO clock rate based upon the DIR detection circuitry, which determines the frame rate of the incoming AES3-encoded bit stream. Based upon the estimated frame rate, a maximum rate for the recovered clock output (RXCKO) is determined and output from PLL2, as well as being loaded into the RXCKR0 and RXCKR1 status bits. The status of the RXCKR0 and RXCKR1 bits may be utilized to determine the programmed value for the PLL2 output clock divider, set by the RXCKOD0 and RXCKOD1 bits in control register 0x0E. RXCKR1 RXCKR0 0 0 Maximum Available RXCKO Rate Clock rate not determined. 0 1 128fS 1 0 256fS 1 1 512fS Register 14: Receiver Status Register 2 (Read-Only) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) CSCRC PARITY VBIT BPERR QCHG UNLOCK QCRC RBTI Note: Status bits must be unmasked in control register 0x16 in order for the status interrupts to be generated. CSCRC Channel Status CRC Status CSCRC PARITY CRC Status 0 No error 1 CRC error detected Parity Status PARITY VBIT Parity Status 0 No error 1 Parity error detected Validity Bit Status VBIT BPERR Validity Bit 0 Valid audio data indicated 1 Non-valid data indicated Biphase Encoding Error Status BPERR QCHG Biphase Encoding Status 0 No error 1 Biphase encoding error detected Q-Channel Sub-Code Data Change Status QCHG UNLOCK Q-Channel Data Status 0 No change in Q-channel sub-code data. 1 Q-channel data has changed. May be used to trigger a read of the Q-channel sub-code data, registers 0x1F through 0x28. DIR Unlock Error Status UNLOCK QCRC DIR Lock Status 0 No error; the DIR AES3 decoder and PLL2 are locked. 1 DIR lock error; the AES3 decoder and PLL2 are unlocked. Q-Channel Sub-Code CRC Status QCRC RBTI No error 1 Q-channel sub-code data CRC error detected. Receiver Buffer Transfer Interrupt Status RBTI 0 44 Q-Channel CRC Status 0 DIR RA Buffer-to-UA Buffer Transfer Status Buffer transfer incomplete, or no Buffer transfer interrupt indicated Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 1 Buffer transfer completed Register 15: Receiver Status Register 3 (Read-Only) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 0 0 0 OSLIP Note: Status bits must be unmasked in control register 0x17 in order for the status interrupts to be generated. OSLIP Receiver Output Data Slip Error Status OSLIP Receiver OSLIP Error Status 0 No error 1 DIR output data Slip/Repeat error detected An OSLIP interrupt is possible when the DIR output is used as the source for either the Port A or Port B audio serial port and the port is configured to operate in slave mode. Figure 35 shows the timing associated with the OSLIP interrupt. When only one audio serial port (Port A or Port B) is sourced by the DIR output, then the OSLIP status bit and interrupt applies to that port. If both Port A and Port B are sourced by the DIR output, then the OSLIP status bit and interrupt applies to Port A only. AES3 Bit Stream Y X Y X DIR SYNC R L R L LRCK, Left- or RightJustified Formats (input) L R L R L R L R 2 LRCK, I S Format (input) ±5% ±5% Data Slip or Repeat may occur when the LRCK edges indicated are within the ±5% window. Figure 35. DIR Output Slip/Repeat (OSLIP) Behavior Register 16: Receiver Interrupt Mask Register 1 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) MCSCRC MPARITY MVBIT MBPERR MQCHG MUNLOCK MQCRC MRBTI MCSCRC Channel Status CRC Error Interrupt Mask MCSCRC MPARITY Masked (default) 1 Enabled Parity Error Interrupt Mask MPARITY MVBIT CRC Interrupt 0 Parity Error Interrupt 0 Masked (default) 1 Enabled Validity Error Interrupt Mask MVBIT Validity Error Interrupt 0 Masked (default) 1 Enabled Submit Documentation Feedback 45 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 MBPERR Biphase Encoding Error Interrupt Mask MBPERR MQCHG Biphase Error Interrupt 0 Masked (default) 1 Enabled Q-Channel Sub-Code Data Change Interrupt Mask MQCHG MUNLOCK Q-Channel Data Change Interrupt 0 Masked (default) 1 Enabled DIR Unlock Error Interrupt Mask MUNLOCK MQCRC DIR Unlock Interrupt 0 Masked (default) 1 Enabled Q-Channel Sub-Code CRC Error Interrupt Mask MQCRC MRBTI Q-Channel CRC Error Interrupt 0 Masked (default) 1 Enabled Receiver Buffer Transfer Interrupt Mask MRBTI Receiver Buffer Transfer Interrupt 0 Masked (default) 1 Enabled Register 17: Receiver Interrupt Mask Register 2 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 0 0 0 MOSLIP MOSLIP Receiver Output Data Slip Error Mask MOSLIP Receiver OSLIP Error Interrupt 0 Masked (default) 1 Enabled Register 18: Receiver Interrupt Mode Register 1 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) QCHGM1 QCHGM0 UNLOCKM1 UNLOCKM0 QCRCM1 QCRCM0 RBTIM1 RBTIM0 QCHGM[1:0] UNLOCKM[1:0] QCRCM[1:0] 46 Q-Channel Sub-Code Data Change Interrupt Mode QCHGM1 QCHGM0 0 0 Interrupt Active State Rising edge active (default) 0 1 Falling edge active 1 0 Level active 1 1 Reserved DIR Unlock Error Interrupt Mode UNLOCKM1 UNLOCKM0 0 0 Interrupt Active State Rising edge active (default) 0 1 Falling edge active 1 0 Level active 1 1 Reserved Q-Channel Sub-Code CRC Error Interrupt Mode QCRCM1 QCRCM0 0 0 Interrupt Active State Rising edge active (default) 0 1 Falling edge active 1 0 Level active 1 1 Reserved Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 RBTIM[1:0] Receive Buffer Transfer Interrupt Mode RBTIM1 RBTIM0 0 0 Interrupt Active State Rising edge active (default) 0 1 Falling edge active 1 0 Level active 1 1 Reserved Register 19: Receiver Interrupt Mode Register 2 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) CSCRCM1 CSCRCM0 PARITYM1 PARITYM0 VBITM1 VBITM0 BPERRM1 BPERRM0 CSCRCM[1:0] PARITYM[1:0] VBITM[1:0] BPERRM[1:0] Channel Status CRC Error Interrupt Mode CSCRCM1 CSCRCM0 0 0 Interrupt Active State Rising edge active (default) 0 1 Falling edge active 1 0 Level active 1 1 Reserved Parity Error Interrupt Mode PARITYM1 PARITYM0 0 0 Interrupt Active State Rising edge active (default) 0 1 Falling edge active 1 0 Level active 1 1 Reserved Validity Error Interrupt Mode VBITM1 VBITM0 0 0 Interrupt Active State Rising edge active (default) 0 1 Falling edge active 1 0 Level active 1 1 Reserved Biphase Encoding Error Interrupt Mode BPERRM1 BPERRM0 0 0 Interrupt Active State Rising edge active (default) 0 1 Falling edge active 1 0 Level active 1 1 Reserved Register 1A: Receiver Interrupt Mode Register 3 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 0 0 OSLIPM1 OSLIPM0 OSLIPM[1:0] Receiver Output Data Slip Error Interrupt Mode OSLIPM1 OSLIPM0 0 0 Interrupt Active State Rising edge active (default) 0 1 Falling edge active 1 0 Level active 1 1 Reserved Submit Documentation Feedback 47 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 1B: General-Purpose Output 1 (GPO1) Control Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 GPO13 GPO12 GPO11 GPO10 GPO[13:10] General-Purpose Output 1 (GPO1) Configuration These bits are used to set the state or data source for the general-purpose digital output pin GPO1. GPO13 GPO12 GPO11 GPO10 0 0 0 0 GPO1 Function GPO1 is forced low (default) 0 0 0 1 GPO1 is forced high 0 0 1 0 Reserved 0 0 1 1 Transmitter interrupt, active low 0 1 0 0 Receiver interrupt, active low 0 1 0 1 Receiver 50/15µs pre-emphasis, active low 0 1 1 0 Receiver non-audio data, active high 0 1 1 1 Receiver non-valid data, active high 1 0 0 0 Receiver channel status bit 1 0 0 1 Receiver user data bit 1 0 1 0 Receiver block start clock 1 0 1 1 Receiver COPY bit (0 = copyright asserted, 1 = copyright not asserted) 1 1 0 0 Receiver L-bit (0 = first generation or higher, 1 = original) 1 1 0 1 Receiver parity error, active high 1 1 1 0 Receiver internal sync clock 1 1 1 1 Transmitter internal sync clock Register 1C: General-Purpose Output 2 (GPO2) Control Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 GPO23 GPO22 GPO21 GPO20 GPO[23:20] General-Purpose Output 2 (GPO2) Configuration These bits are used to set the state or data source for the general-purpose digital output pin GPO2. 48 GPO23 GPO22 GPO21 GPO20 0 0 0 0 GPO2 is forced low (default) 0 0 0 1 GPO2 is forced high 0 0 1 0 Reserved 0 0 1 1 Transmitter interrupt, active low 0 1 0 0 Receiver interrupt, active low 0 1 0 1 Receiver 50/15µs pre-emphasis, active low 0 1 1 0 Receiver non-audio data, active high 0 1 1 1 Receiver non-valid data, active high 1 0 0 0 Receiver channel status bit 1 0 0 1 Receiver user data bit 1 0 1 0 Receiver block start clock 1 0 1 1 Receiver COPY bit (0 = copyright asserted, 1 = copyright not asserted) 1 1 0 0 Receiver L-bit (0 = first generation or higher, 1 = original) 1 1 0 1 Receiver parity error, active high 1 1 1 0 Receiver internal sync clock 1 1 1 1 Transmitter internal sync clock Submit Documentation Feedback GPO2 Function DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 1D: General-Purpose Output 3 (GPO3) Control Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 GPO33 GPO32 GPO31 GPO30 GPO[33:30] General-Purpose Output 3 (GPO3) Configuration These bits are used to set the state or data source for the general-purpose digital output pin GPO3. GPO33 GPO32 GPO31 GPO30 0 0 0 0 GPO3 Function GPO3 is forced low (default) 0 0 0 1 GPO3 is forced high 0 0 1 0 Reserved 0 0 1 1 Transmitter interrupt, active low 0 1 0 0 Receiver interrupt, active low 0 1 0 1 Receiver 50/15µs pre-emphasis, active low 0 1 1 0 Receiver non-audio data, active high 0 1 1 1 Receiver non-valid data, active high 1 0 0 0 Receiver channel status bit 1 0 0 1 Receiver user data bit 1 0 1 0 Receiver block start clock 1 0 1 1 Receiver COPY bit (0 = copyright asserted, 1 = copyright not asserted) 1 1 0 0 Receiver L-bit (0 = first generation or higher, 1 = original) 1 1 0 1 Receiver parity error, active high 1 1 1 0 Receiver internal sync clock 1 1 1 1 Transmitter internal sync clock Register 1E: General-Purpose Output 4 (GPO4) Control Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 GPO43 GPO42 GPO41 GPO40 GPO[43:40] General-Purpose Output 4 (GPO4) Configuration These bits are used to set the state or data source for the general-purpose digital output pin GPO4. GPO43 GPO42 GPO41 GPO40 0 0 0 0 GPO4 is forced low (default) 0 0 0 1 GPO4 is forced high 0 0 1 0 Reserved 0 0 1 1 Transmitter interrupt, active low 0 1 0 0 Receiver interrupt, active low 0 1 0 1 Receiver 50/15µs pre-emphasis, active low 0 1 1 0 Receiver non-audio data, active high 0 1 1 1 Receiver non-valid data, active high 1 0 0 0 Receiver channel status bit 1 0 0 1 Receiver user data bit 1 0 1 0 Receiver block start clock 1 0 1 1 Receiver COPY bit (0 = copyright asserted, 1 = copyright not asserted) 1 1 0 0 Receiver L-bit (0 = first generation or higher, 1 = original) 1 1 0 1 Receiver parity error, active high 1 1 1 0 Receiver internal sync clock 1 1 1 1 Transmitter internal sync clock Submit Documentation Feedback GPO4 Function 49 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Registers 1F through 28: Q-Channel Sub-Code Data Registers Registers 0x1F through 0x28 comprise the Q-channel sub-code buffer, which may be accessed for audio CD playback. The Q-channel data provides information regarding the playback status for the current disc. The buffer data is decoded by the DIR block. Register 1F: Q-Channel Sub-Code Data Register 1 (Read-Only), Bits[7:0], Control and Address Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Register 20: Q-Channel Sub-Code Data Register 2 (Read-Only), Bits[15:8], Track Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Register 21: Q-Channel Sub-Code Data Register 3 (Read-Only), Bits[23:16], Index Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Register 22: Q-Channel Sub-Code Data Register 4 (Read-Only), Bits[31:24], Minutes Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Register 23: : Q-Channel Sub-Code Data Register 5 (Read-Only), Bits[39:32], Seconds Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Register 24: : Q-Channel Sub-Code Data Register 6 (Read-Only), Bits[47:40], Frame Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Register 25: Q-Channel Sub-Code Data Register 7 (Read-Only), Bits[55:48], Zero Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Q48 Q49 Q50 Q51 Q52 Q53 Q54 Q55 Register 26: Q-Channel Sub-Code Data Register 8 (Read-Only), Bits[63:56], AMIN Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Register 27: Q-Channel Sub-Code Data Register 9 (Read-Only), Bits[71:64], ASEC Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Register 28: Q-Channel Sub-Code Data Register 10 (Read-Only), Bits[79:72], AFRAME 50 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Q72 Q73 Q74 Q75 Q76 Q77 Q78 Q79 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Registers 29 through 2C: IEC61937 PC/PD Burst Preamble The PC and PD burst preambles are part of the IEC61937 standard for transmission of data reduced, non-PCM audio over a standard two-channel interface (IEC60958). Examples of data-reduced formats include Dolby AC-3, DTS, various flavors of MPEG audio (including AAC), and Sony ATRAC. The PA and PB preambles provide synchronization data, and are fixed values of 0xF872 and 0x4E1F, respectively. The PC preamble indicates the type of data being carried by the interface and the PD preamble indicates the length of the burst, given as number of bits. Registers 0x29 through 0x2C contain the PC and PD preambles as decoded by the DIR block. Register 29: Burst Preamble PC High-Byte Status Register (Read-Only) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) PC15 PC14 PC13 PC12 PC11 PC10 PC09 PC08 Register 2A: Burst Preamble PC Low-Byte Status Register (Read-Only) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) PC07 PC06 PC05 PC04 PC03 PC02 PC01 PC00 PC[4:0], Hex Data Type 00 Null 01 Dolby AC-3 02 Reserved 03 Pause 04 MPEG-1 layer 1 05 MPEG-1 layer 2 or 3, or MPEG-2 without extension 06 MPEG-2 Data with extension 07 MPEG-2 AAC ADTS 08 MPEG-2 layer 1 low sample rate 09 MPEG-2 layer 2 or 3 low sample rate 0A Reserved 0B DTS type 1 0C DTS type 2 0D DTS type 3 0E ATRAC 0F ATRAC2/3 10-1F Reserved Bits PC[6:5] are both set to 0. Bit PC[7] is an Error Flag, where: 0 = A valid burst-payload; 1 = Burst-payload may contain errors. Bits PC[12:8] are data-type dependent. Bits PC[15:13] indicate the stream number, which is set to 0. Register 2B: Burst Preamble PD High-Byte Status Register (Read-Only) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) PD15 PD14 PD13 PD12 PD11 PD10 PD09 PD08 Register 2C: Burst Preamble PD Low-Byte Status Register (Read-Only) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) PD07 PD06 PD05 PD04 PD03 PD02 PD01 PD00 Submit Documentation Feedback 51 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 7F: Page Selection Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 0 0 PAGE1 PAGE0 PAGE[1:0] Page Selection These bits are utilized to select one of three register pages for write and/or read access via the SPI or I2C serial host interface. The Page Selection Register is present on every register page at address 0x7F, allowing movement between pages as necessary. PAGE1 PAGE0 0 0 Register/Buffer Page Selection Page 0, control and status registers (default) 0 1 Page 1, DIR channel status and user data buffers 1 0 Page 2, DIT channel status and user data buffers 1 1 Page 3, reserved CHANNEL STATUS AND USER DATA BUFFER MAPS Table 5 through Table 8 show the buffer maps for the DIR and DIT channel status and user data buffers. For Table 5, the channel status byte definitions are dependent on the transmission mode, either Professional or Consumer. Bit 0 of Byte 0 defines the transmission mode, 0 for Consumer mode, and 1 for Professional mode. This is applicable for Table 5 and Table 6. For Table 7, the channel status byte definitions are dependent on the transmission mode, either Professional or Consumer. Bit 0 of Byte 0 defines the transmission mode, 0 for Consumer mode, and 1 for Professional mode. In Professional mode, Byte 23 for each channel is reserved for CRC data, which is automatically calculated and encoded by the DIT. There is no need to program Byte 23 for either channel in Professional mode. 52 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 CHANNEL STATUS AND USER DATA BUFFER MAPS (continued) Table 5. DIR Channel Status Data Buffer Map (Register Page 1) ADDRESS (Hex) CHANNEL BYTE BIT 0 (MSB) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 0 1 0 D0 D1 D2 D3 D4 D5 D6 D7 1 2 0 D0 D1 D2 D3 D4 D5 D6 D7 2 1 1 D0 D1 D2 D3 D4 D5 D6 D7 3 2 1 D0 D1 D2 D3 D4 D5 D6 D7 4 1 2 D0 D1 D2 D3 D4 D5 D6 D7 5 2 2 D0 D1 D2 D3 D4 D5 D6 D7 6 1 3 D0 D1 D2 D3 D4 D5 D6 D7 7 2 3 D0 D1 D2 D3 D4 D5 D6 D7 8 1 4 D0 D1 D2 D3 D4 D5 D6 D7 9 2 4 D0 D1 D2 D3 D4 D5 D6 D7 A 1 5 D0 D1 D2 D3 D4 D5 D6 D7 B 2 5 D0 D1 D2 D3 D4 D5 D6 D7 C 1 6 D0 D1 D2 D3 D4 D5 D6 D7 D 2 6 D0 D1 D2 D3 D4 D5 D6 D7 E 1 7 D0 D1 D2 D3 D4 D5 D6 D7 F 2 7 D0 D1 D2 D3 D4 D5 D6 D7 10 1 8 D0 D1 D2 D3 D4 D5 D6 D7 11 2 8 D0 D1 D2 D3 D4 D5 D6 D7 12 1 9 D0 D1 D2 D3 D4 D5 D6 D7 13 2 9 D0 D1 D2 D3 D4 D5 D6 D7 14 1 10 D0 D1 D2 D3 D4 D5 D6 D7 15 2 10 D0 D1 D2 D3 D4 D5 D6 D7 16 1 11 D0 D1 D2 D3 D4 D5 D6 D7 17 2 11 D0 D1 D2 D3 D4 D5 D6 D7 18 1 12 D0 D1 D2 D3 D4 D5 D6 D7 19 2 12 D0 D1 D2 D3 D4 D5 D6 D7 1A 1 13 D0 D1 D2 D3 D4 D5 D6 D7 1B 2 13 D0 D1 D2 D3 D4 D5 D6 D7 1C 1 14 D0 D1 D2 D3 D4 D5 D6 D7 1D 2 14 D0 D1 D2 D3 D4 D5 D6 D7 1E 1 15 D0 D1 D2 D3 D4 D5 D6 D7 1F 2 15 D0 D1 D2 D3 D4 D5 D6 D7 20 1 16 D0 D1 D2 D3 D4 D5 D6 D7 21 2 16 D0 D1 D2 D3 D4 D5 D6 D7 22 1 17 D0 D1 D2 D3 D4 D5 D6 D7 23 2 17 D0 D1 D2 D3 D4 D5 D6 D7 24 1 18 D0 D1 D2 D3 D4 D5 D6 D7 25 2 18 D0 D1 D2 D3 D4 D5 D6 D7 26 1 19 D0 D1 D2 D3 D4 D5 D6 D7 27 2 19 D0 D1 D2 D3 D4 D5 D6 D7 28 1 20 D0 D1 D2 D3 D4 D5 D6 D7 29 2 20 D0 D1 D2 D3 D4 D5 D6 D7 2A 1 21 D0 D1 D2 D3 D4 D5 D6 D7 2B 2 21 D0 D1 D2 D3 D4 D5 D6 D7 2C 1 22 D0 D1 D2 D3 D4 D5 D6 D7 2D 2 22 D0 D1 D2 D3 D4 D5 D6 D7 2E 1 23 D0 D1 D2 D3 D4 D5 D6 D7 2F 2 23 D0 D1 D2 D3 D4 D5 D6 D7 Submit Documentation Feedback 53 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Table 6. DIR User Data Buffer Map (Register Page 1) ADDRESS (Hex) CHANNEL BYTE BIT 0 (MSB) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 40 1 0 D0 D1 D2 D3 D4 D5 D6 D7 41 2 0 D0 D1 D2 D3 D4 D5 D6 D7 42 1 1 D0 D1 D2 D3 D4 D5 D6 D7 43 2 1 D0 D1 D2 D3 D4 D5 D6 D7 44 1 2 D0 D1 D2 D3 D4 D5 D6 D7 45 2 2 D0 D1 D2 D3 D4 D5 D6 D7 46 1 3 D0 D1 D2 D3 D4 D5 D6 D7 47 2 3 D0 D1 D2 D3 D4 D5 D6 D7 48 1 4 D0 D1 D2 D3 D4 D5 D6 D7 49 2 4 D0 D1 D2 D3 D4 D5 D6 D7 4A 1 5 D0 D1 D2 D3 D4 D5 D6 D7 4B 2 5 D0 D1 D2 D3 D4 D5 D6 D7 4C 1 6 D0 D1 D2 D3 D4 D5 D6 D7 4D 2 6 D0 D1 D2 D3 D4 D5 D6 D7 4E 1 7 D0 D1 D2 D3 D4 D5 D6 D7 4F 2 7 D0 D1 D2 D3 D4 D5 D6 D7 50 1 8 D0 D1 D2 D3 D4 D5 D6 D7 51 2 8 D0 D1 D2 D3 D4 D5 D6 D7 52 1 9 D0 D1 D2 D3 D4 D5 D6 D7 53 2 9 D0 D1 D2 D3 D4 D5 D6 D7 54 1 10 D0 D1 D2 D3 D4 D5 D6 D7 55 2 10 D0 D1 D2 D3 D4 D5 D6 D7 56 1 11 D0 D1 D2 D3 D4 D5 D6 D7 57 2 11 D0 D1 D2 D3 D4 D5 D6 D7 58 1 12 D0 D1 D2 D3 D4 D5 D6 D7 59 2 12 D0 D1 D2 D3 D4 D5 D6 D7 5A 1 13 D0 D1 D2 D3 D4 D5 D6 D7 5B 2 13 D0 D1 D2 D3 D4 D5 D6 D7 5C 1 14 D0 D1 D2 D3 D4 D5 D6 D7 5D 2 14 D0 D1 D2 D3 D4 D5 D6 D7 5E 1 15 D0 D1 D2 D3 D4 D5 D6 D7 5F 2 15 D0 D1 D2 D3 D4 D5 D6 D7 60 1 16 D0 D1 D2 D3 D4 D5 D6 D7 61 2 16 D0 D1 D2 D3 D4 D5 D6 D7 62 1 17 D0 D1 D2 D3 D4 D5 D6 D7 63 2 17 D0 D1 D2 D3 D4 D5 D6 D7 64 1 18 D0 D1 D2 D3 D4 D5 D6 D7 65 2 18 D0 D1 D2 D3 D4 D5 D6 D7 66 1 19 D0 D1 D2 D3 D4 D5 D6 D7 67 2 19 D0 D1 D2 D3 D4 D5 D6 D7 68 1 20 D0 D1 D2 D3 D4 D5 D6 D7 69 2 20 D0 D1 D2 D3 D4 D5 D6 D7 6A 1 21 D0 D1 D2 D3 D4 D5 D6 D7 6B 2 21 D0 D1 D2 D3 D4 D5 D6 D7 6C 1 22 D0 D1 D2 D3 D4 D5 D6 D7 6D 2 22 D0 D1 D2 D3 D4 D5 D6 D7 6E 1 23 D0 D1 D2 D3 D4 D5 D6 D7 6F 2 23 D0 D1 D2 D3 D4 D5 D6 D7 54 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Table 7. DIT Channel Status Data Buffer Map (Register Page 2) ADDRESS (Hex) CHANNEL BYTE BIT 0 (MSB) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 0 1 0 D0 D1 D2 D3 D4 D5 D6 D7 1 2 0 D0 D1 D2 D3 D4 D5 D6 D7 2 1 1 D0 D1 D2 D3 D4 D5 D6 D7 3 2 1 D0 D1 D2 D3 D4 D5 D6 D7 4 1 2 D0 D1 D2 D3 D4 D5 D6 D7 5 2 2 D0 D1 D2 D3 D4 D5 D6 D7 6 1 3 D0 D1 D2 D3 D4 D5 D6 D7 7 2 3 D0 D1 D2 D3 D4 D5 D6 D7 8 1 4 D0 D1 D2 D3 D4 D5 D6 D7 9 2 4 D0 D1 D2 D3 D4 D5 D6 D7 A 1 5 D0 D1 D2 D3 D4 D5 D6 D7 B 2 5 D0 D1 D2 D3 D4 D5 D6 D7 C 1 6 D0 D1 D2 D3 D4 D5 D6 D7 D 2 6 D0 D1 D2 D3 D4 D5 D6 D7 E 1 7 D0 D1 D2 D3 D4 D5 D6 D7 F 2 7 D0 D1 D2 D3 D4 D5 D6 D7 10 1 8 D0 D1 D2 D3 D4 D5 D6 D7 11 2 8 D0 D1 D2 D3 D4 D5 D6 D7 12 1 9 D0 D1 D2 D3 D4 D5 D6 D7 13 2 9 D0 D1 D2 D3 D4 D5 D6 D7 14 1 10 D0 D1 D2 D3 D4 D5 D6 D7 15 2 10 D0 D1 D2 D3 D4 D5 D6 D7 16 1 11 D0 D1 D2 D3 D4 D5 D6 D7 17 2 11 D0 D1 D2 D3 D4 D5 D6 D7 18 1 12 D0 D1 D2 D3 D4 D5 D6 D7 19 2 12 D0 D1 D2 D3 D4 D5 D6 D7 1A 1 13 D0 D1 D2 D3 D4 D5 D6 D7 1B 2 13 D0 D1 D2 D3 D4 D5 D6 D7 1C 1 14 D0 D1 D2 D3 D4 D5 D6 D7 1D 2 14 D0 D1 D2 D3 D4 D5 D6 D7 1E 1 15 D0 D1 D2 D3 D4 D5 D6 D7 1F 2 15 D0 D1 D2 D3 D4 D5 D6 D7 20 1 16 D0 D1 D2 D3 D4 D5 D6 D7 21 2 16 D0 D1 D2 D3 D4 D5 D6 D7 22 1 17 D0 D1 D2 D3 D4 D5 D6 D7 23 2 17 D0 D1 D2 D3 D4 D5 D6 D7 24 1 18 D0 D1 D2 D3 D4 D5 D6 D7 25 2 18 D0 D1 D2 D3 D4 D5 D6 D7 26 1 19 D0 D1 D2 D3 D4 D5 D6 D7 27 2 19 D0 D1 D2 D3 D4 D5 D6 D7 28 1 20 D0 D1 D2 D3 D4 D5 D6 D7 29 2 20 D0 D1 D2 D3 D4 D5 D6 D7 2A 1 21 D0 D1 D2 D3 D4 D5 D6 D7 2B 2 21 D0 D1 D2 D3 D4 D5 D6 D7 2C 1 22 D0 D1 D2 D3 D4 D5 D6 D7 2D 2 22 D0 D1 D2 D3 D4 D5 D6 D7 2E 1 23 D0 D1 D2 D3 D4 D5 D6 D7 2F 2 23 D0 D1 D2 D3 D4 D5 D6 D7 Submit Documentation Feedback 55 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Table 8. DIT User Data Buffer Map (Register Page 2) ADDRESS (Hex) CHANNEL BYTE BIT 0 (MSB) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 40 1 0 D0 D1 D2 D3 D4 D5 D6 D7 41 2 0 D0 D1 D2 D3 D4 D5 D6 D7 42 1 1 D0 D1 D2 D3 D4 D5 D6 D7 43 2 1 D0 D1 D2 D3 D4 D5 D6 D7 44 1 2 D0 D1 D2 D3 D4 D5 D6 D7 45 2 2 D0 D1 D2 D3 D4 D5 D6 D7 46 1 3 D0 D1 D2 D3 D4 D5 D6 D7 47 2 3 D0 D1 D2 D3 D4 D5 D6 D7 48 1 4 D0 D1 D2 D3 D4 D5 D6 D7 49 2 4 D0 D1 D2 D3 D4 D5 D6 D7 4A 1 5 D0 D1 D2 D3 D4 D5 D6 D7 4B 2 5 D0 D1 D2 D3 D4 D5 D6 D7 4C 1 6 D0 D1 D2 D3 D4 D5 D6 D7 4D 2 6 D0 D1 D2 D3 D4 D5 D6 D7 4E 1 7 D0 D1 D2 D3 D4 D5 D6 D7 4F 2 7 D0 D1 D2 D3 D4 D5 D6 D7 50 1 8 D0 D1 D2 D3 D4 D5 D6 D7 51 2 8 D0 D1 D2 D3 D4 D5 D6 D7 52 1 9 D0 D1 D2 D3 D4 D5 D6 D7 53 2 9 D0 D1 D2 D3 D4 D5 D6 D7 54 1 10 D0 D1 D2 D3 D4 D5 D6 D7 55 2 10 D0 D1 D2 D3 D4 D5 D6 D7 56 1 11 D0 D1 D2 D3 D4 D5 D6 D7 57 2 11 D0 D1 D2 D3 D4 D5 D6 D7 58 1 12 D0 D1 D2 D3 D4 D5 D6 D7 59 2 12 D0 D1 D2 D3 D4 D5 D6 D7 5A 1 13 D0 D1 D2 D3 D4 D5 D6 D7 5B 2 13 D0 D1 D2 D3 D4 D5 D6 D7 5C 1 14 D0 D1 D2 D3 D4 D5 D6 D7 5D 2 14 D0 D1 D2 D3 D4 D5 D6 D7 5E 1 15 D0 D1 D2 D3 D4 D5 D6 D7 5F 2 15 D0 D1 D2 D3 D4 D5 D6 D7 60 1 16 D0 D1 D2 D3 D4 D5 D6 D7 61 2 16 D0 D1 D2 D3 D4 D5 D6 D7 62 1 17 D0 D1 D2 D3 D4 D5 D6 D7 63 2 17 D0 D1 D2 D3 D4 D5 D6 D7 64 1 18 D0 D1 D2 D3 D4 D5 D6 D7 65 2 18 D0 D1 D2 D3 D4 D5 D6 D7 66 1 19 D0 D1 D2 D3 D4 D5 D6 D7 67 2 19 D0 D1 D2 D3 D4 D5 D6 D7 68 1 20 D0 D1 D2 D3 D4 D5 D6 D7 69 2 20 D0 D1 D2 D3 D4 D5 D6 D7 6A 1 21 D0 D1 D2 D3 D4 D5 D6 D7 6B 2 21 D0 D1 D2 D3 D4 D5 D6 D7 6C 1 22 D0 D1 D2 D3 D4 D5 D6 D7 6D 2 22 D0 D1 D2 D3 D4 D5 D6 D7 6E 1 23 D0 D1 D2 D3 D4 D5 D6 D7 6F 2 23 D0 D1 D2 D3 D4 D5 D6 D7 56 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 REFERENCE DOCUMENTS Throughout this data sheet, various standards and documents are repeatedly cited as references. Sources for these documents are listed here so that the reader may obtain the documents for further study. Audio Engineering Society (AES) standards documents, including the AES3, AES11, AES18, and related specifications are available from the AES web site: http://www.aes.org. International Electrotechnical Committee (IEC) standards, including the IEC60958 and IEC61937 are available from the IEC web site: http://www.iec.ch; or the ANSI web site: http://www.ansi.org. The EIAJ CP-1212 (formerly CP-1201) standard is available from the Japanese Electronics and Information Technologies Industries Association (JEITA): http://www.jeita.or.jp/english. The Philips I2C bus specification is available from Philips: http://www.philips.com. The version utilized as a reference for this product is Version 2.1, published in January 2000. Several papers regarding balanced and unbalanced transformer-coupled digital audio interfaces have been published and presented at past AES conventions by Jon D. Paul of Scientific Conversion, Inc. These papers are available for download from: http://www.scientificonversion.com. Submit Documentation Feedback 57 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) DIX4192IPFB ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DIX4192I DIX4192IPFBG4 ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DIX4192I DIX4192IPFBR ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DIX4192I DIX4192IPFBRG4 ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DIX4192I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DIX4192IPFBR Package Package Pins Type Drawing TQFP PFB 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.5 12.0 16.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DIX4192IPFBR TQFP PFB 48 1000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. 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