TI CD74FCT652EN

CD74FCT652
BiCMOS OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCBS734A – JULY 2000 – REVISED JULY 2000
D
D
D
D
D
D
D
D
D
D
EN OR M PACKAGE
(TOP VIEW)
BiCMOS Technology With Low Quiescent
Power
Buffered Inputs
Noninverted Outputs
Input/Output Isolation From VCC
Controlled Output Edge Rates
64-mA Output Sink Current
Output Voltage Swing Limited to 3.7 V
SCR Latch-Up-Resistant BiCMOS Process
and Circuit Design
Multiplexed Real-Time and Stored Data
Package Options Include Plastic
Small-Outline (M) Package and Standard
Plastic (EN) DIP
CLKAB
SAB
OEAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
CLKBA
SBA
OEBA
B1
B2
B3
B4
B5
B6
B7
B8
description
The CD74FCT652 is an octal bus transceiver and resistor with 3-state outputs. It consists of D-type flip-flops
and control circuitry, arranged for multiplexed transmission of data directly from the data bus or from the internal
storage registers. Output-enable (OEAB and OEBA) inputs control the transceiver functions. The select-control
(SAB and SBA) inputs select real-time-data or stored-data transfer. A low-input level selects real-time data, and
a high-input level selects stored data. The select-control circuitry eliminates the typical decoding glitch that
occurs in a multiplexer during the transition between stored data and real-time data.
The device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS
transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing
(0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC
bounce and ground bounce and their effects during simultaneous output switching. The output configuration
also enhances switching speed and is capable of sinking 64 mA.
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flop by low-to-high transitions at
the appropriate clock terminal (CLKAB and CLKBA), regardless of the state of the select or enable control
terminals. When SAB and SBA are in the real-time-transfer mode, it also is possible to store data without using
the internal D-type flip-flop by simultaneously enabling OEAB and OEBA. In this configuration, each output
reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each
set of bus lines remains at its last state.
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).
The CD74FCT652 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CD74FCT652
BiCMOS OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCBS734A – JULY 2000 – REVISED JULY 2000
FUNCTION TABLE
INPUTS
DATA I/O
OEAB
OEBA
CLKAB
CLKBA
L
H
H or L
H or L
X
L
H
↑
↑
X
X
H
↑
H or L
H
H
↑
↑
X
X‡
L
X
H or L
↑
X
L
L
↑
↑
X
L
L
X
X
X
L
L
X
H or L
X
H
H
X
X
L
H
H
H or L
X
H
H
L
H or L
H or L
SAB
H
SBA
OPERATION OR
FUNCTION
A1–A8
B1–B8
X
Input
Input
Isolation
X
Input
Input
Store A and B data
X
Input
Unspecified†
Store A, hold B
X
Input
Unspecified†
Output
Store A in both registers
Input
Hold A, store B
Output
Input
Store B in both registers
L
Output
Input
Real-time B data to A bus
H
Output
Input
Stored B data to A bus
X
Input
Output
Real-time A data to B bus
X
Input
Output
Stored A data to B bus
Output
Stored A data to B bus and
stored B data to A bus
X
X‡
H
Output
† The data output functions can be enabled or disabled by various level combinations at OEAB or OEBA. Data input functions
always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
‡ When select control is low, clocks can occur simultaneously if allowances are made for propagation delays from A to B (B to
A) plus setup and hold times. When select control is high, clocks must be staggered to load both registers.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CD74FCT652
BiCMOS OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
1
23
2
CLKAB CLKBA SAB
X
X
X
22
SBA
L
21
OEBA
H
X
H
1
23
2
CLKAB CLKBA SAB
↑
X
↑
X
↑
↑
23
CLKBA
X
2
SAB
L
X
X
X
BUS A
BUS A
3
1
CLKAB
X
22
SBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
OEAB
X
L
L
BUS B
3
21
OEAB OEBA
H
H
BUS B
3
21
OEAB OEBA
L
L
BUS A
BUS A
BUS B
SCBS734A – JULY 2000 – REVISED JULY 2000
22
3
21
1
23
2
22
SBA
OEAB
H
OEBA
L
CLKAB
CLKBA
SAB
SBA
H or L
H or L
H
H
X
X
X
TRANSFER STORED DATA TO A AND/OR B
STORAGE FROM A, B, OR A AND B
Figure 1. Bus-Management Functions
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
CD74FCT652
BiCMOS OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCBS734A – JULY 2000 – REVISED JULY 2000
logic symbol†
OEBA
OEAB
CLKBA
SBA
CLKAB
SAB
A1
21
3
23
22
1
EN1 [BA]
EN2 [AB]
C4
G5
2
C6
G7
4
≥1
1
7
1
A3
A4
A5
A6
A7
A8
4D
≥1
B1
2
7
5
19
6
18
7
17
8
16
9
15
10
14
11
13
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
20
5 1
6D
A2
5
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
B2
B3
B4
B5
B6
B7
B8
CD74FCT652
BiCMOS OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCBS734A – JULY 2000 – REVISED JULY 2000
logic diagram (positive logic)
OEBA
OEAB
CLKBA
SBA
CLKAB
SAB
21
3
23
22
1
2
One of Eight Channels
1D
C1
4
A1
20
1D
B1
C1
To Seven Other Channels
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
CD74FCT652
BiCMOS OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCBS734A – JULY 2000 – REVISED JULY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
DC supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
DC input clamp current, IIK (VI < –0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
DC output clamp current, IOK (VO < –0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
DC output sink current per output pin, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
DC output source current per output pin, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA
Continuous current through VCC, ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 mA
Continuous current through GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 mA
Package thermal impedance, θJA (see Note 1): EN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 2)
MIN
MAX
UNIT
4.75
5.25
V
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
IOL
∆t/∆v
High-level input voltage
2
V
0.8
V
VCC
VCC
V
High-level output current
–15
mA
Low-level output current
64
mA
10
ns/V
Input transition rise or fall rate
0
V
TA
Operating free-air temperature
0
70
°C
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN
MAX
MIN
–1.2
V
II = –18 mA
IOH = –15 mA
4.75 V
VOL
II
IOL = 64 mA
VI = VCC or GND
4.75 V
0.55
0.55
V
5.25 V
±0.1
±1
mA
IOZ
IOS‡
VO = VCC or GND
VI = VCC or GND,
5.25 V
±0.5
±10
mA
ICC
VI = VCC or GND,
One input at 3.4 V,
Other inputs at VCC or GND
∆ICC§
Ci
VO = 0
IO = 0
5.25 V
2.4
2.4
–60
–60
mA
8
80
mA
5.25 V
1.6
1.6
mA
10
10
pF
15
pF
VI = VCC or GND
VO = VCC or GND
POST OFFICE BOX 655303
V
5.25 V
Co
15
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed 100 ms.
§ This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
6
UNIT
VIK
VOH
4.75 V
–1.2
MAX
• DALLAS, TEXAS 75265
CD74FCT652
BiCMOS OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCBS734A – JULY 2000 – REVISED JULY 2000
timing requirements over recommended operating temperature conditions (unless otherwise
noted) (see Figure 2)
MIN
MAX
UNIT
85
MHz
fclock
tw
Clock frequency
Pulse duration
CLK high or low
6
ns
tsu
th
Setup time
A before CLKAB↑ or B before CLKBA↑
4
ns
Hold time
A after CLKAB↑ or B after CLKBA↑
2
ns
switching characteristics over recommended operating temperature conditions (unless otherwise
noted) (see Figure 2)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
TA = 25°C
TYP
fmax
MIN
MAX
85
UNIT
MHz
A or B
B or A
6.8
2
9
CLKBA or CLKAB
A or B
6.8
2
9
SBA or SAB†
A or B
8.3
2
11
ten
OE
A or B
7.5
2
10
ns
tdis
OE
A or B
7.5
2
10
ns
TYP
MAX
tpd
ns
† These parameters are measured with the internal output state of the storage register opposite that of the bus input.
noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C
PARAMETER
VOL(P)
VOH(V)
Quiet output, maximum dynamic VOL
VIH(D)
VIL(D)
High-level dynamic input voltage
MIN
Quiet output, minimum dynamic VOH
V
0.5
V
2
Low-level dynamic input voltage
V
0.8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
1
V
7
CD74FCT652
BiCMOS OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCBS734A – JULY 2000 – REVISED JULY 2000
PARAMETER MEASUREMENT INFORMATION
7V
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
From Output
Under Test
Test
Point
Open
TEST
GND
CL = 50 pF
(see Note A)
500 Ω
S1
S1
Open
7V
Open
7V
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
500 Ω
Open Drain
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
90%
1.5 V
10%
3V
1.5 V
10% 0 V
90%
tr
tf
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
3V
1.5 V
Timing Input
0V
tw
tsu
3V
1.5 V
Input
1.5 V
th
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
1.5 V
Input
0V
tPLH
tPHL
1.5 V
1.5 V
VOL
tPHL
Out-of-Phase
Output
tPLZ
≈3.5 V
1.5 V
tPZH
VOH
1.5 V
VOL
1.5 V
0V
Output
Waveform 1
(see Note B)
tPLH
1.5 V
1.5 V
tPZL
VOH
In-Phase
Output
3V
Output
Control
Output
Waveform 2
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
1.5 V
V
VOH – 0.3 V OH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr and tf = 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jun-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
CD74FCT652EN
OBSOLETE
PDIP
NT
24
TBD
Call TI
Call TI
Samples Not Available
CD74FCT652M
OBSOLETE
SOIC
DW
24
TBD
Call TI
Call TI
Samples Not Available
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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