TI 5962-9324202QLA

SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS072F – JANUARY 1991 – REVISED MAY 1997
D
D
D
CLKAB
SAB
OEAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
CLKBA
SBA
OEBA
B1
B2
B3
B4
B5
B6
B7
B8
SN54ABT652A . . . FK PACKAGE
(TOP VIEW)
description
These devices consist of bus-transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided
to select either real-time or stored data for
transfer. The circuitry used for select control
eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between
stored and real-time data. A low input selects
real-time data, and a high input selects stored
data. Figure 1 illustrates the four fundamental
bus-management functions that can be
performed with the ’ABT652A.
5
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
4
A1
A2
A2
NC
A4
A5
A6
CLKBA
SBA
D
SN54ABT652A . . . JT OR W PACKAGE
SN74ABT652A . . . DB, DW, NT, OR PW PACKAGE
(TOP VIEW)
OEAB
SAB
CLKAB
NC
VCC
D
State-of-the-Art EPIC-ΙΙB  BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce)
< 1 V at VCC = 5 V, TA = 25°C
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs
19
11
12 13 14 15 16 17 18
OEBA
B1
B2
NC
B3
B4
B5
A7
A8
GND
NC
B8
B7
B6
D
NC – No internal connection
Data on the A- or B-data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions
at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control inputs. When SAB
and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all
other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last
state.
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS072F – JANUARY 1991 – REVISED MAY 1997
description (continued)
The SN54ABT652A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT652A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
DATA I/O†
INPUTS
OEAB
OEBA
CLKAB
CLKBA
L
H
H or L
L
H
↑
X
H
H
OPERATION OR FUNCTION
SAB
SBA
A1–A8
B1–B8
H or L
X
X
Input
Input
Isolation
↑
X
X
Input
Input
Store A and B data
↑
H or L
X
Input
Unspecified‡
Store A, hold B
H
↑
↑
X
X‡
X
Input
Output
Store A in both registers
L
X
H or L
↑
X
Unspecified‡
Input
Hold A, store B
L
L
↑
↑
X
X
X‡
Output
Input
Store B in both registers
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real-time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus and
stored B data to A bus
† The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
‡ Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
2
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• DALLAS, TEXAS 75265
SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
3
21
OEAB OEBA
L
L
1
23
2
CLKAB CLKBA SAB
X
X
X
BUS B
BUS A
BUS A
BUS B
SCBS072F – JANUARY 1991 – REVISED MAY 1997
22
SBA
L
3
21
OEAB OEBA
H
H
21
OEBA
H
X
H
1
23
2
CLKAB CLKBA SAB
↑
X
↑
X
↑
↑
X
X
X
2
SAB
L
22
SBA
X
BUS B
BUS A
BUS A
3
OEAB
X
L
L
23
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
1
CLKAB
X
22
3
21
1
23
2
22
SBA
OEAB
H
OEBA
L
CLKAB
CLKBA
SAB
SBA
H or L
H or L
H
H
X
X
X
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
Figure 1. Bus-Management Functions
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS072F – JANUARY 1991 – REVISED MAY 1997
logic symbol†
OEBA
OEAB
CLKBA
SBA
CLKAB
SAB
A1
21
3
23
22
1
EN1 [BA]
EN2 [AB]
C4
G5
2
C6
G7
4
≥1
5
1
6D
4D
20
B1
5 1
7
≥1
2
1 7
A2
A3
A4
A5
A6
A7
A8
5
19
6
18
7
17
8
16
9
15
10
14
11
13
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
4
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• DALLAS, TEXAS 75265
B2
B3
B4
B5
B6
B7
B8
SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS072F – JANUARY 1991 – REVISED MAY 1997
logic diagram (positive logic)
OEBA
OEAB
CLKBA
SBA
CLKAB
SAB
21
3
23
22
1
2
One of Eight Channels
1D
C1
A1
4
20
B1
1D
C1
To Seven Other Channels
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS072F – JANUARY 1991 – REVISED MAY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT652A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT652A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
recommended operating conditions (see Note 3)
SN54ABT652A
MIN
MAX
4.5
5.5
4.5
5.5
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
VCC
–24
Low-level output current
48
∆t/∆v
Input transition rise or fall rate
2
2
0.8
Input voltage
0
Outputs enabled
TA
Operating free-air temperature
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
6
MAX
VCC
VIH
High-level input voltage
SN74ABT652A
MIN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0
5
–55
125
–40
UNIT
V
V
0.8
V
VCC
–32
V
mA
64
mA
5
ns/V
85
°C
SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS072F – JANUARY 1991 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
VCC = 5 V,
VCC = 4
4.5
5V
VOL
VCC = 4
4.5
5V
MIN
SN54ABT652A
MIN
–1.2
MAX
SN74ABT652A
MIN
–1.2
MAX
–1.2
2.5
2.5
2.5
IOH = –3 mA
IOH = –24 mA
3
3
3
2
2
IOH = –32 mA
IOL = 48 mA
2*
IOL = 64 mA
0.55
0.55*
0.55
mV
±1
±1
±100
±100
±100
50
µA
VI = VCC or GND
IOZH‡
IOZL‡
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.5 V
50**
10
–50**
–10
Ioff
VCC = 0,
VCC = 5.5 V,
VO = 5.5 V
VI or VO ≤ 4.5 V
±100
IO§
VCC = 5.5 V,
ICC
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
VO = 2.5 V
Outputs high
ICEX
Outputs high
50
–50
–100
Outputs low
Outputs disabled
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
∆ICC¶
Ci
Control inputs
Cio
A or B ports
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
V
±1
VCC = 5
5.5
5 V,
V
A or B ports
V
V
100
Control inputs
UNIT
2
0.55
Vhys
II
TA = 25°C
TYP†
MAX
–180
50
–50
–180
–50
µA
–50
µA
±100
µA
50
µA
–180
mA
250
250
250
µA
30
30
30
mA
250
250
250
µA
1.5
1.5
1.5
mA
7
pF
12
pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
** These limits apply only to the SN74ABT652A.
† All typical values are at VCC = 5 V.
‡ The parameters IOZH and IOZL include the input leakage current.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS072F – JANUARY 1991 – REVISED MAY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN54ABT652A
VCC = 5 V,
TA = 25°C
MIN
MAX
125
MIN
MAX
0
125
UNIT
fclock
tw
Clock frequency
0
Pulse duration, CLK high or low
4
4
ns
tsu
th
Setup time, A or B before CLKAB↑ or CLKBA↑
3
3.5
ns
1.5
1.5
ns
Hold time, A or B after CLKAB↑ or CLKBA↑
MHz
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN74ABT652A
VCC = 5 V,
TA = 25°C
8
MIN
MAX
0
125
UNIT
MIN
MAX
fclock
tw
Clock frequency
0
125
Pulse duration, CLK high or low
4
4
ns
tsu
th
Setup time, A or B before CLKAB↑ or CLKBA↑
3
3
ns
Hold time, A or B after CLKAB↑ or CLKBA↑
0
0
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MHz
SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS072F – JANUARY 1991 – REVISED MAY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 2)
SN54ABT652A
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
FROM
(INPUT)
TO
(OUTPUT)
CLK
B or A
A or B
B or A
SAB or SBA†
B or A
OEBA
A
OEBA
A
OEAB
B
OEAB
B
VCC = 5 V,
TA = 25°C
MIN
MAX
MIN
TYP
125
200
2.2
4
5.1
1.7
5.9
1.7
4
5.1
1.7
5.9
1.5
3
4.8
1
5
1.5
3.3
4.6
1
5.6
1.5
4
5.5
1.5
6.8
1.5
3.6
4.9
1.5
6.2
2
3.6
5.4
2
6.8
3
5.7
7.7
3
9.2
1.5
3.2
5.8
1
7.5
1.5
3
4.3
1
4.6
2
4.3
6.1
2
7.8
3
5.5
7.4
3
8.9
1.5
3.3
6
1
8
1.5
6.8
UNIT
MAX
125
tPLZ
1.5
3.4
5
† These parameters are measured with the internal output state of the storage register opposite that of the bus input.
MHz
ns
ns
ns
ns
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 2)
SN74ABT652A
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
FROM
(INPUT)
TO
(OUTPUT)
CLK
B or A
A or B
B or A
SAB or SBA†
B or A
OEBA
A
OEBA
A
OEAB
B
OEAB
B
VCC = 5 V,
TA = 25°C
MIN
MIN
TYP
125
200
2.2
4
5.1
2.2
5.6
1.7
4
5.1
1.7
5.6
1.5
3
4.3
1.5
4.8
1.5
3.3
4.6
1.5
5.4
1.5
4
5.1
1.5
6.5
1.5
3.6
4.9
1.5
5.9
2
3.6
4.6
2
5.8
3
5.7
6.8
3
8.5
1.5
3.2
4.5
1.5
5
1.5
3
3.8
1.5
4.1
2
4.3
6.1
2
6.5
3
5.5
6.5
3
7.4
1.5
3.3
4.5
1.5
5.5
1.5
5.1
• DALLAS, TEXAS 75265
UNIT
MAX
125
tPLZ
1.5
3.4
4.4
† These parameters are measured with the internal output state of the storage register opposite that of the bus input.
POST OFFICE BOX 655303
MAX
MHz
ns
ns
ns
ns
ns
ns
ns
9
SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS072F – JANUARY 1991 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
LOAD CIRCUIT
3V
Timing Input
1.5 V
0V
tw
tsu
3V
Input
1.5 V
1.5 V
th
3V
Data Input
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
VOH
1.5 V
Output
1.5 V
VOL
VOH
Output
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLH
tPHL
1.5 V
tPZL
tPHL
tPLH
3V
Output
Control
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
tPZH
3.5 V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
10
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
5962-9324202Q3A
ACTIVE
LCCC
FK
28
1
TBD
Call TI
Level-NC-NC-NC
5962-9324202QKA
ACTIVE
CFP
W
24
1
TBD
Call TI
Level-NC-NC-NC
1
TBD
Call TI
Level-NC-NC-NC
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
5962-9324202QLA
ACTIVE
CDIP
JT
24
SN74ABT652ADBLE
OBSOLETE
SSOP
DB
24
SN74ABT652ADBR
ACTIVE
SSOP
DB
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT652ADBRE4
ACTIVE
SSOP
DB
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT652ADW
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT652ADWE4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT652ADWR
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT652ADWRE4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT652ANSR
ACTIVE
SO
NS
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT652ANSRE4
ACTIVE
SO
NS
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT652ANT
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74ABT652ANTE4
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SNJ54ABT652AFK
ACTIVE
LCCC
FK
28
1
TBD
Call TI
Level-NC-NC-NC
SNJ54ABT652AJT
ACTIVE
CDIP
JT
24
1
TBD
Call TI
Level-NC-NC-NC
SNJ54ABT652AW
ACTIVE
CFP
W
24
1
TBD
Call TI
Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
13
24
B
1
24
28
A MAX
1.280
(32,51)
1.460
(37,08)
A MIN
1.240
(31,50)
1.440
(36,58)
B MAX
0.300
(7,62)
0.291
(7,39)
B MIN
0.245
(6,22)
0.285
(7,24)
DIM
12
0.070 (1,78)
0.030 (0,76)
0.100 (2,54) MAX
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP007 – OCTOBER 1994
W (R-GDFP-F24)
CERAMIC DUAL FLATPACK
0.375 (9,53)
0.340 (8,64)
Base and Seating Plane
0.006 (0,15)
0.004 (0,10)
0.090 (2,29)
0.045 (1,14)
0.045 (1,14)
0.026 (0,66)
0.395 (10,03)
0.360 (9,14)
0.360 (9,14)
0.240 (6,10)
1
0.360 (9,14)
0.240 (6,10)
24
0.019 (0,48)
0.015 (0,38)
0.050 (1,27)
0.640 (16,26)
0.490 (12,45)
0.030 (0,76)
0.015 (0,38)
12
13
30° TYP
1.115 (28,32)
0.840 (21,34)
4040180-5 / B 03/95
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
Index point is provided on cap for terminal identification only.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI004 – OCTOBER 1994
NT (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
PINS **
A
24
28
A MAX
1.260
(32,04)
1.425
(36,20)
A MIN
1.230
(31,24)
1.385
(35,18)
B MAX
0.310
(7,87)
0.315
(8,00)
B MIN
0.290
(7,37)
0.295
(7,49)
DIM
24
13
0.280 (7,11)
0.250 (6,35)
1
12
0.070 (1,78) MAX
B
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0°– 15°
0.010 (0,25) M
0.010 (0,25) NOM
4040050 / B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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