TI TCA9517A

TCA9517A
www.ti.com
SCPS245A – DECEMBER 2012 – REVISED APRIL 2013
LEVEL-TRANSLATING I2C BUS REPEATER
Check for Samples: TCA9517A
FEATURES
1
•
•
•
•
•
•
•
•
•
Two-Channel Bidirectional Buffer
I2C Bus and SMBus Compatible
Operating Supply Voltage Range of
0.9 V to 5.5 V on A Side
Operating Supply Voltage Range of
2.7 V to 5.5 V on B Side
Voltage-Level Translation From 0.9 V to 5.5 V
and 2.7 V to 5.5 V
Footprint and Function Replacement for
PCA9515B
Active-High Repeater-Enable Input
Open-Drain I2C I/O
5.5-V Tolerant I2C and Enable Input Support
•
•
•
•
•
•
Mixed-Mode Signal Operation
Lockup-Free Operation
Accommodates Standard Mode and Fast Mode
I2C Devices and Multiple Masters
Powered-Off High-Impedance I2C Pins
400-kHz Fast I2C Bus
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 5500-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DGK PACKAGE
(TOP VIEW)
VCCA
SCLA
SDAA
GND
1
2
3
4
VCCB
SCLB
SDAB
EN
8
7
6
5
DESCRIPTION/ORDERING INFORMATION
This dual bidirectional I2C buffer is operational at 2.7 V to 5.5 V.
The TCA9517A is a BiCMOS integrated circuit intended for I2C bus and SMBus systems. It can provide
bidirectional voltage-level translation (up-translation/down-translation) between low voltages (down to 0.9 V) and
higher voltages (2.7 V to 5.5 V) in mixed-mode applications. This device enables I2C and similar bus systems to
be extended, without degradation of performance even during level shifting.
The TCA9517A buffers both the serial data (SDA) and the serial clock (SCL) signals on the I2C bus, thus
allowing two buses of 400-pF bus capacitance to be connected in an I2C application. This device can also be
used to isolate two halves of a bus for voltage and capacitance.
The TCA9517A has two types of drivers—A-side drivers and B-side drivers. All inputs and I/Os are overvoltage
tolerant to 5.5 V, even when the device is unpowered (VCCB and/or VCCA = 0 V).
The TCA9517A offers a higher contention level threshold, VILC, than the TCA9517 and can be used in
applications where a larger input logic low is required on the B-side.
ORDERING INFORMATION
PACKAGES (1)
TA
–40°C to 85°C
(1)
(2)
VSSOP – DGK
(2)
Tape and reel
ORDERABLE PART NUMBER
TCA9517ADGKR
TOP-SIDE MARKING
BSK
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
TCA9517A
SCPS245A – DECEMBER 2012 – REVISED APRIL 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The B-side drivers operate from 2.7 V to 5.5 V. The output low level for this internal buffer is approximately 0.5 V,
but the input voltage must be 70 mV or more below the output low level when the output internally is driven low.
The higher-voltage low signal is called a buffered low. When the B-side I/O is driven low internally, the low is not
recognized as a low by the input. This feature prevents a lockup condition from occurring when the input low
condition is released.
This type of design on the B side prevents it from being used in series with the PCA9515B and another
TCA9517A (B side). This is because these devices do not recognize buffered low signals as a valid low and do
not propagate it as a buffered low again.
The A-side drivers operate from 0.9 V to 5.5 V and drive more current. They do not require the buffered low
feature (or the static offset voltage). This means that a low signal on the B side translates to a nearly 0-V low on
the A side, which accommodates smaller voltage swings of lower-voltage logic. The output pulldown on the
A side drives a hard low, and the input level is set at 0.3 VCCA to accommodate the need for a lower low level in
systems where the low-voltage-side supply voltage is as low as 0.9 V.
The A side of two or more TCA9517As can be connected together to allow a star topography, with the A side on
the common bus. Also, the A side can be connected directly to any other buffer with static- or dynamic-offset
voltage. Multiple TCA9517As can be connected in series, A side to B side, with no buildup in offset voltage and
with only time-of-flight delays to consider. Because of the buffered low voltage from the B side, the TCA9517
cannot be connected B side to B side or the B side cannot be connected to a device with rise time accelerators.
The TCA9517A drivers are enabled when VCCA is above 0.8 V and VCCB is above 2.5 V.
The TCA9517A has an active-high enable (EN) input with an internal pullup to VCCB, which allows the user to
select when the repeater is active. This can be used to isolate a badly behaved slave on power-up reset. The EN
input should change state only when the global bus and repeater port are in an idle state, to prevent system
failures.
The TCA9517A includes a power-up circuit that keeps the output drivers turned off until VCCB is above 2.5 V and
the VCCA is above 0.8 V. VCCB and VCCA can be applied in any sequence at power up. After power up and with
the EN high, a low level on the A side (below 0.3 VCCA) turns the corresponding B-side driver (either SDA or
SCL) on and drives the B side down to approximately 0.5 V. When the A side rises above 0.3 VCCA, the B-side
pulldown driver is turned off and the external pullup resistor pulls the pin high. When the B side falls first and
goes below 0.3 VCCB, the A-side driver is turned on and the A side pulls down to 0 V. The B-side pulldown is not
enabled unless the B-side voltage goes below 0.4 V. If the B-side low voltage does not go below 0.5 V, the Aside driver turns off when the B-side voltage is above 0.7 VCCB. If the B-side low voltage goes below 0.4 V, the Bside pulldown driver is enabled, and the B side is able to rise to only 0.5 V until the A side rises above 0.3 VCCA.
VCCA is only used to provide the 0.3 VCCA reference to the A-side input comparators and for the power-gooddetect circuit. The TCA9517A logic and all I/Os are powered by the VCCB pin.
As with the standard I2C system, pullup resistors are required to provide the logic-high levels on the buffered
bus. The TCA9517A has standard open-drain configuration of the I2C bus. The size of these pullup resistors
depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to
work with Standard mode and Fast mode I2C devices in addition to SMBus devices. Standard mode I2C devices
only specify 3 mA in a generic I2C system, where Standard mode devices and multiple masters are possible.
Under certain conditions, higher termination currents can be used.
2
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SCPS245A – DECEMBER 2012 – REVISED APRIL 2013
TERMINAL FUNCTIONS
NO.
NAME
DESCRIPTION
1
VCCA
A-side supply voltage (0.9 V to 5.5 V)
2
SCLA
Serial clock bus, A side. Connect to VCCA through a pullup resistor.
3
SDAA
Serial data bus, A side. Connect to VCCA through a pullup resistor.
4
GND
Supply ground
5
EN
6
SDAB
Serial data bus, B side. Connect to VCCB through a pullup resistor.
7
SCLB
Serial clock bus, B side. Connect to VCCB through a pullup resistor.
8
VCCB
B-side and device supply voltage (2.7 V to 5.5 V)
Active-high repeater enable input
Table 1. FUNCTION TABLE
INPUT
EN
FUNCTION
L
Outputs disabled
H
SDAA = SDAB
SCLA = SCLB
Figure 1. FUNCTIONAL BLOCK DIAGRAM
VCCA
VCCB
1
8
6
3
SDAA
SDAB
7
2
SCLA
SCLB
VCCB
5
Pullup
Resistor
EN
4
GND
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SCPS245A – DECEMBER 2012 – REVISED APRIL 2013
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCCB
Supply voltage range
–0.5
7
V
VCCA
Supply voltage range
–0.5
7
V
VI
Enable input voltage range (2)
–0.5
7
V
VI/O
I2C bus voltage range (2)
–0.5
7
V
IIK
Input clamp current
VI < 0
–50
IOK
Output clamp current
VO < 0
–50
Continuous output current
IO
Continuous current through VCC or GND
Tstg
(1)
(2)
Storage temperature range
–65
mA
±50
mA
±100
mA
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
THERMAL IMPEDANCE
over operating free-air temperature range (unless otherwise noted)
MIN
Package thermal impedance (1)
θJA
(1)
DGK package
MAX
UNIT
172
°C/W
UNIT
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS
VCCA
Supply voltage, A-side bus
VCCB
Supply voltage, B-side bus
VIH
VIL
High-level input voltage
Low-level input voltage
IOL
Low-level output current
TA
Operating free-air temperature
(1)
(2)
4
MIN
MAX
0.9 (1)
5.5
V
V
2.7
5.5
SDAA, SCLA
0.7 × VCCA
5.5
SDAB, SCLB
0.7 × VCCB
5.5
EN
0.7 × VCCB
5.5
SDAA, SCLA
0.3 × VCCA
SDAB, SCLB (2)
0.3 × VCCB
EN
0.3 × VCCB
–40
V
V
6
mA
85
°C
Low-level supply voltage
VIL specification is for the first low level seen by the SDAB and SCLB lines. VILc is for the second and subsequent low levels seen by the
SDAB and SCLB lines. See VILC AND PULL-UP RESISTOR SIZING for VILC application information
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ELECTRICAL CHARACTERISTICS
VCCB = 2.7 V to 5.5 V, GND = 0 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
Input clamp voltage
Low-level output
voltage
VOL
MIN
II = –18 mA
2.7 V to 5.5 V
SDAB, SCLB
IOL = 100 μA or 6 mA,
VILA = VILB = 0 V
2.7 V to 5.5 V
SDAA, SCLA
IOL = 6 mA
SDAB, SCLB
guaranteed by design
VOL – VILc
Low-level input voltage
below low-level output
voltage
VILC
SDA and SCL low-level
SDAB, SCLB
input voltage contention
ICC
VCCB
II
Input leakage current
SDAA, SCLA
2.7 V to 5.5 V
0.45
5.5 V
IOH
CI
CIO
High-level output
leakage current
1.5
5
1.5
5
3
5
Input capacitance
Input/output
capacitance
±1
VI = 0.2 V
10
VI = 0.2 V
±1
2.7 V to 5.5 V
10
SDAA, SCLA
VO = 3.6 V
EN
VI = 3 V or 0 V
SCLA, SCLB
VI = 3 V or 0 V
mA
mA
μA
±1
VI = 0.2 V
SDAB, SCLB
V
VI = VCCB
VI = VCCB
V
mV
1
VI = VCCB
EN
V
0.2
In contention,
SDAA = SCLA = GND and
SDAB = SCLB = GND
SDAB, SCLB
–1.2
0.1
70
Both channels low,
SDAA = SCLA = GND and
SDAB = SCLB = open
Quiescent supply current
UNIT
0.6
Both channels low,
SDAA = SCLA = GND and
SDAB = SCLB = open, or
SDAA = SCLA = open and
SDAB = SCLB = GND
Quiescent supply current for VCCA
MAX
0.52
2.7 V to 5.5 V
Both channels high,
SDAA = SCLA = VCCA and
SDAB = SCLB = VCCB and
EN = VCCB
ICC
0.45
TYP
–10
10
2.7 V to 5.5 V
SDAA, SDAB VI = 3 V or 0 V
–30
10
3.3 V
6
10
3.3 V
8
13
0V
7
11
3.3 V
8
13
0V
7
11
μA
pF
pF
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted)
MIN
tsu
th
(1)
Setup time, EN high before Start condition (1)
Hold time, EN high after Stop condition
(1)
MAX
UNIT
100
ns
100
ns
EN should change state only when the global bus and the repeater port are in an idle state.
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I2C INTERFACE TIMING REQUIREMENTS
VCCB = 2.7 V to 5.5 V, GND = 0 V, TA = –40°C to 85°C (unless otherwise noted) (1) (2)
PARAMETER
tPLZ
Propagation delay
FROM
(INPUT)
TO
(OUTPUT)
SDAB, SCLB (4)
(see Figure 5)
SDAA, SCLA (4)
(see Figure 5)
80
141
350
SDAA, SCLA (5)
(see Figure 4)
SDAB, SCLB (5)
(see Figure 4)
25
74
110
VCCA ≤ 2.7 V
(see Figure 3)
30
76 (6)
110
VCCA ≥ 3 V
(see Figure 3)
10
86
230
60
107
230
VCCA ≤ 2.7 V
(see Figure 4)
10
12
15
VCCA ≥ 3 V
(see Figure 4)
40
42
45
110
125
140
VCCA ≤ 2.7 V
(see Figure 4)
1
52 (6)
105
VCCA ≥ 3 V
(see Figure 4)
20
67
175
30
48
90
SDAB, SCLB
tPZL
SDAA, SCLA
Propagation delay
(5)
SDAA, SCLA
(see Figure 4)
Transition time
80%
SDAB, SCLB
(see Figure 4)
20%
B side to A side
Transition time
80%
20%
A side to B side
(see Figure 3)
(1)
(2)
(3)
(4)
(5)
(6)
6
TYP (3) MAX UNIT
ns
A side to B side
(see Figure 3)
tTHL
MIN
ns
(5)
B side to A side
tTLH
TEST CONDITIONS
ns
ns
Times are specified with loads of 1.35-kΩ pullup resistance and 50-pF load capacitance on the B side and 167-Ω pullup and 57-pF load
capacitance on the A side. Different load resistance and capacitance alter the RC time constant, thereby changing the propagation delay
and transition times.
Pullup voltages are VCCA on the A side and VCCB on the B side.
Typical values were measured with VCCA = VCCB = 3.3 V at TA = 25°C, unless otherwise noted.
The tPLH delay data from B to A side is measured at 0.4 V on the B side to 0.5 VCCA on the A side when VCCA is less than 2 V, and
1.5 V on the A side if VCCA is greater than 2 V.
The proportional delay data from A to B side is measured at 0.3 VCCA on the A side to 1.5 V on the B side.
Typical value measured with VCCA = 2.7 V at TA = 25°C
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PARAMETER MEASUREMENT INFORMATION
VCC
VIN
RL
(see Note A)
VOUT
PULSE
GENERATOR
VCC
S1
DUT
GND
CL = 57 pF
(see Note C)
RT
(see Note B)
TEST
S1
tPLZ/tPZL
VCC
TEST CIRCUIT FOR OPEN-DRAIN OUTPUT
A.
RL = 167 Ω (0.9 V to 2.7 V) and RL = 450 Ω (3.0 V to 5.5 V) on the A side and 1.35 kΩ on the B side
B.
RT termination resistance should be equal to ZOUT of pulse generators.
C.
CL includes probe and jig capacitance.
D.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
slew rate ≥ 1 V/ns.
E.
The outputs are measured one at a time, with one transition per measurement.
F.
tPLH and tPHL are the same as tpd.
G.
tPLZ and tPHZ are the same as tdis.
H.
tPZL and tPZH are the same as ten.
Figure 2. Test Circuit
3V
INPUT
1.5 V
1.5 V
0.1 V
tPZL
tPLZ
1.2 V
80%
80%
OUTPUT
0.6 V
20%
0.6 V
20%
VOL
tTHL
tTLH
Figure 3. Waveform 1 – Propagation Delay and Transition Times for B Side to A Side
VCCA
VCCA
INPUT
0.3 VCCA
0.3 VCCA
tPZL
tPLZ
3V
80%
OUTPUT
1.5 V
20%
80%
1.5 V
20%
Figure 4. Waveform 2 – Propagation Delay and Transition Times for A Side to B Side
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PARAMETER MEASUREMENT INFORMATION (continued)
INPUT
SDAB, SCLB
0.4 V
50% is VCCA is less than 2 V
1.5 V if VCCA is greater than 2 V
OUTPUT
SCLA, SDAA
tPLH
Figure 5. Waveform 3
8
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APPLICATION INFORMATION
A typical application is shown in Figure 6. In this example, the system master is running on a 3.3-V I2C bus, and
the slave is connected to a 1.2-V bus. Both buses run at 400 kHz. Master devices can be placed on either bus.
The TCA9517A is 5-V tolerant, so it does not require any additional circuitry to translate between 0.9-V to 5.5-V
bus voltages and 2.7-V to 5.5-V bus voltages.
When the A side of the TCA9517A is pulled low by a driver on the I2C bus, a comparator detects the falling edge
when it goes below 0.3 VCCA and causes the internal driver on the B side to turn on, causing the B side to pull
down to about 0.5 V. When the B side of the TCA9517A falls, first a CMOS hysteresis-type input detects the
falling edge and causes the internal driver on the A side to turn on and pull the A-side pin down to ground. In
order to illustrate what would be seen in a typical application, refer to Figure 8 and Figure 9. If the bus master in
Figure 6 were to write to the slave through the TCA9517A, waveforms shown in Figure 8 would be observed on
the A bus. This looks like a normal I2C transmission, except that the high level may be as low as 0.9 V, and the
turn on and turn off of the acknowledge signals are slightly delayed.
On the B-side bus of the TCA9517A, the clock and data lines would have a positive offset from ground equal to
the VOL of the TCA9517A. After the eighth clock pulse, the data line is pulled to the VOL of the slave device,
which is very close to ground in this example. At the end of the acknowledge, the level rises only to the low level
set by the driver in the TCA9517A for a short delay, while the A-bus side rises above 0.3 VCCA and then
continues high.
1.2 V
3.3 V
10 kW
BUS
MASTER
400 kHz
10 kW
VCCB
10 kW
VCCA
10 kW
SDA
SDAB SDAA
SDA
SCL
SCLB SCLA
TCA9517A
SCL
SLAVE
400 kHz
EN
BUS B
BUS A
Figure 6. Typical Application
VILC AND PULL-UP RESISTOR SIZING
For the TCA9517A to function correctly, all devices on the B-side must be able to pull the B-side below the
voltage input low contention level (VILC). This means that the VOL of any device on the B-side must be below
0.45V.
VOL of a device can be adjusted by changing the IOL through the device which is set by the pull-up resistance
value. The pull-up resistance on the B-side must be carefully selected to ensure that logic levels will be
transferred correctly to the A-side.
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VCCA
10 kW
VCCB
10 kW
10 kW
10 kW
SDA
SDAA SDAB
SDA
SCL
SCLA SCLB
SCL
SLAVE
400 kHz
TCA9517A
BUS
MASTER
EN
10 kW
10 kW
SDAA SDAB
SDA
SCLA SCLB
SCL
TCA9517A
SLAVE
400 kHz
EN
10 kW
10 kW
SDAA SDAB
SDA
SCLA SCLB
SCL
SLAVE
400 kHz
TCA9517A
EN
Figure 7. Typical Star Application
Multiple TCA9517A A sides can be connected in a star configuration, allowing all nodes to communicate with
each other.
VCCB
10 kW
10 kW
10 kW
10 kW
10 kW
10 kW
10 kW
10 kW
SDA
SDAA SDAB
SDAA SDAB
SDAA SDAB
SDA
SCL
SCLA SCLB
SCLA SCLB
SCLA SCLB
SCL
TCA9517A
EN
TCA9517A
EN
TCA9517A
EN
BUS
MASTER
SLAVE
400 kHz
Figure 8. Typical Series Application
Multiple TCA9517As can be connected in series as long as the A side is connected to the B side. I2C bus slave
devices can be connected to any of the bus segments. The number of devices that can be connected in series is
limited by repeater delay/time-of-flight considerations on the maximum bus speed requirements.
10
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9th CLOCK PULSE — ACKNOWLEDGE
SCL
SDA
Figure 9. Bus A (0.9-V to 5.5-V Bus) Waveform
9th CLOCK PULSE — ACKNOWLEDGE
SCL
SDA
VOL OF TCA9517A
VOL OF SLAVE
Figure 10. Bus B (2.7-V to 5.5-V Bus) Waveform
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REVISION HISTORY
Changes from Original (December 2012) to Revision A
•
12
Page
Updated the TOP-SIDE MARKING column of the ORDERING INFORMATION TABLE. ................................................... 1
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PACKAGE OPTION ADDENDUM
www.ti.com
22-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
TCA9517ADGKR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VSSOP
DGK
8
2500
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS CU NIPDAUAG
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Level-1-260C-UNLIM
(4/5)
-40 to 85
BSK
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TCA9517ADGKR
Package Package Pins
Type Drawing
VSSOP
DGK
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
3.4
1.4
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TCA9517ADGKR
VSSOP
DGK
8
2500
364.0
364.0
27.0
Pack Materials-Page 2
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