19-0474; Rev 6; 3/11 Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators The MAX9972 four-channel, ultra-low-power, pin-electronics IC includes, for each channel, a three-level pin driver, a window comparator, a passive load, and force-and-sense Kelvin-switched parametric measurement unit (PMU) connections. The driver features a -2.2V to +5.2V voltage range, includes high-impedance and active-termination (3rd-level drive) modes, and is highly linear even at low voltage swings. The window comparator features 500MHz equivalent input bandwidth and programmable output voltage levels. The passive load provides pullup and pulldown voltages to the device-under-test (DUT). Low-leakage, high-impedance, and terminate controls are operational configurations that are programmed through a 3-wire, low-voltage, CMOS-compatible serial interface. High-speed PMU switching is realized through dedicated digital control inputs. This device is available in an 80-pin, 12mm x 12mm body, 1.0mm pitch TQFP with an exposed 6mm x 6mm die pad on the bottom of the package for efficient heat removal. The MAX9972 is specified to operate over the 0°C to +70°C commercial temperature range, and features a die temperature monitor output. Applications Features ♦ Small Footprint—Four Channels in 0.3in2 ♦ Low-Power Dissipation: 325mW/Channel (typ) ♦ High Speed: 300Mbps at 3VP-P ♦ -2.2V to +5.2V Operating Range ♦ Active Termination (3rd-Level Drive) ♦ Integrated PMU Switches ♦ Passive Load ♦ Low-Leak Mode: 20nA (max) ♦ Low Gain and Offset Error Ordering Information PART TEMP RANGE PINPACKAGE HEAT EXTRACTION MAX9972ACCS+ 0°C to +70°C 80 TQFP-EP* Bottom +Denotes a lead(Pb)-free/RoHs-compliant package. *EP = Exposed pad. NAND Flash Testers DRAM Probe Testers Low-Cost Mixed-Signal/System-on-Chip (SoC) Testers Active Burn-In Systems Structural Testers Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9972 General Description MAX9972 Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators ABSOLUTE MAXIMUM RATINGS VDD to GND ...........................................................-0.3V to +9.4V VSS to GND..........................................................-6.25V to +0.3V VDD to VSS ........................................................................+15.7V VL to GND.................................................................-0.3V to +5V DHV_, DTV_, DLV_, LDV_, DUT_ to GND ...................VSS to VDD DATA_, RCV_ ...........................................................-0.3V to +5V CHV_, CLV_, CMPH_, CMPL_, COMPHI, COMPLO to GND.....................................................VSS to VDD FORCE_, SENSE_, PMU_ to GND ..............................VSS to VDD LD, DIN, SCLK, CS to GND......................................-0.3V to +5V DUT_, CMPH_, CMPL_ Short-Circuit Duration ...........Continuous DHV_, DLV_, DTV_ to Each Other ..............................VSS to VDD CHV_, CLV_ to DUT_ ..................................................VSS to VDD DOUT to GND...........................................................-0.3V to +5V TEMP Short-Circuit Duration ......................................Continuous FORCE_ Path Switch Current..............................................50mA SENSE_ Path Switch Current .............................................1.5mA Continuous Power Dissipation (TA = +70°C) 80-Pin TQFP-EP (derate 35.7mW/°C above +70°C) ....2857mW Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +8V, VSS = -5V, VL = +3V, VCOMPHI = +1V, VCOMPLO = 0V, VLDV_ = 0V, LOAD EN LOW = LOAD EN HIGH = 0, TJ = +75°C. All temperature coefficients measured at TJ = +50°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS +5.2 V 1 1.005 V/V DRIVER (all specifications apply when DUT_ = DHV_, DUT_ = DTV_, or DUT_ = DLV_) DC CHARACTERISTICS Voltage Range -2.2 Gain Measured at 0V and 3V 0.995 Gain Temperature Coefficient 50 Offset VDHV_ = 2V, VDLV_ = 0V, VDTV_ = 1V ppm/°C ±10 Offset Temperature Coefficient ±250 Power-Supply Rejection Ratio PSRR VDD, VSS independently varied over full range Maximum DC Drive Current IDUT_ All drive mode specs valid over this range -40 DC Output Resistance IDUT_ = ±10mA (Note 2) 48.5 DC Output Resistance Variation IDUT_ = -40mA to +40mA DHV_ to DLV_ and DTV_: VDLV_ = VDTV_ = +1.5V, VDHV_ = -2.2V, +5.2V 5 DLV_ to DHV_ and DTV_: VDHV_ = VDTV_ = +1.5V, VDLV_ = -2.2V, +5.2V 5 DTV_ to DHV_ and DLV_: VDHV_ = VDLV_ = +1.5V, VDTV_ = -2.2V, +5.2V 5 DC Crosstalk Linearity Error 2 49.5 mV µV/°C 18 mV/V +40 mA 50.5 _ 2.5 _ mV 0 to 3V (Note 3) ±5 mV Full range (Note 4) ±15 mV _______________________________________________________________________________________ Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators (VDD = +8V, VSS = -5V, VL = +3V, VCOMPHI = +1V, VCOMPLO = 0V, VLDV_ = 0V, LOAD EN LOW = LOAD EN HIGH = 0, TJ = +75°C. All temperature coefficients measured at TJ = +50°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AC CHARACTERISTICS (Note 5) Dynamic Output Current Drive-Mode Overshoot, Undershoot, and Preshoot Term-Mode Spike High-Impedance-Mode Spike (Note 1) 40 mA 5% +10 200mV to 4VP-P swing (Note 6) VDHV_ = VDTV_ = 1V, VDLV_ = 0V 25 VDLV_ = VDTV_ = 0V, VDHV_ = 1V 25 VDLV_ = -1V, VDHV_ = 0V 25 VDLV_ = 0V, VDHV_ = 1V 25 Propagation Delay, Data to Output 1.6 2.6 mV mV mV 4.2 ns Prop-Delay Temperature Coefficient 10 ps/°C Prop-Delay Match, tLH vs. tHL 30 ps Prop-Delay Skew, Drivers Within Package 150 ps Prop-Delay Change vs. Pulse Width Relative to 12.5ns pulse 3VP-P, 40MHz, PW = 4ns to 21ns 20 ps 1VP-P, 40MHz, PW = 2.5ns to 23.5ns 90 Prop-Delay Change vs. CommonMode Voltage 1VP-P, VDLV_ = 0 to 3V, relative to delay at VDLV_ = 1V 80 ps Prop Delay, Data to High Impedance VDHV_ = +1.5V, VDLV_ = -1.5V, both directions 1.8 ns Prop Delay, Data to Term VDHV_ = +1.5V, VDLV_ = -1.5V, VDTV_ = 0V, both directions 1.6 ns mV Minimum Voltage Swing (Note 7) 25 VDHV_ = 0.2V, VDLV_ = 0V, 20% to 80% 0.7 VDHV_ = 1V, VDLV_ = 0V, 20% to 80% 0.7 VDHV_ = 3V, VDLV_ = 0V, 10% to 90% Rise/Fall Time Rise/Fall-Time Matching Minimum Pulse Width (Note 8) 1.5 2.0 VDHV_ = 4V, VDLV_ = 0V, RL = 500_, 10% to 90% 2.6 VDHV_ = 5V, VDLV_ = 0V, RL = 500_, 10% to 90% 3.4 VDHV_ = 1V to 5V ±5 200mV, VDHV_ = 0.2V, VDLV_ = 0V 1.8 1V, VDHV_ = 1V, VDLV_ = 0V 2.4 3V, VDHV_ = 3V, VDLV_ = 0V 3.3 2.5 ns % ns _______________________________________________________________________________________ 3 MAX9972 ELECTRICAL CHARACTERISTICS (continued) MAX9972 Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators ELECTRICAL CHARACTERISTICS (continued) (VDD = +8V, VSS = -5V, VL = +3V, VCOMPHI = +1V, VCOMPLO = 0V, VLDV_ = 0V, LOAD EN LOW = LOAD EN HIGH = 0, TJ = +75°C. All temperature coefficients measured at TJ = +50°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN Differential Input Voltage VDUT_ - VCHV_, VDUT_ - VCLV_ Hysteresis VCHV_ = VCLV_ = 1.5V Input Offset Voltage VDUT_ = 1.5V (VCOMPHI = 0.8V, VCOMPLO = 0.2V) TYP MAX UNITS -2.2 +5.2 V -7.4 +7.4 V COMPARATOR (Note 9) DC CHARACTERISTICS (driver in high-impedance mode) Input Voltage Range 8 ±10 Input Offset Temperature Coefficient Common-Mode Rejection Ratio 25 CMRR VDUT_ = 0 and 3V dB ±5 VDUT_ = -2.2V, +5.2V PSRR mV µV/°C 60 VDUT_ = 1.5V Linearity Error (Note 10) Power-Supply Rejection Ratio mV ±10 VDUT_ = 1.5V, supplies independently varied over full range 5 mV mV/V AC CHARACTERISTICS (Note 11) Equivalent Input Bandwidth Terminated (Note 12) 500 High impedance (Note 13) 300 Propagation Delay 0.9 Prop-Delay Temperature Coefficient Prop-Delay Match, tLH to tHL Prop-Delay Skew, Comparators Within Package Prop-Delay Dispersions vs. Common-Mode Voltage (Note 14) Same edges (LH and HL) 2.2 MHz 3.1 ns 4 ps/°C 120 ps 200 ps 0 to 4.9V 20 -1.9V to +4.9V 30 ps Prop-Delay Dispersions vs. Overdrive VCHV_ = VCLV_ = 0.1V to 0.9V, VDUT_ = 1VP-P, tR = tF = 500ps, 10% to 90% relative to timing at 50% point 220 ps Prop-Delay Dispersions vs. Pulse Width 2ns to 23ns pulse width, relative to 12.5ns pulse width ±60 ps Prop-Delay Dispersions vs. Slew Rate 0.5V/ns to 2V/ns 50 ps 4 _______________________________________________________________________________________ Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators (VDD = +8V, VSS = -5V, VL = +3V, VCOMPHI = +1V, VCOMPLO = 0V, VLDV_ = 0V, LOAD EN LOW = LOAD EN HIGH = 0, TJ = +75°C. All temperature coefficients measured at TJ = +50°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS +3.6 V LOGIC OUTPUTS Reference Voltages COMPHI and COMPLO (Note 15) Output High Voltage Offset IOUT = 0mA, relative to COMPHI at VCOMPHI = 1V ±50 mV Output Low Voltage Offset IOUT = 0mA, relative to COMPLO at VCOMPLO = 0V ±50 mV Output Resistance ICHV_ = ICLV_ = ±10mA 0 40 Current Limit 20% to 80%, VCHV_ = 1VP-P, load = T-line, 50Ω, > 1ns Rise/Fall Time 50 60 Ω 25 mA 0.7 ns PASSIVE LOAD DC CHARACTERISTICS (RDUT_ ≥ 10MΩ) LDV_ Voltage Range -2.2 +5.2 V Gain 0.99 1.01 V/V Gain Temperature Coefficient 0.02 Offset %/°C ±100 Offset Temperature Coefficient Power-Supply Rejection Ratio PSRR mV 0.02 mV/°C 10 mV/V Output Resistance Tolerance—High Value IDUT_ = ±0.2mA, VLDV_ = 1.5V 7.125 7.5 7.875 kΩ Output Resistance Tolerance—Low Value IDUT_ = ±0.1mA, VLDV_ = 1.5V 1.90 2.0 2.10 kΩ Switch Resistance Variation Relative to 1.5V Maximum Output Current (Note 16) VLDV_ = -2V, VDUT_ = +5V ±4 VLDV_ = +5V, VDUT_ = -2V ±4 Linearity Error, Full Range 0 to 3V ±10 Full range ±30 Measured at -2.2V, +1.5V, and +5.2V (Note 16) % mA ±25 mV AC CHARACTERISTICS Settling Time, LDV_ to Output VLDV_ = -2V to +5V step, RDUT_ = 100kΩ (Note 17) 0.5 µs Output Transient Response VLDV_ = +1.5V, VDUT_ = -2V to +5V square wave at 1MHz, RDUT_ = 50Ω 20 ns _______________________________________________________________________________________ 5 MAX9972 ELECTRICAL CHARACTERISTICS (continued) MAX9972 Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators ELECTRICAL CHARACTERISTICS (continued) (VDD = +8V, VSS = -5V, VL = +3V, VCOMPHI = +1V, VCOMPLO = 0V, VLDV_ = 0V, LOAD EN LOW = LOAD EN HIGH = 0, TJ = +75°C. All temperature coefficients measured at TJ = +50°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PMU SWITCHES (FORCE_, SENSE_, PMU_) Voltage Range Force Switch Resistance Force Switch Compliance Force Switch Resistance Variation (Note 18) -2.2 VFORCE_ = 1.5V, IPMU_ = ±10mA VPMU_ = 6.2V, VFORCE_ set to make IFORCE_ = 30mA 25 VPMU_ = -3.2V, VFORCE_ set to make IFORCE_ = -30mA 25 0 to 3V ±10 ±30 700 Sense Switch Resistance Variation Relative to 1.3V, full range PMU_ Capacitance Force-and-sense switches open V 40 Ω mA Full range Sense Switch Resistance +5.2 1000 % 1300 Ω ±30 % 5 pF FORCE_ Capacitance 5 pF SENSE_ Capacitance 0.2 pF FORCE_ External Capacitance Allowable external capacitance 2 nF SENSE_ External Capacitance Allowable external capacitance 1 nF FORCE_ and SENSE_ Switching Speed Connect or disconnect 10 µs PMU_ Leakage FORCE EN_ = SENSE EN_ = 0, VFORCE_ = VSENSE_ = -2.2V to +5.2V ±0.5 ±5 nA 2 µA ±20 nA TOTAL FUNCTION DUT_ Leakage, High-Impedance Mode Load switches open, VDUT_ = +5.2V, VCLV_ = VCHV_ = -2.2V, VDUT_ = -2.2V, VCLV_ = VCHV_ = +5.2V, full range Leakage, Low-Leakage Mode Full range ±1 Low-Leakage Recovery Time (Note 19) 10 Term mode 2 High-impedance mode 5 Combined Capacitance µs pF Load Resistance (Note 20) 1 GΩ Load Capacitance (Note 20) 12 nF 6 _______________________________________________________________________________________ Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators (VDD = +8V, VSS = -5V, VL = +3V, VCOMPHI = +1V, VCOMPLO = 0V, VLDV_ = 0V, LOAD EN LOW = LOAD EN HIGH = 0, TJ = +75°C. All temperature coefficients measured at TJ = +50°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±100 µA VOLTAGE REFERENCE INPUTS (DHV_, DTV_, DLV_, DATA_, RCV_, CHV_, CLV_, LDV_, COMPHI, COMPLO) Input Bias Current Input Bias Current Temperature Coefficient Settling to Output 0.1% of full-scale step ±200 nA/°C 10 µs DIGITAL INPUTS (DATA_, RCV_, LD, DIN, SCLK, CS) Input High Voltage (Note 21) VL/2 + 0.2 +3.6 V Input Low Voltage (Note 21) -0.3 VL/2 0.2 V Input Bias Current DATA_, 100 LD, DIN, SCLK, CS 1 µA SERIAL DATA OUTPUT (DOUT) IOH = -1mA VL - 0.4 Output Low Voltage IOL = 1mA 0 Output Rise and Fall Time CL = 10pF Output High Voltage VL +0.4 1.1 V V ns SERIAL-INTERFACE TIMING (Note 22) SCLK Frequency 50 MHz SCLK Pulse-Width High tCH 10 ns SCLK Pulse-Width Low tCL 10 ns CS Low to SCLK High Setup tCSS0 3.5 ns SCLK High to CS Low Hold tCSH0 0 ns CS High to SCLK High Setup tCSS1 3.5 ns SCLK High to CS High Hold ns tCSH1 15 DIN to SCLK High Setup tDS 3.5 ns DIN to SCLK High Hold tDH 1 ns CS High to LOAD Low Hold tCSHLD 6 ns CS High Pulse Width tCSWH 20 ns LD Low Pulse Width tLDW 5 ns LD High to Any Activity SCLK Low to DOUT Delay VL Rising to CS Low 0 tDO CL = 10pF Power-on delay ns 5 40 ns 2 µs 3.00 V Temperature Coefficient +10 mV/°C Output Resistance 500 Ω TEMP SENSOR Nominal Voltage TJ = +27°C _______________________________________________________________________________________ 7 MAX9972 ELECTRICAL CHARACTERISTICS (continued) MAX9972 Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators ELECTRICAL CHARACTERISTICS (continued) (VDD = +8V, VSS = -5V, VL = +3V, VCOMPHI = +1V, VCOMPLO = 0V, VLDV_ = 0V, LOAD EN LOW = LOAD EN HIGH = 0, TJ = +75°C. All temperature coefficients measured at TJ = +50°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLIES Positive Supply Voltage VDD (Note 23) 7.6 8 8.4 V Negative Supply Voltage VSS (Note 23) -5.25 -5 -4.75 V 3.6 V 97 120 mA Logic Supply Voltage VL Positive Supply Current IDD fOUT = 0MHz Negative Supply Current ISS fOUT = 0MHz Logic Supply Current 2.3 IL 99 120 mA 0.15 0.30 mA 1.5 W Static Power Dissipation fOUT = 0MHz 1.3 Operating Power Dissipation fOUT = 100Mbps (Note 24) 1.4 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: Note 17: Note 18: Note 19: Note 20: Note 21: Note 22: Note 23: Note 24: 8 W All minimum and maximum specifications are 100% production tested except driver dynamic output current and driver/comparator propagation delays, which are guaranteed by design. All specifications are with DUT_ and PMU_ electrically isolated, unless otherwise noted. Nominal target value is 49.5Ω. Contact factory for alternate trim selections within the 45Ω to 55Ω range. Measured at 1.5V, relative to a straight line through 0 and 3V. Measured at end points, relative to a straight line through 0 and 3V. DUT_ is terminated with 50Ω to ground, VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V, unless otherwise specified. DATA_ and RCV_ logic levels are VHIGH = 2V, VLOW = 1V. Undershoot is any reflection of the signal back towards its starting voltage after it has reached 90% of its swing. Preshoot is any aberration in the signal before it reaches 10% of its swing. At the minimum voltage swing, undershoot is less than 20%. DHV_ and DLV_ references are adjusted to result in the specified swing. At this pulse width, the output reaches at least 90% of its nominal (DC) amplitude. The pulse width is measured at DATA_. With the exception of offset and gain/CMRR tests, reference input values are calibrated for offset and gain. Relative to a straight line through 0 and 3V. Unless otherwise noted, all propagation delays are measured at 40MHz, VDUT_ = 0 to 1V, VCHV_ = VCLV_ = +0.5V, tR = tF = 500ps, ZS = 50Ω, driver in term mode with VDTV_ = +0.5V. Comparator outputs are terminated with 50Ω to GND. Measured from VDUT_ crossing calibrated CHV_/CLV_ threshold to midpoint of nominal comparator output swing. Terminated is defined as driver in drive mode and set to zero volts. High impedance is defined as driver in high-impedance mode. VDUT_ = 200mVP-P. Propagation delay is compared to a reference time at 1.5V. The comparator meets all its timing specifications with the specified output conditions when the output current is less than 10mA, VCOMPHI > VCOMPLO, and VCOMPHI - VCOMPLO ≤ 1V. Higher voltage swings are valid but AC performance may degrade. The maximum comparator output swing is (COMPHI - COMPLO) ≤ 1V when the output is terminated with a 50Ω resistor to termination voltage VTERM, where COMPHI ≥ VTERM ≥ COMPLO. LOAD EN LOW = LOAD EN HIGH = 1. Waveform settles to within 5% of final value into load 100kΩ. IPMU_ = ±2mA at VFORCE_ = -2.2V, +1.5V, and +5.2V. Percent variation relative to value calculated at VFORCE_ = +1.5V. Time to return to the specified maximum leakage after a 3V, 4V/ns step at DUT_. Load at end of 2ns transmission line; for stability only, AC performance may be degraded. The driver meets all of its timing specifications over the specified digital input voltage range. Timing characteristics with VL = 3V. Specifications are simulated and characterized over the full power-supply range. Production tests are performed with power supplies at typical values. All channels driven at 3VP-P, load = 2ns, 50Ω transmission line terminated with 3pF. _______________________________________________________________________________________ Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators MAX9971 toc02 MAX9971 toc01 VDLV_ = 0 RL = 50Ω VDHV_ = 3V VDHV_ = 200mV VDHV_ = 100mV VDHV_ = 1V 0 0 VDHV_ = 3V VDHV_ = 1V 0 4.5ns CABLE t = 2.0ns/div DRIVER 1VP-P, 150Mbps SIGNAL RESPONSE DRIVER 1VP-P, 400Mbps SIGNAL RESPONSE DRIVER 3VP-P, 100Mbps SIGNAL RESPONSE VDUT_ = 250mV/div VDUT_ = 100mV/div VDUT_ = 100mV/div MAX9971 toc05 MAX9971 toc06 t = 2.0ns/div MAX9971 toc04 t = 2.0ns/div VDLV_ = 0 VDHV_ = 1V RL = 50Ω 0 0 VDLV_ = 0 VDHV_ = 1V RL = 50Ω VDLV_ = 0 VDHV_ = 3V RL = 50Ω 0 t = 2ns/div t = 1ns/div t = 2.5ns/div DRIVER LINEARITY ERROR vs. OUTPUT VOLTAGE DRIVER DC CURRENT-LIMIT AND OVERVOLTAGE RESPONSE DRIVER 3V TRAILING-EDGE TIMING ERROR vs. PULSE WIDTH VDHV_ = 1.5V 80 60 IDUT_ (mA) 0.5 0 -0.5 20 0 -20 -1.0 -40 -1.5 -60 -2.0 -80 -2.5 -1.5 -0.5 0.5 1.5 VDUT_ (V) 2.5 3.5 4.5 5.5 -50 -100 -150 NEGATIVE PULSE -200 -250 -100 -2.5 POSITIVE PULSE 0 TIMING ERROR (ps) 40 1.0 50 MAX9971 toc09 1.5 100 MAX9971 toc08 DUT_ = DTV_ VDLV_ = 1.5V VDHV_ = 1.5V 2.0 MAX9971 toc15 2.5 LINEARITY ERROR (mV) VDLV_ = 0 RL = 500Ω CL = 0.1pF VDUT_ = 500mV/div VDHV_ = 500mV VDUT_ = 300mV/div VDUT_ = 50mV/div VDLV_ = 0 RL = 50Ω DRIVER LARGESIGNAL RESPONSE INTO 500Ω DRIVER LARGESIGNAL RESPONSE MAX9971 toc03 DRIVER SMALLSIGNAL RESPONSE NORMALIZED AT PW = 12.5ns, PERIOD = 25ns, VDHV_ = 3V, VDLV_ = 0 -300 -6 -3 0 3 VDUT_ (V) 6 9 3 4 5 6 7 8 9 10 11 12 13 PULSE WIDTH (ns) _______________________________________________________________________________________ 9 MAX9972 Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) DRIVER TIME DELAY vs. COMMON-MODE VOLTAGE VDUT_ = 200mV/div VDUT_ = 200mV/div -20 DLV_ TO DTV_ DLV_ TO HIGH IMPEDANCE 0 NORMALIZED AT VCM = 1.5V 0.5 1.0 1.5 2.0 2.5 COMMON-MODE VOLTAGE (V) 3.0 DRIVER LINEARITY ERROR vs. OUTPUT VOLTAGE DUT_ = DHV_ VDLV_ = 1.5V VDTV_ = 1.5V 2.0 1.0 0.5 0 -0.5 -1.0 DRIVER LINEARITY ERROR vs. OUTPUT VOLTAGE DRIVER LINEARITY ERROR vs. OUTPUT VOLTAGE DUT_ = DLV_ VDHV_ = 1.5V VDTV_ = 1.5V 2.0 1.5 LINEARITY ERROR (mV) 1.5 t = 2ns/div 2.5 MAX9971 toc13 2.5 t = 2ns/div 2.5 1.0 0.5 0 -0.5 -1.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -1.5 -1.5 -2.0 -2.0 -2.0 -2.5 -2.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 0.5 1.5 2.5 3.5 4.5 5.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 VDUT_ (V) VDUT_ (V) VDUT_ (V) CROSSTALK, DUT_ DRIVEN BY DHV_ WITH DLV_ VARIED CROSSTALK, DUT_ DRIVEN BY DHV_ WITH DTV_ VARIED CROSSTALK, DUT_ DRIVEN BY DLV_ WITH DHV_ VARIED 60 20 0 -20 VDHV_ = 3V VDLV_ = 0 60 VDUT_ ERROR (µV) 40 80 100 40 20 0 -20 60 20 0 -20 -40 -40 -60 -60 -60 -80 -80 NORMALIZED AT VDLV_ = 0 -80 NORMALIZED AT VDTV_ = 1.5V -100 -2.5 -1.5 -0.5 0.5 1.5 VDLV_ (V) 2.5 3.5 4.5 5.5 5.5 40 -40 -100 VDTV_ = 1.5V VDLV_ = 0 80 VDUT_ ERROR (µV) VDHV_ = 3V VDTV_ = 1.5V MAX9971 toc17 100 MAX9971 toc16 100 80 -2.5 -2.5 -1.5 -0.5 5.5 DUT_ = DTV_ VDLV_ = 1.5V VDHV_ = 1.5V 2.0 LINEARITY ERROR (mV) 0 RL = 50Ω RL = 50Ω -60 MAX9971 toc14 -40 LINEARITY ERROR (mV) 0 MAX9971 toc15 0 MAX9971 toc18 FALLING EDGE 20 10 MAX9971 toc12 MAX9971 toc11 DHV_ TO DTV_ DHV_ TO HIGH IMPEDANCE 40 TIME DELAY (ps) MAX9971 toc10 RISING EDGE 60 DRIVE-TO-HIGH-IMPEDANCE TRANSITION DRIVE-TO-TERM TRANSITION 80 VDUT_ ERROR (µV) MAX9972 Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators NORMALIZED AT VDHV_ = 3V -100 -2.5 -1.5 -0.5 0.5 1.5 VDTV_ (V) 2.5 3.5 4.5 5.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 VDHV_ (V) ______________________________________________________________________________________ 3.5 4.5 5.5 Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators 60 20 0 -20 40 20 0 -20 60 20 0 -20 -40 -40 -60 -60 -60 -80 -80 NORMALIZED AT VDTV_ = 1.5V -80 NORMALIZED AT VDHV_ = 3V 0.5 1.5 2.5 3.5 4.5 5.5 NORMALIZED AT VDLV_ = 0 -100 -100 -2.5 -1.5 -0.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 -2.5 -1.5 -0.5 5.5 0.5 1.5 2.5 3.5 4.5 VDHV_ (V) VDLV_ (V) DRIVER GAIN vs. TEMPERATURE DRIVER OFFSET vs. TEMPERATURE COMPARATOR RESPONSE TO 0 TO 3V SIGNAL 1.0006 MAX9971 toc23 MAX9971 toc22 5 4 VCHV_ = VCLV_ = 1.5V, RL = 50Ω VCOMPHI = 1V, VCOMPLO = 0 OFFSET (mV) 1.0002 1.0000 VCMP_ _ = 100mV/div 3 1.0004 5.5 MAX9971 toc24 VDTV_ (V) 1.0008 GAIN (V/V) 40 -40 -100 VDHV_ = 3V VDTV_ = 1.5V 80 VDUT_ ERROR (µV) 40 VDUT_ ERROR (µV) VDUT_ ERROR (µV) 60 VDTV_ = +1.5V VDLV_ = -1.5V 80 100 MAX9971 toc20 VDHV_ = 3V VDLV_ = 0 80 100 MAX9971 toc19 100 CROSSTALK, DUT_ DRIVEN BY DTV_ WITH DLV_ VARIED CROSSTALK, DUT_ DRIVEN BY DTV_ WITH DHV_ VARIED MAX9971 toc21 CROSSTALK, DUT_ DRIVEN BY DLV_ WITH DTV_ VARIED 2 1 0 -1 0.9998 -2 NORMALIZED AT TJ = +85°C NORMALIZED AT TJ = +85°C -3 70 80 90 100 80 90 100 COMPARATOR WAVEFORM TRACKING 400 MAX9971 toc25 300 TIMING VARIATION (ps) 0.10 0.05 OFFSET (mV) 70 COMPARATOR OFFSET vs. COMMON-MODE VOLTAGE 0.15 0 -0.05 -0.10 -0.15 -0.20 -0.30 60 TEMPERATURE (°C) 0.20 -0.25 50 TEMPERATURE (°C) VDUT_ FALLING COMPARATOR TIMING VARIATION vs. PULSE WIDTH VDUT_ RISING 200 100 0 -100 -200 NORMALIZED AT VCM = 1.5V OTHER COMPARATOR REFERENCE = -2.5V NORMALIZED AT 50% REFERENCE VDUT_ = 0 TO 1V PULSE 0.5 1.5 2.5 3.5 COMMON-MODE VOLTAGE (V) 4.5 5.5 30 10 -10 -30 -50 -70 -90 -130 -400 -2.5 -1.5 -0.5 50 -110 -300 -0.35 t = 2.0ns/div MAX9971 toc27 60 MAX9971 toc26 50 TRAILING-EDGE ERROR (ps) 0.9996 NORMALIZED AT PW = 10ns -150 0 20 40 60 REFERENCE LEVEL (%) 80 100 1 2 3 4 5 6 7 8 9 10 PULSE WIDTH (ns) ______________________________________________________________________________________ 11 MAX9972 Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) COMPARATOR TIMING VARIATION vs. INPUT SLEW RATE VDUT_ RISING 0 -10 -20 -30 MAX9971 toc30 INPUT SLEW RATE = 6V/ns TERM MODE, VDTV_ = 0 TO 1V 100 50 0 OFFSET (µV) VDUT_ FALLING 150 MAX9971 toc29 MAX9971 toc28 50 40 30 20 10 COMPARATOR OFFSET vs. TEMPERATURE COMPARATOR RESPONSE vs. HIGH SLEW-RATE OVERDRIVE VCMP_ _ = 200mV/div TIMING VARIATION (ps) 60 -50 -100 -150 -200 -250 -300 -40 NORMALIZED AT SR = 2V/ns VCOMPHI = 1V, VCOMPLO = 0, RL = 50Ω -50 -60 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -350 VCOMPHI = 1V, VCOMPLO = 0, RCOMP_ = 50Ω NORMALIZED AT TJ = +75°C -400 4.5 5.0 50 t = 2ns/div 60 SLEW RATE (V/ns) 70 80 100 90 TEMPERATURE (°C) 0.1 0 -0.1 IDUT_ (µA) 0µA 0µA MAX9971 toc33 MAX9971 toc32 0.2 10µA IDUT_ = 2µA/div IDUT_ = 2µA/div 10µA HIGH-IMPEDANCE LEAKAGE AT DUT_ vs. DUT_ VOLTAGE LOW LEAKAGE TO DRIVE 1V TRANSITION MAX9971 toc31 DRIVE 1V TO LOW-LEAKAGE TRANSITION -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 t = 2.5µs/div -2.5 -1.5 -0.5 0.5 t = 100ns/div 1.5 2.5 3.5 4.5 5.5 VDUT_ (V) LOW-LEAKAGE CURRENT vs. DUT_VOLTAGE 107 MAX9971 toc36 1.6 -104 MAX9971 toc35 108 MAX9971 toc34 1.7 -105 106 IDD (mA) 1.4 1.3 1.2 -106 105 ISS (mA) 1.5 104 103 1.1 -107 -108 102 1.0 -109 101 0.9 0.8 -110 100 -2.5 -1.5 -0.5 0.5 1.5 VDUT_ (V) 12 ISS SUPPLY CURRENT vs.TEMPERATURE IDD SUPPLY CURRENT vs.TEMPERATURE 1.8 IDUT_ (nA) MAX9972 Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators 2.5 3.5 4.5 5.5 50 60 70 80 TEMPERATURE (°C) 90 100 50 60 70 80 TEMPERATURE (°C) ______________________________________________________________________________________ 90 100 Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators 100 80 60 40 7400 0 7100 VDLV_ = +1.5V 60 70 80 90 100 MAX9971 toc39 VDLV_ = -2.2V VDLV_ = +5.2V 2050 2000 1950 1900 VDLV_ = +1.5V 1850 1800 7000 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 -2.5 -1.5 -0.5 5.5 0.5 1.5 2.5 3.5 4.5 TEMPERATURE (°C) VOLTAGE (V) VOLTAGE (V) PMU_ FORCE_ SWITCH RESISTANCE vs. FORCE_ CURRENT PMU_ FORCE_ SWITCH RESISTANCE vs. FORCE_ CURRENT PMU_ FORCE_ SWITCH RESISTANCE vs. FORCE_ CURRENT SWITCH RESISTANCE (Ω) 39 42 36 33 30 27 24 VPMU_ = 1.5V 45 39 42 SWITCH RESISTANCE (Ω) VPMU_ = 5.2V 36 33 30 27 24 36 33 30 27 24 21 21 18 18 18 15 15 10 20 30 40 50 FORCE_ CURRENT (mA) VPMU_ = -2.2V 39 21 -50 -40 -30 -20 -10 0 5.5 MAX9971 toc42 45 MAX9971 toc40 45 MAX9971 toc41 50 SWITCH RESISTANCE (Ω) 7500 7200 DUT_ = DLV_ 2150 2100 VDLV_ = +5.2V 7600 20 2200 VDLV_ = -2.2V 7700 7300 -20 DUT_ = DLV_ RESISTANCE (Ω) 7800 RESISTANCE (Ω) 120 7900 MAX9971 toc38 140 OFFSET (µV) 8000 MAX9971 toc37 160 42 PASSIVE LOAD LOW RESISTOR vs. VOLTAGE PASSIVE LOAD HIGH RESISTOR vs. VOLTAGE PASSIVE LOAD OFFSET vs. TEMPERATURE 15 -50 -40 -30 -20 -10 0 10 20 30 40 50 FORCE_ CURRENT (mA) -50 -40 -30 -20 -10 0 10 20 30 40 50 FORCE_ CURRENT (mA) ______________________________________________________________________________________ 13 MAX9972 Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators MAX9972 Pin Description 14 PIN NAME FUNCTION 1 DATA1 2 RCV1 Channel 1 Multiplexer Control Input. Sets channel 1 mode to drive or receive. See Table 1 and Figure 2. 3, 8, 13, 18, 51 GND Analog Ground 4 CMPH1 Channel 1 High-Side Comparator Output 5 CMPL1 Channel 1 Low-Side Comparator Output 6 DATA2 Channel 2 Multiplexer Control Input. Selects driver 2 input from DHV2 or DLV2 in drive mode. See Table 1 and Figure 2. 7 RCV2 Channel 1 Multiplexer Control Input. Selects driver 1 input from DHV1 or DLV1 in drive mode. See Table 1 and Figure 2. Channel 2 Multiplexer Control Input. Sets channel 2 mode to drive or receive. See Table 1 and Figure 2. 9 CMPH2 Channel 2 High-Side Comparator Output 10 CMPL2 Channel 2 Low-Side Comparator Output 11 CMPL3 Channel 3 Low-Side Comparator Output 12 CMPH3 14 RCV3 15 DATA3 Channel 3 High-Side Comparator Output Channel 3 Multiplexer Control Input. Sets channel 3 mode to drive or receive. See Table 1 and Figure 2. Channel 3 Multiplexer Control Input. Selects driver 3 input from DHV3 or DLV3 in drive mode. See Table 1 and Figure 2. 16 CMPL4 Channel 4 Low-Side Comparator Output 17 CMPH4 Channel 4 High-Side Comparator Output 19 RCV4 Channel 4 Multiplexer Control Input. Sets channel 4 mode to drive or receive. See Table 1 and Figure 2. Channel 4 Multiplexer Control Input. Selects driver 4 input from DHV4 or DLV4 in drive mode. See Table 1 and Figure 2. 20 DATA4 21 DHV4 Channel 4 Driver High Voltage Input 22 DLV4 Channel 4 Driver Low Voltage Input 23 DTV4 Channel 4 Driver Termination Voltage Input 24 CHV4 Channel 4 Threshold Voltage Input for High-Side Comparator 25 CLV4 Channel 4 Threshold Voltage Input for Low-Side Comparator 26 DHV3 Channel 3 Driver High Voltage Input 27 DLV3 Channel 3 Driver Low Voltage Input 28 DTV3 Channel 3 Driver Termination Voltage Input 29 CHV3 Channel 3 Threshold Voltage Input for High-Side Comparator 30 CLV3 Channel 3 Threshold Voltage Input for Low-Side Comparator 31 DGND Digital Ground Connection 32 DOUT Serial-Interface Data Output 33 LD Load Input. Latches data from the serial input register to the control register on rising edge. Transparent when low. 34 DIN 35 SCLK Serial Clock Serial-Interface Data Input 36 CS Chip Select 37 SENSE4 Channel 4 PMU Sense Connection 38 FORCE4 Channel 4 PMU Force Connection ______________________________________________________________________________________ Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators PIN NAME 39 SENSE3 Channel 3 PMU Sense Connection FUNCTION 40 FORCE3 Channel 3 PMU Force Connection 41 TEMP Temperature Sensor Output 42, 47, 52, 56, 60 VDD Positive Power-Supply Input 43 DUT4 Channel 4 Device-Under-Test Connection. Driver, comparator, and load I/O node for channel 4. 44 PMU4 Channel 4 Parametric Measurement Connection. PMU switch I/O node for channel 4. 45, 50, 53, 57 VSS Negative Power-Supply Input 46 VL 48 DUT3 Channel 3 Device-Under-Test Connection. Driver, comparator, and load I/O node for channel 3. Logic Power-Supply Input 49 PMU3 Channel 3 Parametric Measurement Connection. PMU switch I/O node for channel 3. 54 PMU2 Channel 2 Parametric Measurement Connection. PMU switch I/O node for channel 2. 55 DUT2 Channel 2 Device-Under-Test Connection. Driver, comparator, and load I/O node for channel 2. 58 PMU1 Channel 1 Parametric Measurement Connection. PMU switch I/O node for channel 1. 59 DUT1 Channel 1 Device-Under-Test Connection. Driver, comparator, and load I/O node for channel 1. 61 FORCE2 Channel 2 PMU Force Connection 62 SENSE2 Channel 2 PMU Sense Connection 63 FORCE1 Channel 1 PMU Force Connection 64 SENSE1 Channel 1 PMU Sense Connection 65 COMPLO Comparator Output-Low Voltage Reference Input 66 COMPHI Comparator Output-High Voltage Reference Input 67 LDV4 Channel 4 Load Voltage Input 68 LDV3 Channel 3 Load Voltage Input 69 LDV2 Channel 2 Load Voltage Input 70 LDV1 Channel 1 Load Voltage Input 71 CLV2 Channel 2 Threshold Voltage Input for Low-Side Comparator 72 CHV2 Channel 2 Threshold Voltage Input for High-Side Comparator 73 DTV2 Channel 2 Driver Termination Voltage Input 74 DLV2 Channel 2 Driver Low Voltage Input 75 DHV2 Channel 2 Driver High Voltage Input 76 CLV1 Channel 1 Threshold Voltage Input for Low-Side Comparator 77 CHV1 Channel 1 Threshold Voltage Input for High-Side Comparator 78 DTV1 Channel 1 Driver Termination Voltage Input 79 DLV1 Channel 1 Driver Low Voltage Input 80 DHV1 — EP Channel 1 Driver High Voltage Input Exposed Pad. Leave unconnected or connect to ground. ______________________________________________________________________________________ 15 MAX9972 Pin Description (continued) MAX9972 Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators ONE OF FOUR IDENTICAL CHANNELS SHOWN MAX9972 DHV_ 50Ω DTV_ MULTIPLEXER BUFFER DUT_ 0 LLEAK DLV_ HIGH IMPEDANCE 0 DATA_ HIGH-IMPEDANCE LOGIC RCV_ TERM CHV_ CMPH_ CMPL_ SEE TABLE 3 CLV_ 7.5kΩ LDV_ 2.0kΩ 30Ω LOAD EN HIGH 0 LOAD EN LOW 0 FORCE_ FORCE EN 0 PMU_ 1kΩ SENSE_ SENSE EN COMMON TO ALL FOUR CHANNELS COMPHI COMPLO LD DOUT SERIAL INTERFACE TERM VL LLEAK VSS SENSE EN FORCE EN LOAD EN LOW LOAD EN HIGH Figure 1. Block Diagram 16 TEMP VDD CS SCLK DIN 0 ______________________________________________________________________________________ GND DGND Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators The MAX9972 is a four-channel, pin-electronics IC for automated test equipment that includes, for each channel, a three-level pin driver, a window comparator, a passive load, and a Kelvin instrument connection (Figure 1). All functions feature a -2.2V to +5.2V operating range and the drivers include both high-impedance and active-termination (3rd-level drive) modes. The comparators feature programmable output voltages, allowing optimization for different CMOS interface standards. The loads have selectable output resistance for optimizing DUT current loading. The Kelvin paths allow accurate connection of an instrument with ±25mA source/sink capability. Additionally, the MAX9972 offers a low-leakage mode that reduces DUT_ leakage current to less than 20nA. Each of the four channels feature single-ended CMOScompatible inputs, DATA_ and RCV_, for control of the driver signal path (Figure 2). The MAX9972 modal operation is programmed through a 3-wire, low-voltage CMOS-compatible serial interface. Output Driver The driver input is a high-speed multiplexer that selects one of three voltage inputs: DHV_, DLV_, or DTV_. This switching is controlled by high-speed inputs DATA_ and RCV_, and mode-control bit TERM (Table 1). DATA_ and RCV_ are single-ended inputs with threshold levels equal to VL/2. Each channel’s threshold levels are independently generated to minimize crosstalk. DUT_ can be toggled at high speed between the buffer output and high-impedance mode, or it can be placed into low-leakage mode (Figure 2, Table 1). High-speed input RCV_ and mode-control bits TERM and LLEAK control these modes. In high-impedance mode, the bias current at DUT_ is less than 2µA over the -2.2V to +5.2V range, while the node maintains its ability to track high-speed signals. In low-leakage mode, the bias current at DUT_ is further reduced to less than 20nA, and signal tracking slows. The nominal driver output resistance is 50Ω. Custom resistance values from 45Ω to 51Ω are possible; consult factory for further information. Table 1. Driver Channel Control Signals EXTERNAL CONNECTIONS INTERNAL CONTROL BITS RCV_ DATA_ TERM DRIVER OUTPUT DRIVER MODE LLEAK 0 0 X 0 DUT_ = DLV_ Drive 0 1 X 0 DUT_ = DHV_ Drive 1 X 0 0 High Impedance Receive 1 X 1 0 DUT_ = DTV_ Receive X X X 1 Low Leak Low Leakage DLV_ DHV_ 0 0 BUFFER 1 DTV_ 50Ω 0 DUT_ 1 LLEAK DATA_ RCV_ COMPARATORS AND LOAD TERM HIGH IMPEDANCE MAX9972 Figure 2. Multiplexer and Driver Channel ______________________________________________________________________________________ 17 MAX9972 Detailed Description MAX9972 Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators Comparators The MAX9972 provides two independent high-speed comparators for each channel. Each comparator has one input connected internally to DUT_ and the other input connected to either CHV_ or CLV_ (see Figure 1). Comparator outputs are a logical result of the input conditions, as indicated in Table 2. The comparator output voltages are easily interfaced to a wide variety of logic standards. Use buffered inputs COMPHI and COMPLO to set the high and low output voltages. For correct operation, COMPHI should be greater than or equal to COMPLO. The comparator 50Ω output impedance provides source termination (Figure 3). Passive Load The MAX9972 channels each feature a passive load consisting of a buffered input voltage, LDV_, connected to DUT_ through two resistive paths (Figure 1). Each path connects to DUT_ individually by a switch controlled through the serial interface. Programming options include none (load disconnected), either, or both paths connected. The loads facilitate fast open/short testing in conjunction with the comparator, and pullup of open-drain DUT_ outputs. Table 2. Comparator Logic DUT_ > CHV_ DUT_ > CLV_ CMPH_ CMPL_ 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 MAX9972 COMPHI CHV_ 50Ω CMPH_ DUT_ Parametric Switches Each of the four MAX9972 channels provides forceand-sense paths for connection of a PMU or other DC resource to the device-under-test (Figure 1). Each force-and-sense switch is independently controlled though the serial interface providing maximum application flexibility. PMU_ and DUT_ are provided on separate pins allowing designs that do not require the parametric switch feature to avoid the added capacitance of PMU_. It also allows PMU_ to connect to DUT_ either directly or with an impedance-matching network. Low-Leakage Mode, LLEAK Asserting LLEAK through the serial port places the MAX9972 into a very-low-leakage state (see the Electrical Characteristics table). This mode is convenient for making IDDQ and PMU measurements without the need for an output disconnect relay. LLEAK control is independent for each channel. When DUT_ is driven with a high-speed signal while LLEAK is asserted, the leakage current momentarily increases beyond the limits specified for normal operation. The low-leakage recovery specification in the Electrical Characteristics table indicates device behavior under this condition. 18 50Ω CMPL_ CLV_ COMPLO Figure 3. Complementary 50Ω Comparator Outputs Table 3. Passive Load Resistance Values HIGH RESISTOR (kΩ) LOW RESISTOR (kΩ) 7.5 2 Temperature Monitor Each device supplies a single temperature output signal, TEMP, that asserts a nominal 3.43V output voltage at a +70°C (343K) die temperature. The output voltage increases proportionately with temperature at a rate of 10mV/°C. The temperature sensor output impedance is 500Ω, typical. ______________________________________________________________________________________ Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators 9 8 7 6 5 4 3 2 TE RM CH 1 10 LO AD EN HII GH LO AD EN LO W FO RC EE N SE NS EE N LL EA K CH 2 11 UN US ED CH 3 DIN CH 4 SCLK UN US ED The latches contain the six mode bits for each channel of the device. The mode bits, in conjunction with external inputs DATA_ and RCV_, manage the features of each channel. Transfer data asynchronously from the input registers to the channel registers by forcing LD low. With LD always low, data transfer on the rising edge of CS. 1 0 ENABLE CS LD MAX9972 QUAD F/F QUAD F/F 0–5 8 D 0–5 Q ENABLE D 9 6 10 ENABLE 6 D MODE BITS CHANNEL 1 0–5 Q D 11 ENABLE LOAD LOAD QUAD F/F QUAD F/F 0–5 Q Q ENABLE 6 6 LOAD LOAD MODE BITS CHANNEL 2 MODE BITS CHANNEL 3 MODE BITS CHANNEL 4 Figure 4. Serial Interface Table 4. Control Register Bit Functions BIT STATE 0 1 POWER-UP STATE Term Mode Control High Impedance Term Mode 0 LLEAK Assert Low-Leakage Mode Term Mode Low Leakage 0 SENSE EN Enable Sense Switch Disabled Enabled 0 Enable Force Switch Disabled Enabled 0 BIT NAME FUNCTION 0 TERM 1 2 3 FORCE EN 4 LOAD EN LOW Enable Low Load Resistor Disabled Enabled 0 5 LOAD EN HIGH Enable High Load Resistor Disabled Enabled 0 6 — Unused X X 0 7 — Unused X X 0 8 CH1 Update Channel 1 Control Register Disabled Enabled 1 9 CH2 Update Channel 2 Control Register Disabled Enabled 1 10 CH3 Update Channel 3 Control Register Disabled Enabled 1 11 CH4 Update Channel 4 Control Register Disabled Enabled 1 ______________________________________________________________________________________ 19 MAX9972 Serial Interface and Device Control A CMOS-compatible serial interface controls the MAX9972 modes (Figure 4). Control data flow into a 12bit shift register (LSB first) and are latched when CS is taken high. Data from the shift register are then loaded to the per-channel control latches as determined by bits D8–D11, and indicated in Figure 4 and Table 4. MAX9972 Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators tCH SCLK tCL tCSSO tCSS1 tCSHO tCSH1 CS tCSWH tDH tDS DIN D0 D1 D2 D3 D4 D5 D10 D11 D10 LAST D11 LAST tDO DOUT D0 LAST D1 LAST D2 LAST D3 LAST D4 LAST D5 LAST D0 tCSHLD tLDW LOAD Figure 5. Serial-Interface Timing Heat Removal With adequate airflow, no external heat sinking is needed under most operating conditions. If excess heat must be dissipated through the exposed pad, solder it to circuit board copper. The exposed pad must be either left unconnected, isolated, or connected to ground. Power Minimization To minimize power consumption, activate only the needed channels. Each channel placed in low-leakage mode saves approximately 240mW. 20 Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 80 TQFP-EP C80E+4 21-0115 90-0152 ______________________________________________________________________________________ Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators DHV1 DLV1 DTV1 CHV1 CLV1 DHV2 DLV2 DTV2 CHV2 CLV2 LDV1 LDV2 LDV3 LDV4 COMPHI COMPLO SENSE1 FORCE1 SENSE2 FORCE2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 + DATA1 1 60 VDD RCV1 2 59 DUT1 GND 3 58 PMU1 CMPH1 4 57 VSS CMPL1 5 56 VDD DATA2 6 55 DUT2 RCV2 7 54 PMU2 GND 8 53 VSS CMPH2 9 52 VDD CMPL2 10 51 GND CMPL3 11 50 VSS CMPH3 12 49 PMU3 GND 13 48 DUT3 RCV3 14 47 VDD DATA3 15 46 VL CMPL4 16 45 VSS CMPH4 17 44 PMU4 GND 18 43 DUT4 RCV4 19 42 VDD DATA4 20 41 TEMP MAX9972 CHV4 CLV4 DHV3 DLV3 DTV3 CHV3 32 33 34 35 36 37 38 39 40 FORCE3 DTV4 31 SENSE3 DLV4 30 FORCE4 29 SENSE4 28 CS 27 SCLK 26 DIN 25 LD 24 DOUT 23 DGND 22 CLV3 21 DHV4 EP TQFP ______________________________________________________________________________________ 21 MAX9972 Pin Configuration MAX9972 Quad, Ultra-Low-Power, 300Mbps ATE Drivers/Comparators Revision History REVISION NUMBER REVISION DATE 0 6/06 Initial release 1 7/09 Changed driver offset max value in Electrical Characteristics table and removed all references to MAX9971 2 4/10 Added soldering temperature to Absolute Maximum Ratings, updated SCLK to DOUT specification in Electrical Characteristics table, and replaced Figure 5 DESCRIPTION PAGES CHANGED — 1–22 2, 7, 20 3 9/10 Updated Absolute Maximum Ratings and Figure 1 2, 16 4 12/10 Updated Electrical Characteristics table and notes 3, 4, 7, 8 5 1/11 Changed maximum DC drive current in Electrical Characteristics table to reflect actual circuit operation 6 3/11 Narrowed down product offerings and modified exposed die pad connection description; added CS high pulse width to Electrical Characteristics table 2 1, 2, 4, 5, 7, 15, 17, 18, 20 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.